[llvm] [RISCV] Allow tail memcmp expansion (PR #121460)

[Philip Reames via llvm-commits]

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@@ -2565,9 +2565,12 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
   Options.AllowOverlappingLoads = true;
   Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
   Options.NumLoadsPerBlock = Options.MaxNumLoads;
-  if (ST->is64Bit())
+  if (ST->is64Bit()) {
     Options.LoadSizes = {8, 4, 2, 1};
-  else
+    Options.AllowedTailExpansions = {3, 5, 6};
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preames wrote:

(No action needed at the moment, recording thoughts for later reference)

Any reason to not support 7?  It would be formed as 4 + 2 + 1, which is then transformed to 4 + 4.  Ah, so then we're merging two legal stores into a wider one.  The existing code probably could do this, but AArch64 doesn't, and exploring that in a separate commit seems reasonable.  

https://github.com/llvm/llvm-project/pull/121460