[llvm] [CodeGen][Spill2Reg] Initial patch (PR #118832)

[via llvm-commits]

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@@ -2284,6 +2294,52 @@ class TargetInstrInfo : public MCInstrInfo {
     llvm_unreachable("unknown number of operands necessary");
   }
 
+  /// \Returns true if a spill/reload of \p Reg can be handled by Spill2Reg.
+  virtual bool isLegalToSpill2Reg(Register Reg, const TargetRegisterInfo *TRI,
+                                  const MachineRegisterInfo *MRI) const {
+    llvm_unreachable(
+        "Target didn't implement TargetInstrInfo::isLegalToSpill2Reg!");
+  }
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vporpo wrote:

I think most of them have to do with Instructions rather than registers, with the exception of `isLegalToSpill2Reg(), and `getVectorRegisterClassForSpill2Reg()`. I will move these to TargetRegisterInfo.
- `isStoreToStackSlotMO()` inspects an instruction
- `targetSupportsSpill2Reg()` could be placed in either file as it does not check an instruction or register
- `isSpill2RegProfitable()` checks the instruction sequence
- `spill2RegInsertToVectoReg()` emits instructions
- `spill2RegExtractFromVectorReg()` emits instructions

https://github.com/llvm/llvm-project/pull/118832