[llvm] [CodeGen][Spill2Reg] Initial patch (PR #118832)

[via llvm-commits]

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@@ -2284,6 +2294,52 @@ class TargetInstrInfo : public MCInstrInfo {
     llvm_unreachable("unknown number of operands necessary");
   }
 
+  /// \Returns true if a spill/reload of \p Reg can be handled by Spill2Reg.
+  virtual bool isLegalToSpill2Reg(Register Reg, const TargetRegisterInfo *TRI,
+                                  const MachineRegisterInfo *MRI) const {
+    llvm_unreachable(
+        "Target didn't implement TargetInstrInfo::isLegalToSpill2Reg!");
+  }
+
+  virtual bool targetSupportsSpill2Reg(const TargetSubtargetInfo *STI) const {
+    return false;
+  }
+
+  virtual const TargetRegisterClass *
+  getVectorRegisterClassForSpill2Reg(const TargetRegisterInfo *TRI,
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vporpo wrote:

Makes sense, done. 

There are a couple more of these, like `spill2RegExtractFromVectorReg()`. I am thinking of using the term `Host` instead of `Vector` to describe the register used by spill2reg, what do you think?

https://github.com/llvm/llvm-project/pull/118832