[llvm] [Xtensa] Implement Windowed Register Option. (PR #121118)

[Min-Yih Hsu via llvm-commits]

================
@@ -678,3 +678,124 @@ let isReturn = 1, isTerminator = 1,
     let t = 0;
   }
 }
+
+//===----------------------------------------------------------------------===//
+// Windowed instructions
+//===----------------------------------------------------------------------===//
+
+def ENTRY : BRI12_Inst<0x06, 0x3, 0x0, (outs), (ins AR:$s, entry_imm12:$imm),
+                     "entry\t$s, $imm", []>, Requires<[HasWindowed]> {
+  bits<15> imm;
+
+  let imm12{11-0} = imm{14-3};
+  let Defs = [SP];
+}
+
+let isCall = 1, Defs = [A0] in {
+  def CALL4 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset),
+                      "call4\t$offset", []>, Requires<[HasWindowed]> {
+    let n = 1;
+  }
+
+  def CALL8 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset),
+                       "call8\t$offset", []>, Requires<[HasWindowed]> {
+    let n = 2;
+  }
+
+  def CALL12 : CALL_Inst<0x05, (outs), (ins pcrel32call:$offset),
+                        "call12\t$offset", []>, Requires<[HasWindowed]> {
+    let n = 3;
+  }
+
+  def CALLX4 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),
+                         "callx4\t$s", []>, Requires<[HasWindowed]> {
+    let m = 0x3;
+    let n = 0x1;
+    let r = 0;
+  }
+
+  def CALLX8 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),
+                         "callx8\t$s", []>, Requires<[HasWindowed]> {
+    let m = 0x3;
+    let n = 0x2;
+    let r = 0;
+  }
+
+  def CALLX12 : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins AR:$s),
+                          "callx12\t$s", []>, Requires<[HasWindowed]> {
+    let m = 0x3;
+    let n = 0x3;
+    let r = 0;
+  }
+}
----------------
mshockwave wrote:

ditto factoring out the common parts.

https://github.com/llvm/llvm-project/pull/121118