[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -8147,7 +8147,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
 
     if (!TLI.shouldExpandPartialReductionIntrinsic(cast<IntrinsicInst>(&I))) {
       setValue(&I,
-               DAG.getNode(ISD::PARTIAL_REDUCE_UADD, dl, AccVT, Acc, Input));
+               DAG.getNode(ISD::PARTIAL_REDUCE_UMLA, dl, AccVT, Acc, Input));
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JamesChesterman wrote:

Done, made `MUL` instructions get generated all the time in the combine and expand functions. So if `Input2` is a splat vector of all 1s, the instruction is automatically removed. I have tested that this works by trying it with a splat vector of all 3s, and the `MUL` instructions are generated and remain in the output.

https://github.com/llvm/llvm-project/pull/117185