[llvm] [AArch64] Verify consecutive vector registers in tbl, tbx (PR #120262)

Oliver Stannard via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 19 01:11:09 PST 2024

Previous message: [llvm] [AArch64] Verify consecutive vector registers in tbl, tbx (PR #120262)
Next message: [llvm] [AArch64] Verify consecutive vector registers in tbl, tbx (PR #120262)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/ostannard approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/120262

Previous message: [llvm] [AArch64] Verify consecutive vector registers in tbl, tbx (PR #120262)
Next message: [llvm] [AArch64] Verify consecutive vector registers in tbl, tbx (PR #120262)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list