[llvm] [AArch64] Verify consecutive vector registers in tbl, tbx (PR #120262)

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git-clang-format --diff 57c161a6479fb70a31553e2f9bc1efa46262aa92 ea5fe7caf7be22bf27aff13eb3a4c8a25849a741 --extensions cpp -- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 5cda34dd4d..2fd0027251 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1865,10 +1865,12 @@ public:
     VecListIdx_PReg = 3,
   };
 
-  template <VecListIndexType RegTy, unsigned NumRegs, bool IsConsecutive = false>
+  template <VecListIndexType RegTy, unsigned NumRegs,
+            bool IsConsecutive = false>
   void addVectorListOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
-    assert((!IsConsecutive || (getVectorListStride() == 1)) && "Expected consecutive registers");
+    assert((!IsConsecutive || (getVectorListStride() == 1)) &&
+           "Expected consecutive registers");
     static const unsigned FirstRegs[][5] = {
       /* DReg */ { AArch64::Q0,
                    AArch64::D0,       AArch64::D0_D1,

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https://github.com/llvm/llvm-project/pull/120262