[llvm] [AArch64] Extend vecreduce to udot/sdot transformation to support usdot (PR #120094)

[David Green via llvm-commits]

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@@ -2866,6 +4497,362 @@ entry:
   %x = add i32 %r1, %r2
   ret i32 %x
 }
+
+define i32 @test_usdot_v33i8(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %sum) {
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davemgreen wrote:

There are quite a few of them! So long as there are tests for the usdot (including commuted patterns), then it should be OK. You can at least drop all the test that are not power-of-2 sizes - v5/v33/v24/v25.

https://github.com/llvm/llvm-project/pull/120094