[llvm] VT: teach implied-cond about samesign (PR #120120)

[Nikita Popov via llvm-commits]

https://github.com/nikic commented:

I was hoping for something between these two changes. This is now changing four different transforms at the same time. It should be possible to update these one by one, so it's clearer that each has adequate test coverage.

https://github.com/llvm/llvm-project/pull/120120