[llvm] [AArch64] Extend vecreduce to udot/sdot transformation to support usdot (PR #120094)

[Igor Kirillov via llvm-commits]

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@@ -1,22 +1,28 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple aarch64-linux-gnu -mattr=+dotprod    < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple aarch64-linux-gnu -mattr=+dotprod -global-isel -global-isel-abort=2 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple aarch64-linux-gnu -mattr=+dotprod,+i8mm    < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple aarch64-linux-gnu -mattr=+dotprod,+i8mm -global-isel -global-isel-abort=2 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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igogo-x86 wrote:

I am not sure it is a good place for the tests, but this file is responsible for testing the functionality of the `performVecReduceAddCombine` function and other tests with `+i8mm` have different purposes.

https://github.com/llvm/llvm-project/pull/120094