[llvm] 54dac27 - [GISel][RISCV] Use isSExtCheaperThanZExt when widening G_UMAX/G_UMIN. (#120041)
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Sun Dec 15 23:17:02 PST 2024
Author: Craig Topper
Date: 2024-12-15T23:16:58-08:00
New Revision: 54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71
URL: https://github.com/llvm/llvm-project/commit/54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71
DIFF: https://github.com/llvm/llvm-project/commit/54dac27c57d05d3f5c33bd4ec878bcb0a9c7cb71.diff
LOG: [GISel][RISCV] Use isSExtCheaperThanZExt when widening G_UMAX/G_UMIN. (#120041)
Similar to what we do for unsigned comparisons after #120032.
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 9edf8b0436a04d..e2247f76098e97 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2884,15 +2884,12 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
return Legalized;
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
- case TargetOpcode::G_UMIN:
- case TargetOpcode::G_UMAX:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
widenScalarDst(MI, WideTy);
Observer.changedInstr(MI);
return Legalized;
-
case TargetOpcode::G_UDIVREM:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
@@ -2901,6 +2898,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
widenScalarDst(MI, WideTy, 1);
Observer.changedInstr(MI);
return Legalized;
+ case TargetOpcode::G_UMIN:
+ case TargetOpcode::G_UMAX: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
+ auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
+ unsigned ExtOpc =
+ TLI.isSExtCheaperThanZExt(getApproximateEVTForLLT(Ty, Ctx),
+ getApproximateEVTForLLT(WideTy, Ctx))
+ ? TargetOpcode::G_SEXT
+ : TargetOpcode::G_ZEXT;
+
+ Observer.changingInstr(MI);
+ widenScalarSrc(MI, WideTy, 1, ExtOpc);
+ widenScalarSrc(MI, WideTy, 2, ExtOpc);
+ widenScalarDst(MI, WideTy);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
case TargetOpcode::G_SELECT:
Observer.changingInstr(MI);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
index 0a2331debd347d..afef788e79ef77 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
@@ -99,11 +99,12 @@ body: |
; RV64ZBB-LABEL: name: umax_i32
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]]
- ; RV64ZBB-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UMAX]], [[C]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
index 78673a1dcdda63..36a8ccb62cc3e8 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
@@ -99,11 +99,12 @@ body: |
; RV64ZBB-LABEL: name: umin_i32
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]]
- ; RV64ZBB-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UMIN]], [[C]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 7a0d5f3bf8cf74..0b876fed59c16f 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -987,12 +987,7 @@ define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBB-LABEL: minu_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: slli a0, a0, 32
-; RV64ZBB-NEXT: slli a1, a1, 32
-; RV64ZBB-NEXT: srli a0, a0, 32
-; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: minu a0, a0, a1
-; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%cmp = icmp ult i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
@@ -1031,12 +1026,7 @@ define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBB-LABEL: maxu_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: slli a0, a0, 32
-; RV64ZBB-NEXT: slli a1, a1, 32
-; RV64ZBB-NEXT: srli a0, a0, 32
-; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: maxu a0, a0, a1
-; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%cmp = icmp ugt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
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