[llvm] 6dc24f6 - [GISel] Improve MachineVerifier for G_SCMP/UCMP. (#120017)

[via llvm-commits]

Author: Craig Topper
Date: 2024-12-15T22:08:43-08:00
New Revision: 6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e

URL: https://github.com/llvm/llvm-project/commit/6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e
DIFF: https://github.com/llvm/llvm-project/commit/6dc24f6a2fcf0a199e007dc127ca5a4901a3a24e.diff

LOG: [GISel] Improve MachineVerifier for G_SCMP/UCMP. (#120017)

-Ensure destination type is at least 2 bits.
-Remove unnecessary check that both sources are the same type. The
verifier already handles this generically.

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineVerifier.cpp
    llvm/test/MachineVerifier/test_uscmp.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 7077580361d08a..bec36b728ae328 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1590,9 +1590,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
   case TargetOpcode::G_UCMP: {
     LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
-    LLT SrcTy2 = MRI->getType(MI->getOperand(2).getReg());
 
-    if (SrcTy.isPointerOrPointerVector() || SrcTy2.isPointerOrPointerVector()) {
+    if (SrcTy.isPointerOrPointerVector()) {
       report("Generic scmp/ucmp does not support pointers as operands", MI);
       break;
     }
@@ -1602,6 +1601,11 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
       break;
     }
 
+    if (DstTy.getScalarSizeInBits() < 2) {
+      report("Result type must be at least 2 bits wide", MI);
+      break;
+    }
+
     if ((DstTy.isVector() != SrcTy.isVector()) ||
         (DstTy.isVector() &&
          DstTy.getElementCount() != SrcTy.getElementCount())) {
@@ -1609,11 +1613,6 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
       break;
     }
 
-    if (SrcTy != SrcTy2) {
-      report("Generic scmp/ucmp must have same input types", MI);
-      break;
-    }
-
     break;
   }
   case TargetOpcode::G_EXTRACT: {

diff  --git a/llvm/test/MachineVerifier/test_uscmp.mir b/llvm/test/MachineVerifier/test_uscmp.mir
index aa686c4ec73e65..4e518749e7377e 100644
--- a/llvm/test/MachineVerifier/test_uscmp.mir
+++ b/llvm/test/MachineVerifier/test_uscmp.mir
@@ -19,13 +19,17 @@ body:             |
     %23:_(<2 x s32>) = G_IMPLICIT_DEF
     %24:_(<2 x s32>) = G_IMPLICIT_DEF
     ; CHECK: Generic vector scmp/ucmp must preserve number of lanes
-    %5:_(s1) = G_UCMP  %23, %24
+    %5:_(s2) = G_UCMP  %23, %24
 
     %15:_(s32) = G_CONSTANT i32 0
     %16:_(s64) = G_CONSTANT i64 2
-    ; CHECK: Generic scmp/ucmp must have same input types
-    %17:_(s1) = G_SCMP %15, %16
+    ; CHECK: Type mismatch in generic instruction
+    %17:_(s2) = G_SCMP %15, %16
 
+    %18:_(s32) = G_CONSTANT i32 0
+    %19:_(s32) = G_CONSTANT i32 2
+    ; CHECK: Result type must be at least 2 bits wide
+    %20:_(s1) = G_SCMP %18, %19
 
 
 ...