[llvm] [GISel][RISCV] Use isSExtCheaperThanZExt when widening G_UMAX/G_UMIN. (PR #120041)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 15 22:04:58 PST 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/120041
Similar to what we do for unsigned comparisons after #120032.
>From 6e37b5de5189e4a1123da81fda499deff296e331 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 15 Dec 2024 21:38:04 -0800
Subject: [PATCH] [GISel][RISCV] Use isSExtCheaperThanZExt when widening
G_UMAX/G_UMIN.
Similar to what we do for unsigned comparisons after #120032.
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 21 ++++++++++++++++---
.../legalizer/legalize-umax-rv64.mir | 9 ++++----
.../legalizer/legalize-umin-rv64.mir | 9 ++++----
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll | 10 ---------
4 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index c0f52e9b5cb16e..15b11177f2e83f 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2884,15 +2884,12 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
return Legalized;
case TargetOpcode::G_UDIV:
case TargetOpcode::G_UREM:
- case TargetOpcode::G_UMIN:
- case TargetOpcode::G_UMAX:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
widenScalarDst(MI, WideTy);
Observer.changedInstr(MI);
return Legalized;
-
case TargetOpcode::G_UDIVREM:
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
@@ -2901,6 +2898,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
widenScalarDst(MI, WideTy, 1);
Observer.changedInstr(MI);
return Legalized;
+ case TargetOpcode::G_UMIN:
+ case TargetOpcode::G_UMAX: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
+ auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
+ unsigned ExtOpc =
+ TLI.isSExtCheaperThanZExt(getApproximateEVTForLLT(Ty, Ctx),
+ getApproximateEVTForLLT(WideTy, Ctx))
+ ? TargetOpcode::G_SEXT
+ : TargetOpcode::G_ZEXT;
+
+ Observer.changingInstr(MI);
+ widenScalarSrc(MI, WideTy, 1, ExtOpc);
+ widenScalarSrc(MI, WideTy, 2, ExtOpc);
+ widenScalarDst(MI, WideTy);
+ Observer.changedInstr(MI);
+ return Legalized;
+ }
case TargetOpcode::G_SELECT:
Observer.changingInstr(MI);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
index 17f99ecc1e98a2..f6c69241d9d1f4 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umax-rv64.mir
@@ -100,11 +100,12 @@ body: |
; RV64ZBB-LABEL: name: umax_i32
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; RV64ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s64) = G_UMAX [[AND]], [[AND1]]
- ; RV64ZBB-NEXT: $x10 = COPY [[UMAX]](s64)
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UMAX]], [[C]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
index 33fac8ec13d64f..443b43c4634909 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-umin-rv64.mir
@@ -100,11 +100,12 @@ body: |
; RV64ZBB-LABEL: name: umin_i32
; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; RV64ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; RV64ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[SEXT_INREG]], [[SEXT_INREG1]]
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; RV64ZBB-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
- ; RV64ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s64) = G_UMIN [[AND]], [[AND1]]
- ; RV64ZBB-NEXT: $x10 = COPY [[UMIN]](s64)
+ ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UMIN]], [[C]]
+ ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64)
; RV64ZBB-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
index 4e12644a22b428..deede2d8515f68 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll
@@ -1006,12 +1006,7 @@ define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBB-LABEL: minu_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: slli a0, a0, 32
-; RV64ZBB-NEXT: slli a1, a1, 32
-; RV64ZBB-NEXT: srli a0, a0, 32
-; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: minu a0, a0, a1
-; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%cmp = icmp ult i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
@@ -1054,12 +1049,7 @@ define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind {
;
; RV64ZBB-LABEL: maxu_i32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: slli a0, a0, 32
-; RV64ZBB-NEXT: slli a1, a1, 32
-; RV64ZBB-NEXT: srli a0, a0, 32
-; RV64ZBB-NEXT: srli a1, a1, 32
; RV64ZBB-NEXT: maxu a0, a0, a1
-; RV64ZBB-NEXT: sext.w a0, a0
; RV64ZBB-NEXT: ret
%cmp = icmp ugt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
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