[llvm] e4fb302 - [LoongArch] Adds support for vectors in OptWInstrs (#118935)

[via llvm-commits]

Author: hev
Date: 2024-12-16T13:39:01+08:00
New Revision: e4fb30205f1df5156328b234ff2a2866b7035fef

URL: https://github.com/llvm/llvm-project/commit/e4fb30205f1df5156328b234ff2a2866b7035fef
DIFF: https://github.com/llvm/llvm-project/commit/e4fb30205f1df5156328b234ff2a2866b7035fef.diff

LOG: [LoongArch] Adds support for vectors in OptWInstrs (#118935)

Added: 
    

Modified: 
    llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
    llvm/test/CodeGen/LoongArch/sextw-removal.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
index 51e5e288a25124..322d3967563dbf 100644
--- a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
@@ -126,7 +126,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
 
       switch (UserMI->getOpcode()) {
       default:
-        // TODO: Add vector
         return false;
 
       case LoongArch::ADD_W:
@@ -162,6 +161,10 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
       case LoongArch::MOVGR2FCSR:
       case LoongArch::MOVGR2FRH_W:
       case LoongArch::MOVGR2FR_W_64:
+      case LoongArch::VINSGR2VR_W:
+      case LoongArch::XVINSGR2VR_W:
+      case LoongArch::VREPLGR2VR_W:
+      case LoongArch::XVREPLGR2VR_W:
         if (Bits >= 32)
           break;
         return false;
@@ -175,14 +178,37 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
           break;
         return false;
       case LoongArch::MOVGR2CF:
+      case LoongArch::VREPLVE_D:
+      case LoongArch::XVREPLVE_D:
         if (Bits >= 1)
           break;
         return false;
+      case LoongArch::VREPLVE_W:
+      case LoongArch::XVREPLVE_W:
+        if (Bits >= 2)
+          break;
+        return false;
+      case LoongArch::VREPLVE_H:
+      case LoongArch::XVREPLVE_H:
+        if (Bits >= 3)
+          break;
+        return false;
+      case LoongArch::VREPLVE_B:
+      case LoongArch::XVREPLVE_B:
+        if (Bits >= 4)
+          break;
+        return false;
       case LoongArch::EXT_W_B:
+      case LoongArch::VINSGR2VR_B:
+      case LoongArch::VREPLGR2VR_B:
+      case LoongArch::XVREPLGR2VR_B:
         if (Bits >= 8)
           break;
         return false;
       case LoongArch::EXT_W_H:
+      case LoongArch::VINSGR2VR_H:
+      case LoongArch::VREPLGR2VR_H:
+      case LoongArch::XVREPLGR2VR_H:
         if (Bits >= 16)
           break;
         return false;
@@ -435,7 +461,8 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
   case LoongArch::MOVCF2GR:
   case LoongArch::MOVFRH2GR_S:
   case LoongArch::MOVFR2GR_S_64:
-    // TODO: Add vector
+  case LoongArch::VPICKVE2GR_W:
+  case LoongArch::XVPICKVE2GR_W:
     return true;
   // Special cases that require checking operands.
   // shifting right sufficiently makes the value 32-bit sign-extended

diff  --git a/llvm/test/CodeGen/LoongArch/sextw-removal.ll b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
index 684ac1d3558683..fff749fb13e950 100644
--- a/llvm/test/CodeGen/LoongArch/sextw-removal.ll
+++ b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
@@ -1322,7 +1322,6 @@ define signext i32 @test20(<4 x i32> %v) {
 ; CHECK-LABEL: test20:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vpickve2gr.w $a0, $vr0, 3
-; CHECK-NEXT:    addi.w $a0, $a0, 0
 ; CHECK-NEXT:    ret
 ;
 ; NORMV-LABEL: test20:
@@ -1358,7 +1357,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
 ; CHECK-NEXT:    .cfi_offset 27, -56
 ; CHECK-NEXT:    .cfi_offset 28, -64
 ; CHECK-NEXT:    .cfi_offset 29, -72
-; CHECK-NEXT:    ld.d $s6, $sp, 80
+; CHECK-NEXT:    ld.w $s6, $sp, 80
 ; CHECK-NEXT:    move $s2, $a7
 ; CHECK-NEXT:    move $s4, $a5
 ; CHECK-NEXT:    move $s0, $a4
@@ -1379,8 +1378,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
 ; CHECK-NEXT:  .LBB24_3: # %for.cond32.preheader.preheader
 ; CHECK-NEXT:    ld.d $a0, $sp, 96
 ; CHECK-NEXT:    ld.d $a1, $sp, 88
-; CHECK-NEXT:    addi.w $a2, $s6, 0
-; CHECK-NEXT:    sltui $a2, $a2, 1
+; CHECK-NEXT:    sltui $a2, $s6, 1
 ; CHECK-NEXT:    masknez $a0, $a0, $a2
 ; CHECK-NEXT:    vreplgr2vr.w $vr0, $s6
 ; CHECK-NEXT:    andi $a1, $a1, 1
@@ -1452,7 +1450,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
 ; NORMV-NEXT:    beqz $s4, .LBB24_2
 ; NORMV-NEXT:  # %bb.1: # %if.then26
 ; NORMV-NEXT:    addi.d $a0, $s6, 1
-; NORMV-NEXT:    addi.w $s6, $a0, 0
+; NORMV-NEXT:    addi.d $s6, $a0, 0
 ; NORMV-NEXT:    beqz $s4, .LBB24_3
 ; NORMV-NEXT:    b .LBB24_6
 ; NORMV-NEXT:  .LBB24_2: