[llvm] 40a4cbb - [MIR, test] Change llc -march=x86-64 to -mtriple=x86_64
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 15 11:23:14 PST 2024
Author: Fangrui Song
Date: 2024-12-15T11:23:08-08:00
New Revision: 40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
URL: https://github.com/llvm/llvm-project/commit/40a4cbb0f200e5e0bafbd58d55c2da6daab9515d
DIFF: https://github.com/llvm/llvm-project/commit/40a4cbb0f200e5e0bafbd58d55c2da6daab9515d.diff
LOG: [MIR,test] Change llc -march=x86-64 to -mtriple=x86_64
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple (e.g. Windows, macOS).
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as these MIR tests do not
utilize object file format specific detail, but it's good to change
these tests to neighbor files that use -mtriple=x86_64
Added:
Modified:
llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
llvm/test/CodeGen/MIR/X86/block-address-operands.mir
llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
llvm/test/CodeGen/MIR/X86/cfi-offset.mir
llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
llvm/test/CodeGen/MIR/X86/constant-pool.mir
llvm/test/CodeGen/MIR/X86/constant-value-error.mir
llvm/test/CodeGen/MIR/X86/copyIRflags.mir
llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
llvm/test/CodeGen/MIR/X86/exception-function-state.mir
llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
llvm/test/CodeGen/MIR/X86/fastmath.mir
llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
llvm/test/CodeGen/MIR/X86/function-liveins.mir
llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
llvm/test/CodeGen/MIR/X86/global-value-operands.mir
llvm/test/CodeGen/MIR/X86/immediate-operands.mir
llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
llvm/test/CodeGen/MIR/X86/jump-table-info.mir
llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
llvm/test/CodeGen/MIR/X86/machine-instructions.mir
llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
llvm/test/CodeGen/MIR/X86/machine-verifier.mir
llvm/test/CodeGen/MIR/X86/memory-operands.mir
llvm/test/CodeGen/MIR/X86/metadata-operands.mir
llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
llvm/test/CodeGen/MIR/X86/missing-comma.mir
llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
llvm/test/CodeGen/MIR/X86/named-registers.mir
llvm/test/CodeGen/MIR/X86/newline-handling.mir
llvm/test/CodeGen/MIR/X86/null-register-operands.mir
llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
llvm/test/CodeGen/MIR/X86/register-operand-class.mir
llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
llvm/test/CodeGen/MIR/X86/stack-objects.mir
llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
llvm/test/CodeGen/MIR/X86/subregister-operands.mir
llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
llvm/test/CodeGen/MIR/X86/unknown-register.mir
llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
llvm/test/CodeGen/MIR/X86/virtual-registers.mir
llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
index 40bd1a86990be7..971e895322ad7f 100644
--- a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
+++ b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses basic block liveins correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir b/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
index 9358c7c19c4181..bfce653314977b 100644
--- a/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir
index 6108bef31a5a69..64d4d00fc0e989 100644
--- a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the block address operands
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
index 8337117e3718e4..f0a19d89577174 100644
--- a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
+++ b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses callee saved information in the
# stack objects correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
index 2ef5eb3ecc3712..527407f4c0150b 100644
--- a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
+++ b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the cfi offset operands
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
index 55b3fa474e2c68..ffdd45215e96dd 100644
--- a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the cfi def_cfa_register
# operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/cfi-offset.mir b/llvm/test/CodeGen/MIR/X86/cfi-offset.mir
index 1e1a8ad2011bdd..94a7c54641632a 100644
--- a/llvm/test/CodeGen/MIR/X86/cfi-offset.mir
+++ b/llvm/test/CodeGen/MIR/X86/cfi-offset.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the cfi offset operands
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
index acae12b07de314..8485924028228f 100644
--- a/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/constant-pool.mir b/llvm/test/CodeGen/MIR/X86/constant-pool.mir
index e367c2658cbaa5..6e78f44c9e7975 100644
--- a/llvm/test/CodeGen/MIR/X86/constant-pool.mir
+++ b/llvm/test/CodeGen/MIR/X86/constant-pool.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses constant pool constants and
# constant pool operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/constant-value-error.mir b/llvm/test/CodeGen/MIR/X86/constant-value-error.mir
index ca5b78984c81e2..15d71e345125b1 100644
--- a/llvm/test/CodeGen/MIR/X86/constant-value-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/constant-value-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when parsing an invalid
# constant value.
diff --git a/llvm/test/CodeGen/MIR/X86/copyIRflags.mir b/llvm/test/CodeGen/MIR/X86/copyIRflags.mir
index 27eb9feb92bae4..05f412919ed167 100644
--- a/llvm/test/CodeGen/MIR/X86/copyIRflags.mir
+++ b/llvm/test/CodeGen/MIR/X86/copyIRflags.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the fast math instruction flags.
...
diff --git a/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir b/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
index e01fd8d2b08244..3fd179caf28bf5 100644
--- a/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'dead' register flags
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
index 765d2e09ba8233..aea49eef1dda98 100644
--- a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @test(i64 %x) #0 {
entry:
diff --git a/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir b/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
index 6b6adf3d08dc16..08ae87084e108f 100644
--- a/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir b/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
index b7d7221fb790f6..9140971d2d9a03 100644
--- a/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
index aff96f49c9aa2f..5df0d65c6df17f 100644
--- a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'early-clobber' register
# flags correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/exception-function-state.mir b/llvm/test/CodeGen/MIR/X86/exception-function-state.mir
index f401da1dde1613..af974ad0e79e17 100644
--- a/llvm/test/CodeGen/MIR/X86/exception-function-state.mir
+++ b/llvm/test/CodeGen/MIR/X86/exception-function-state.mir
@@ -1,5 +1,5 @@
-# RUN: llc -simplify-mir=0 -march=x86-64 -run-pass=none -o - %s | FileCheck -check-prefixes=FULL,ALL %s
-# RUN: llc -simplify-mir=1 -march=x86-64 -run-pass=none -o - %s | FileCheck -check-prefixes=SIMPLE,ALL %s
+# RUN: llc -simplify-mir=0 -mtriple=x86_64 -run-pass=none -o - %s | FileCheck -check-prefixes=FULL,ALL %s
+# RUN: llc -simplify-mir=1 -mtriple=x86_64 -run-pass=none -o - %s | FileCheck -check-prefixes=SIMPLE,ALL %s
# This test ensures that the MIR parser parses callee saved information in the
# stack objects correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
index b1d3745015122c..397df6d7d2ab00 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
index 1b31b5ee441107..7b3145389d4f26 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir b/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
index a4e19a4ec96b6c..fec30ba3d231ff 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
index 2a47393f8d64f1..a8ab62904c2836 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
#
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
index a0d9dcd84ee5bd..164f1bf9a44a80 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
index a21ed0e6188c91..b9b520e86de08c 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-operand.mir
index 5e81481eda9a8c..577a7fa8411d5b 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-register-flag.mir
index ae36a3e54ae33b..57c5bc7e543691 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-
diff erent-implicit-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
index 27f44fdd3cda19..d91a92869763eb 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
index cb75cdd3cfbcd9..c4c4bcb150a67a 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
index 9f1a15b500b6b5..c5f3a7b86f4662 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
index f8b6baddd41d5e..7160a3e3c3d848 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @test(i64 %x) #0 {
entry:
diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
index 4a9c425fbfda02..aed994e8cb1b50 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
index cb7fb2586e41ab..0d1aac89a59c50 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
index db927be80bc02f..0ad92ad0f76a29 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
index f79b93c6777490..8cea9dde563adc 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
index 4befc53947601b..8350344e2700cc 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
index 4ef479d13b0abe..e50ced1132ce5b 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %x) {
entry:
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
index 03f2ec4d6cd3f7..45d4c3cd15ce54 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
index 30f80f9ed719f3..fc1915e473038a 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
index b0c5b979277e26..b49a5fd04a4f98 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
index 9257807d2879d6..b3b2e0dbb1875d 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir b/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
index dd0f4d39b09acf..e3b7b79ea6e366 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
index b0df32477833f7..39566aa1081d62 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
index 44ebcbc8a44616..06ac6d8d5cb9f0 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
index 21970038dd041b..9fd6a266ad6a35 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir b/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
index d2beda69696e4a..f79b84197019b4 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir b/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
index 1cf57719fa8767..d80dbee5af1c27 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
---
name: align_0
diff --git a/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
index 65f2c0b63879e7..426426a0423867 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir b/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
index d507de9531188e..6af814bbbe4501 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when a register operand doesn't
# follow register flags.
diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
index 98073d91843fd2..499fcd7115f25a 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
index 8b56239dc0fb92..fb931c8c5fc6f8 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir b/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
index 59d77b32f7fb7d..bc7667d9a9a950 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
---
name: test
diff --git a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
index e819e3fa772dca..c6adb28913c722 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
index 25a352a06d20d1..c81524e667c4d0 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir b/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
index 3f08e46f8971ba..164d3a034f3c1d 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
index f15db555f33f5d..a2c65dd3f0195a 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @test(i64 %x) #0 {
entry:
diff --git a/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
index 87995babe09c2f..601e1a3f077cd7 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
index 6b56f39c7e2d68..d03797c69a538c 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir b/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
index 785662e59a4999..2bbe1ebcde5705 100644
--- a/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the external symbol machine
# operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/fastmath.mir b/llvm/test/CodeGen/MIR/X86/fastmath.mir
index 5697d8bb259253..0e8d382b6a9a9f 100644
--- a/llvm/test/CodeGen/MIR/X86/fastmath.mir
+++ b/llvm/test/CodeGen/MIR/X86/fastmath.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the fast math instruction flags.
...
diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
index 0c68a3a3ed1a76..e26233f946606f 100644
--- a/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
+++ b/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the save and restore points in
# the machine frame info correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
index 2aa46928729155..7766c8e2e2ddc3 100644
--- a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
+++ b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the stack protector stack
# object reference in the machine frame info correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir b/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
index 01341b3a6da6cc..410d3e230c27c9 100644
--- a/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the frame setup instruction flag.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/function-liveins.mir b/llvm/test/CodeGen/MIR/X86/function-liveins.mir
index 7e71d2e05f1668..87df4352496950 100644
--- a/llvm/test/CodeGen/MIR/X86/function-liveins.mir
+++ b/llvm/test/CodeGen/MIR/X86/function-liveins.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses machine function's liveins
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
index 7514cdab0ab110..c2e508868da44c 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# Test that the MIR parser parses types on generic instructions correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir
index d981abf8ba5b9a..08e51870ba477b 100644
--- a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses global value operands correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/immediate-operands.mir b/llvm/test/CodeGen/MIR/X86/immediate-operands.mir
index 2fef51ca2305f5..043cf9bf47fbf0 100644
--- a/llvm/test/CodeGen/MIR/X86/immediate-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/immediate-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses immediate machine operands.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
index 61c4b6c98a73c5..8cece84518712a 100644
--- a/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'implicit' and 'implicit-def'
# register flags correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
index 2ac4d7cccac079..54145a4224895c 100644
--- a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
--- |
define i64 @test(i64 %x, i64 %y) #0 {
diff --git a/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir b/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
index 136e491a2e3b0e..30873a27790be8 100644
--- a/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses cfi-type correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir b/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
index e1edb19c9a74bf..f776e38b448bab 100644
--- a/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses heap alloc markers correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir b/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
index ad1b8efe7f86c7..947d93ef359372 100644
--- a/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
+++ b/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses pcsections metadata correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir b/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
index aade8327554495..761f4fe43bd9ac 100644
--- a/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses pre- and post-instruction symbols
# and MCSymbol operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
index 78403629c7b058..11fed8ae64fd0d 100644
--- a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
+++ b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the machine instruction's
# debug location metadata correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir b/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
index bcfdc6a316fa5a..e3009e3237a1fb 100644
--- a/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
+++ b/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when parsing an invalid
# constant pool item operand.
diff --git a/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir b/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
index 63f394356f2016..1a83f891d1fa46 100644
--- a/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
diff --git a/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir b/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
index c30d58a642c024..7f31318c813b13 100644
--- a/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
+++ b/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
index 65aab15442a564..091cbb0c40c950 100644
--- a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @test(i64 %x) #0 {
entry:
diff --git a/llvm/test/CodeGen/MIR/X86/jump-table-info.mir b/llvm/test/CodeGen/MIR/X86/jump-table-info.mir
index 8bbfb96a81906d..aad6caa477746d 100644
--- a/llvm/test/CodeGen/MIR/X86/jump-table-info.mir
+++ b/llvm/test/CodeGen/MIR/X86/jump-table-info.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the jump table info and jump
# table operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
index a965f9938b2c19..a1041f04fe527e 100644
--- a/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir b/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
index 6641848c75be6a..39e88fe3180d8e 100644
--- a/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'killed' register flags
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
index 1d53de61d4356a..c895d845708a54 100644
--- a/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir b/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
index 84e1c4fa8c12c4..ddbd876c97e1c6 100644
--- a/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
index 4fdb17f8a17196..785066111eccad 100644
--- a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
index a14cf33889808b..1b0ebbc1d19f14 100644
--- a/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir b/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
index 51438ac53f087f..9bcbd341b6a777 100644
--- a/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir b/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
index 69a5fd437085e9..6058912c61bed3 100644
--- a/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
+++ b/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the liveout register mask
# machine operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir b/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
index fc6a81fcef02dd..c6fe89d6235080 100644
--- a/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
+++ b/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass=none -o - %s | FileCheck %s
# CHECK: name: truly_aligned_load
# CHECK: MOV32rm {{.*}} :: (load (s32), align 4294967296)
diff --git a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
index 72e36f5e5716dc..5429d25a8e7d36 100644
--- a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses machine basic block operands.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir
index 38d80ebf304ab7..07aafd088f7ff1 100644
--- a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir
+++ b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses X86 machine instructions
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
index 64c07ae16f0378..6479bdd400a47a 100644
--- a/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
+++ b/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the address is checked in machine verifier.
---
diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir
index 6966b3e6778e25..329117464b10b8 100644
--- a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir
+++ b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the VerifyInstrumentation works for machine function.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/memory-operands.mir b/llvm/test/CodeGen/MIR/X86/memory-operands.mir
index 3beddf0245310c..70353cfb019795 100644
--- a/llvm/test/CodeGen/MIR/X86/memory-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/memory-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the machine memory operands
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir
index e6f8e05dcb1f71..c80af7dd6501cf 100644
--- a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the metadata machine operands
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir b/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
index 6b7b577f8ca549..44f8c3ca3dc981 100644
--- a/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
+++ b/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
@@ -1,5 +1,5 @@
-# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s
# The purpose of this test is to ensure that
diff ering flags do in-fact cause
# naming collisions with the new vreg renamers naming scheme.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir b/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
index dc4c3638f48bfe..51ef95877068c2 100644
--- a/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
+++ b/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/missing-comma.mir b/llvm/test/CodeGen/MIR/X86/missing-comma.mir
index 3500f05966fc5e..82ea21de39fe41 100644
--- a/llvm/test/CodeGen/MIR/X86/missing-comma.mir
+++ b/llvm/test/CodeGen/MIR/X86/missing-comma.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
index dcb39e86d680f0..8cd13895923b3b 100644
--- a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when an instruction
# is missing one of its implicit register operands.
diff --git a/llvm/test/CodeGen/MIR/X86/named-registers.mir b/llvm/test/CodeGen/MIR/X86/named-registers.mir
index 9d4dd8b8427a7d..23e1762f355893 100644
--- a/llvm/test/CodeGen/MIR/X86/named-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/named-registers.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses X86 registers correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/newline-handling.mir b/llvm/test/CodeGen/MIR/X86/newline-handling.mir
index 8b425a2f98ccec..6a248bb90fbec5 100644
--- a/llvm/test/CodeGen/MIR/X86/newline-handling.mir
+++ b/llvm/test/CodeGen/MIR/X86/newline-handling.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/null-register-operands.mir b/llvm/test/CodeGen/MIR/X86/null-register-operands.mir
index 5d22399cd72d09..7f99af02e7b0d8 100644
--- a/llvm/test/CodeGen/MIR/X86/null-register-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/null-register-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses null register operands correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
index 761d44d84ffb4c..c74e22586fa297 100644
--- a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses register mask operands correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
index c0eaddc6490970..35e3f4dd9a91c6 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s
+# RUN: not llc -o /dev/null %s -mtriple=x86_64 -run-pass none 2>&1 | FileCheck %s
# This test ensures that an error is reported for specifying the register class
# of a physical register.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
index 5d6777c63cc8cf..559fa31898801b 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s
+# RUN: not llc -o /dev/null %s -mtriple=x86_64 -run-pass none 2>&1 | FileCheck %s
# This test ensures that an error is reported for specifying the register class
# of a physical register.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
index 521722d9f24c54..a6bdde82ff0630 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
@@ -1,4 +1,4 @@
-# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s
+# RUN: llc -o - %s -mtriple=x86_64 -run-pass none | FileCheck %s
# Test various aspects of register class specification on machine operands.
--- |
define void @func() { ret void }
diff --git a/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir b/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
index dff926e1ebc009..e103385cddc01f 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir b/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
index 3a773b1320862f..06f7b22814f5f5 100644
--- a/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'renamable' register flags
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
index aacf66c98cf5d3..44b4c346cdd2f4 100644
--- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
+++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses simple register allocation hints
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
index f3a60a91f6d00f..5f440f6ea551a9 100644
--- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
+++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
index a705beaca1e8d6..f8f6edd5ca6f95 100644
--- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
+++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
index fd634b02c208ba..69c3deccd6758a 100644
--- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses fixed stack objects correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
index 9c5f549a9ea9d8..9cc25d8882bf87 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the stack object's debug info
# correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir b/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
index 78281839866a25..4721a02eef276e 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when it encounters a
# stack object with a name that can't be associated with an alloca instruction.
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
index 15b33e1818382c..2ff08e739bf96d 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an stack object reference
# uses a
diff erent name then the stack object definition.
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
index 20b93077609ce5..6217ad35c13bb6 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/stack-objects.mir b/llvm/test/CodeGen/MIR/X86/stack-objects.mir
index 4a97455e20387a..0eaf6b9fb597e9 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-objects.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses stack objects correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
index 30df44da56c65f..2afdda47c85278 100644
--- a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %a) {
body:
diff --git a/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir b/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
index 832576fbb68896..4adae94978b1e1 100644
--- a/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
+++ b/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported for subreg index on a physreg.
--- |
define void @t() { ret void }
diff --git a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
index f34816bf9a1b8a..db53873faffcf9 100644
--- a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses and prints subregisters index
# operands correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir
index a7d854fde1ed50..039122a030edc9 100644
--- a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses subregisters in register operands
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
index 54fbd01eae7a59..6770f03e250454 100644
--- a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
+++ b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses basic block successors and
# probabilities correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
index d08919692a49d9..2c01ab187df6c1 100644
--- a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
+++ b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses basic block successors correctly.
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
index 7509b31964e5aa..3ad5d2e8c935cf 100644
--- a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
+++ b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @test(i64 %x) #0 {
entry:
diff --git a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
index 1e4104e8ebda03..ff67990b22d415 100644
--- a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
+++ b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not --crash llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the Machine Verifier detects tied physical registers
# that doesn't match.
diff --git a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
index e0220cfdb706e5..7e84591d92b559 100644
--- a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the 'undef' register flags
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
index f319108e5628e1..5434ea0b0153c9 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %a) {
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir b/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
index 650695c0a9cbf6..1f568eb810550a 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an invalid global value index
# is used.
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
index 18589798704640..a88a9308d0d58b 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
index 309da51ca830fb..ed860d23ede564 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir b/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
index 246b0c99646142..46bfaa301aab8b 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
index 48f17ef3b006ec..57bcf958569454 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an undefined global value is
# used.
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir b/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
index 8fb9dbc2c56803..a677bbf68441aa 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when it encounters an
# unknown register class.
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
index ea77d137eb820b..03585f8704b436 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %a) {
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
index 7bfb6ad197d9ea..6954ffbf9abcca 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
index c31735a52eb68c..820291c26989b1 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that the MIR parser reports an error when parsing a
# reference to an undefined virtual register.
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir b/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
index 953b9f666bfec8..4c12c768a3f3a1 100644
--- a/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when a register operand is sized
# but isn't generic, like a physical register.
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir b/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
index 4377347f0a9f0a..143e542fa6f502 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an unknown instruction is
# encountered.
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
index 6e6796c06464d9..bc11ee3e6ea7cd 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an invalid machine basic
# block index is used.
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
index e08ad4c93b01c8..022ea039044509 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @inc(ptr %x) {
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
index 95fc53b441fb93..295e356c2be3e3 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
index 10819bfafd9ae2..fc5deb4d6dd52f 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an unknown named machine
# basic block is encountered.
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-register.mir b/llvm/test/CodeGen/MIR/X86/unknown-register.mir
index cdd85f0b1b369c..c8f007874c35da 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-register.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an unknown register is
# encountered.
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
index 30ec530fad3db7..bc95dd3a295f27 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an unknown subregister index
# is encountered.
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
index 6db338dc9fcaeb..69ff69623c3135 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# This test ensures that an error is reported when an unknown subregister index
# is encountered.
diff --git a/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir b/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
index 15817d06a28a9f..0849b7155249a7 100644
--- a/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
+++ b/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
index ebf0b41c09e4d5..3c8594abd97af6 100644
--- a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %a) {
diff --git a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
index a34754c8ed483e..6e27bc064234ef 100644
--- a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
+++ b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses variable sized stack objects
# correctly.
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
index 423e892da4a496..03e0653b1d6eae 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
index 819f65638b67de..f85dd15f330248 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses virtual register definitions and
# references correctly.
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
index 53312f93772a2b..6a236a09646a12 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/instr-ref-roundtrip.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=machineverifier -o - -experimental-debug-variable-locations | FileCheck %s
+# RUN: llc %s -mtriple=x86_64 -run-pass=machineverifier -o - -experimental-debug-variable-locations | FileCheck %s
#
# REQUIRES: x86-registered-target
#
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
index d4ed0fba2d7cdc..10f12458a9963c 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations | FileCheck %s -implicit-check-not=DBG_VALUE
;
; Test that InstrRefBasedLDV / livedebugvalues doesn't crash when it sees
; illegal instruction referencing debug-info. This can be caused by
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
index e8391538d3fe76..d8d13676ebde87 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations | FileCheck %s -implicit-check-not=DBG_VALUE
define i32 @_Z8bb_to_bb() local_unnamed_addr !dbg !12 {
entry:
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
index 33e3be7634c58f..c4856a24990a55 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_recover_clobbers.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - -force-instr-ref-livedebugvalues=1 -emulate-old-livedebugvalues=0 | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - -force-instr-ref-livedebugvalues=1 -emulate-old-livedebugvalues=0 | FileCheck %s -implicit-check-not=DBG_VALUE
;; When using instruction referencing LiveDebugValues, when a register gets
;; clobbered, we should transfer variable locations to backup locations, if
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
index ff5d3c5e1cbaee..fdfb11410a8cbb 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
+# RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
#
# Test that we can spill and restore through subregisters too. In this test,
# eax is def'd and then spilt, but as part of a larger register.
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
index 779c06fe378d84..3bc9689425c882 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
+# RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
#
# Test that when we have a subregister qualifiers in substitutions, that
# InstrRefBasedLDV correctly applies them to the variable location. Below, a
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
index 7d83ccb52cec34..b478ceeaa7f4e2 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues \
+# RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues \
# RUN: -mtriple x86_64-unknown-unknown \
# RUN: -experimental-debug-variable-locations -o - 2>&1 \
# RUN: | FileCheck %s
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir b/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
index 782ddf895a8c63..fcdfb8a138716f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/no-duplicates.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc %s -march=x86-64 -run-pass=machineverifier -o - 2>&1 | FileCheck %s
+# RUN: not --crash llc %s -mtriple=x86_64 -run-pass=machineverifier -o - 2>&1 | FileCheck %s
#
# REQUIRES: x86-registered-target
#
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir b/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
index 917d921a506063..f2a5b9b3d6ff1f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/no-metainstrs.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc %s -march=x86-64 -run-pass=machineverifier -o - 2>&1 | FileCheck %s
+# RUN: not --crash llc %s -mtriple=x86_64 -run-pass=machineverifier -o - 2>&1 | FileCheck %s
#
# REQUIRES: x86-registered-target
#
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
index 5c4f9b0d0e478e..5409b79ec9c604 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -o - -run-pass=livedebugvalues -march=x86-64 \
+# RUN: llc %s -o - -run-pass=livedebugvalues -mtriple=x86_64 \
# RUN: -experimental-debug-variable-locations=true \
# RUN: | FileCheck %s
#
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir b/llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
index 0d46b8ce1d0823..6b6c2931d7ca48 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/pretty-print.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=machineverifier -print-after-all -o /dev/null -experimental-debug-variable-locations 2>&1 | FileCheck %s
+# RUN: llc %s -mtriple=x86_64 -run-pass=machineverifier -print-after-all -o /dev/null -experimental-debug-variable-locations 2>&1 | FileCheck %s
# REQUIRES: x86-registered-target
--- |
define void @pretty_print_test() {
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
index 8f43a55b34001f..c1ae0ab9c95a92 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - \
+# RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - \
# RUN: -experimental-debug-variable-locations=true \
# RUN: | FileCheck %s -implicit-check-not=DBG_VALUE \
# RUN: --check-prefixes=CHECK,COMMON
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
index 515180388652c5..64212b21bbbaf8 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -march=x86-64 -run-pass=machineverifier \
+# RUN: llc %s -mtriple=x86_64 -run-pass=machineverifier \
# RUN: -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
#
# REQUIRES: x86-registered-target
diff --git a/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir b/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
index 57cb19734e5ef7..2e858d4d87456c 100644
--- a/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
+++ b/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
@@ -1,5 +1,5 @@
-# RUN: llc -run-pass=livedebugvalues -verify-machineinstrs -march=x86-64 -o - %s | FileCheck %s
-# RUN: llc -force-instr-ref-livedebugvalues=1 -run-pass=livedebugvalues -verify-machineinstrs -march=x86-64 -o - %s | FileCheck %s
+# RUN: llc -run-pass=livedebugvalues -verify-machineinstrs -mtriple=x86_64 -o - %s | FileCheck %s
+# RUN: llc -force-instr-ref-livedebugvalues=1 -run-pass=livedebugvalues -verify-machineinstrs -mtriple=x86_64 -o - %s | FileCheck %s
#
#extern void fn2(int);
#
diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
index 3b5bf5d38075c9..73c723b1446de4 100644
--- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
+++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass livedebugvalues -march=x86-64 -o - %s \
+# RUN: llc -run-pass livedebugvalues -mtriple=x86_64 -o - %s \
# RUN: -experimental-debug-variable-locations=true | FileCheck %s
# Generated from the following source with:
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
index b887f9b44fd77e..2d3ae1517b7737 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues-ignores-metaInstructions.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that live-debug-values ignores meta instructions.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
index ace5cbf407702f..e11eb159103173 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated through a CFG containing
; a diamond that doesn't move or clobber their locations.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
index 21c2875f32cdff..0a557d89b1fdc7 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_clobber.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are only propagated into the top blocks of
; a diamond when the location is clobbered and not into the successor block.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
index a8c0fab3374c44..8e7f802b0fc515 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_match_move.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated correctly through a
; diamond CFG when the location is moved by another instruction.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
index 8f37c88fe98505..dfbbd5f79585f5 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_clobber.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into a successor block
; of a diamond CFG that clobbers its location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
index 33b918c2eaa7d6..ad0747f359b915 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_diamond_one_move.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into a successor block
; of a diamond CFG that moves its location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
index 7f85b98c201341..81c7b9a9cbae90 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_basic_loop.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated throughout a CFG with a
; loop that doesn't move or clobber its location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
index 808d3a41a05a2d..5647e331f8b1e4 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated throughout a basic
; sequential CFG.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
index 935dcc494fd867..7a37021d920163 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_clobbered.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated into basic blocks with no
; control flow when it's location is clobbered.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
index 33246054dca82f..2f534aa776c41c 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_bb_to_bb_move_to_clobber.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are correctly propagated into blocks with
; no control flow when a location is moved and then clobbered.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
index aca28e2bceb18c..19a131b6dcfd77 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_load_in_loop.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations -emulate-old-livedebugvalues=0 | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations -emulate-old-livedebugvalues=0 | FileCheck %s -implicit-check-not=DBG_VALUE
; Sometimes, variables can have multiple locations, and when control flow
; merges LiveDebugValues has a hard time picking which one the variable lives
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
index c9f972646f9ba3..9941ba9fe6face 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are correctly propagated into a loop with
; break.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
index 92fe5a041eb47b..bf81ad4bd04ef5 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_break_clobbered.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are correctly propagated when dealing
; with a loop that clobbers its location and has two exit points (a break).
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
index 14d9196ee13a05..9ec07a37c77e1f 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_clobbered.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into a loop that
; clobbers it's location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
index a0b1075ae30a47..0dbdcaca0f5726 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated into a loop with
; diamond pattern and beyond.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
index 2e1f4292042d62..f88c99e1b635d4 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_clobber.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into a loop with
; diamond pattern that clobbers it's location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
index 70a7b379e19b07..1a760bc46cdc52 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_diamond_move.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated into a loop with
; diamond pattern but not beyond.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
index 01d2735d4d9263..600c28cc25afbb 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_early_clobber.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into a loop that
; clobbers it's location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
index 0011593d4f5043..bd4adb64e8e3a4 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_terminated.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into a loop that
; explicitly terminates its location.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
index a018c66160f1f3..e58d666dfcdd6b 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are prapogated into a loop that has two
; backedges and beyond.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
index d40553322e5dc4..50cda6cf25c882 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_two_backedge_clobbered.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into loops that clobber
; their locations and have two backedges.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
index 32d85e882dbfb7..43b01b3bf27076 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are propagated into loops within loops.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
index 4b143414a41c0f..aaa007938e0128 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_clobbered.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into loops with inner
; loops that clobber their locations.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
index 3b25b8313e40a4..a3b8da29d29c75 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_moved.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into loops with inner
; loops that move their locations.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
index 44a1daf45deaba..f123b3f47bb385 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_loop_within_loop_outer_moved.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - | FileCheck %s -implicit-check-not=DBG_VALUE
; Check that DBG_VALUE instructions are not propagated into loops with inner
; loops that move their locations.
diff --git a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
index c204b5dcf82c4c..00304eb3e8e325 100644
--- a/llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
+++ b/llvm/test/DebugInfo/MIR/X86/livedebugvalues_many_loop_heads.mir
@@ -1,5 +1,5 @@
--- |
- ; RUN: llc %s -march=x86-64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations | FileCheck %s -implicit-check-not=DBG_VALUE
+ ; RUN: llc %s -mtriple=x86_64 -run-pass=livedebugvalues -o - -experimental-debug-variable-locations | FileCheck %s -implicit-check-not=DBG_VALUE
; The MIR below represents a pathalogical case for value-tracking
; LiveDebugValues. The code structure is eight nested loops, with loop heads
diff --git a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
index 776335e5ddfd4c..5548f622d7f9b7 100644
--- a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
+++ b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
@@ -1,5 +1,5 @@
-# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s| FileCheck %s
-# RUN: llc -force-instr-ref-livedebugvalues=1 -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s| FileCheck %s
+# RUN: llc -debug-entry-values -run-pass=livedebugvalues -mtriple=x86_64 -o - %s| FileCheck %s
+# RUN: llc -force-instr-ref-livedebugvalues=1 -debug-entry-values -run-pass=livedebugvalues -mtriple=x86_64 -o - %s| FileCheck %s
## Test case:
## int global;
## int foo(int p, int q, int r) {
diff --git a/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir b/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
index 9585f4bb131794..2bafcc2944bbe7 100644
--- a/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
+++ b/llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
@@ -1,6 +1,6 @@
# Verify that a CFI instruction with no debug location
# does not result in a line-0 location in the assembler.
-# RUN: %llc_dwarf -start-after=prologepilog -march=x86-64 -use-unknown-locations=Enable %s -o - | FileCheck %s
+# RUN: %llc_dwarf -start-after=prologepilog -mtriple=x86_64 -use-unknown-locations=Enable %s -o - | FileCheck %s
#
# CHECK-NOT: .loc 1 0
# CHECK: .cfi_def_cfa_offset
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