[llvm] Add SD matchers and unit test coverage for ISD::VECTOR_SHUFFLE (PR #119592)

[Aidan Goldfarb via llvm-commits]

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@@ -119,6 +119,27 @@ TEST_F(SelectionDAGPatternMatchTest, matchValueType) {
   EXPECT_FALSE(sd_match(Op2, m_ScalableVectorVT()));
 }
 
+TEST_F(SelectionDAGPatternMatchTest, matchVecShuffle) {
+  SDLoc DL;
+  auto Int32VT = EVT::getIntegerVT(Context, 32);
+  auto VInt32VT = EVT::getVectorVT(Context, Int32VT, 4);
+  SmallVector<int, 4> MaskData = {2, 0, 3, 1};
+  ArrayRef<int> CapturedMask;
+
+  SDValue V0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, VInt32VT);
+  SDValue V1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, VInt32VT);
+  SDValue VecShuffleWithMask =
+      DAG->getVectorShuffle(VInt32VT, DL, V0, V1, MaskData);
+
+  using namespace SDPatternMatch;
+  EXPECT_TRUE(sd_match(VecShuffleWithMask,
+                       m_Shuffle(m_Value(), m_Value(), CapturedMask)));
+  EXPECT_TRUE(sd_match(VecShuffleWithMask,
+                       m_ShuffleSpecificMask(m_Value(), m_Value(), MaskData)));
+  EXPECT_TRUE(std::equal(MaskData.begin(), MaskData.end(), CapturedMask.begin(),
+                         CapturedMask.end()));
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AidanGoldfarb wrote:

Will add. I was wondering before about false cases, such as used in other tests. For example `VSelect` is asserted to not match `Select`. Is it worth implementing some EXPECT_FALSE for the instruction (as opposed to the mask) part of the match? 

https://github.com/llvm/llvm-project/pull/119592