[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -81,12 +75,10 @@ static ExecutionMode getExecutionModes(const Instruction &Instr,
     EM |= ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS;
   if (Instr.hasMemoryOperands())
     EM |= ExecutionMode::SERIAL_VIA_MEMORY_INSTR;
-  else {
-    if (Instr.hasAliasingRegisters(ForbiddenRegisters))
-      EM |= ExecutionMode::SERIAL_VIA_EXPLICIT_REGS;
-    if (Instr.hasOneUseOrOneDef())
-      EM |= ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR;
-  }
+  if (Instr.hasAliasingNotMemoryRegisters(ForbiddenRegisters))
+    EM |= ExecutionMode::SERIAL_VIA_EXPLICIT_REGS;
+  if (Instr.hasOneUseOrOneDef())
+    EM |= ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR;
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AnastasiyaChernikova wrote:

Yes, as example this allows to chain instructions via rd and rs2:
amo* rd, rs2, (rs1)
amo* rd, rs2, (rs1)

https://github.com/llvm/llvm-project/pull/89047