[llvm] [NVPTX] Pattern match texture/surface intrinsics (NFCI) (PR #119982)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 15 05:10:34 PST 2024
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/119982
>From 0730b73f3b3f6f17d1982edb51a4e1a7d024ec7e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sat, 14 Dec 2024 20:37:48 +0300
Subject: [PATCH 1/4] [NVPTX] Let SelectionDAG match intrinsics (NFCI)
---
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 1392 -------------------
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 -
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 1076 +-------------
llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 357 -----
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 735 ++++++++++
5 files changed, 741 insertions(+), 2821 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index e1fb2d7fcee030..989ec8d02d2f1a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -166,351 +166,6 @@ void NVPTXDAGToDAGISel::Select(SDNode *N) {
if (tryIntrinsicVoid(N))
return;
break;
- case NVPTXISD::Tex1DFloatS32:
- case NVPTXISD::Tex1DFloatFloat:
- case NVPTXISD::Tex1DFloatFloatLevel:
- case NVPTXISD::Tex1DFloatFloatGrad:
- case NVPTXISD::Tex1DS32S32:
- case NVPTXISD::Tex1DS32Float:
- case NVPTXISD::Tex1DS32FloatLevel:
- case NVPTXISD::Tex1DS32FloatGrad:
- case NVPTXISD::Tex1DU32S32:
- case NVPTXISD::Tex1DU32Float:
- case NVPTXISD::Tex1DU32FloatLevel:
- case NVPTXISD::Tex1DU32FloatGrad:
- case NVPTXISD::Tex1DArrayFloatS32:
- case NVPTXISD::Tex1DArrayFloatFloat:
- case NVPTXISD::Tex1DArrayFloatFloatLevel:
- case NVPTXISD::Tex1DArrayFloatFloatGrad:
- case NVPTXISD::Tex1DArrayS32S32:
- case NVPTXISD::Tex1DArrayS32Float:
- case NVPTXISD::Tex1DArrayS32FloatLevel:
- case NVPTXISD::Tex1DArrayS32FloatGrad:
- case NVPTXISD::Tex1DArrayU32S32:
- case NVPTXISD::Tex1DArrayU32Float:
- case NVPTXISD::Tex1DArrayU32FloatLevel:
- case NVPTXISD::Tex1DArrayU32FloatGrad:
- case NVPTXISD::Tex2DFloatS32:
- case NVPTXISD::Tex2DFloatFloat:
- case NVPTXISD::Tex2DFloatFloatLevel:
- case NVPTXISD::Tex2DFloatFloatGrad:
- case NVPTXISD::Tex2DS32S32:
- case NVPTXISD::Tex2DS32Float:
- case NVPTXISD::Tex2DS32FloatLevel:
- case NVPTXISD::Tex2DS32FloatGrad:
- case NVPTXISD::Tex2DU32S32:
- case NVPTXISD::Tex2DU32Float:
- case NVPTXISD::Tex2DU32FloatLevel:
- case NVPTXISD::Tex2DU32FloatGrad:
- case NVPTXISD::Tex2DArrayFloatS32:
- case NVPTXISD::Tex2DArrayFloatFloat:
- case NVPTXISD::Tex2DArrayFloatFloatLevel:
- case NVPTXISD::Tex2DArrayFloatFloatGrad:
- case NVPTXISD::Tex2DArrayS32S32:
- case NVPTXISD::Tex2DArrayS32Float:
- case NVPTXISD::Tex2DArrayS32FloatLevel:
- case NVPTXISD::Tex2DArrayS32FloatGrad:
- case NVPTXISD::Tex2DArrayU32S32:
- case NVPTXISD::Tex2DArrayU32Float:
- case NVPTXISD::Tex2DArrayU32FloatLevel:
- case NVPTXISD::Tex2DArrayU32FloatGrad:
- case NVPTXISD::Tex3DFloatS32:
- case NVPTXISD::Tex3DFloatFloat:
- case NVPTXISD::Tex3DFloatFloatLevel:
- case NVPTXISD::Tex3DFloatFloatGrad:
- case NVPTXISD::Tex3DS32S32:
- case NVPTXISD::Tex3DS32Float:
- case NVPTXISD::Tex3DS32FloatLevel:
- case NVPTXISD::Tex3DS32FloatGrad:
- case NVPTXISD::Tex3DU32S32:
- case NVPTXISD::Tex3DU32Float:
- case NVPTXISD::Tex3DU32FloatLevel:
- case NVPTXISD::Tex3DU32FloatGrad:
- case NVPTXISD::TexCubeFloatFloat:
- case NVPTXISD::TexCubeFloatFloatLevel:
- case NVPTXISD::TexCubeS32Float:
- case NVPTXISD::TexCubeS32FloatLevel:
- case NVPTXISD::TexCubeU32Float:
- case NVPTXISD::TexCubeU32FloatLevel:
- case NVPTXISD::TexCubeArrayFloatFloat:
- case NVPTXISD::TexCubeArrayFloatFloatLevel:
- case NVPTXISD::TexCubeArrayS32Float:
- case NVPTXISD::TexCubeArrayS32FloatLevel:
- case NVPTXISD::TexCubeArrayU32Float:
- case NVPTXISD::TexCubeArrayU32FloatLevel:
- case NVPTXISD::Tld4R2DFloatFloat:
- case NVPTXISD::Tld4G2DFloatFloat:
- case NVPTXISD::Tld4B2DFloatFloat:
- case NVPTXISD::Tld4A2DFloatFloat:
- case NVPTXISD::Tld4R2DS64Float:
- case NVPTXISD::Tld4G2DS64Float:
- case NVPTXISD::Tld4B2DS64Float:
- case NVPTXISD::Tld4A2DS64Float:
- case NVPTXISD::Tld4R2DU64Float:
- case NVPTXISD::Tld4G2DU64Float:
- case NVPTXISD::Tld4B2DU64Float:
- case NVPTXISD::Tld4A2DU64Float:
- case NVPTXISD::TexUnified1DFloatS32:
- case NVPTXISD::TexUnified1DFloatFloat:
- case NVPTXISD::TexUnified1DFloatFloatLevel:
- case NVPTXISD::TexUnified1DFloatFloatGrad:
- case NVPTXISD::TexUnified1DS32S32:
- case NVPTXISD::TexUnified1DS32Float:
- case NVPTXISD::TexUnified1DS32FloatLevel:
- case NVPTXISD::TexUnified1DS32FloatGrad:
- case NVPTXISD::TexUnified1DU32S32:
- case NVPTXISD::TexUnified1DU32Float:
- case NVPTXISD::TexUnified1DU32FloatLevel:
- case NVPTXISD::TexUnified1DU32FloatGrad:
- case NVPTXISD::TexUnified1DArrayFloatS32:
- case NVPTXISD::TexUnified1DArrayFloatFloat:
- case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
- case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
- case NVPTXISD::TexUnified1DArrayS32S32:
- case NVPTXISD::TexUnified1DArrayS32Float:
- case NVPTXISD::TexUnified1DArrayS32FloatLevel:
- case NVPTXISD::TexUnified1DArrayS32FloatGrad:
- case NVPTXISD::TexUnified1DArrayU32S32:
- case NVPTXISD::TexUnified1DArrayU32Float:
- case NVPTXISD::TexUnified1DArrayU32FloatLevel:
- case NVPTXISD::TexUnified1DArrayU32FloatGrad:
- case NVPTXISD::TexUnified2DFloatS32:
- case NVPTXISD::TexUnified2DFloatFloat:
- case NVPTXISD::TexUnified2DFloatFloatLevel:
- case NVPTXISD::TexUnified2DFloatFloatGrad:
- case NVPTXISD::TexUnified2DS32S32:
- case NVPTXISD::TexUnified2DS32Float:
- case NVPTXISD::TexUnified2DS32FloatLevel:
- case NVPTXISD::TexUnified2DS32FloatGrad:
- case NVPTXISD::TexUnified2DU32S32:
- case NVPTXISD::TexUnified2DU32Float:
- case NVPTXISD::TexUnified2DU32FloatLevel:
- case NVPTXISD::TexUnified2DU32FloatGrad:
- case NVPTXISD::TexUnified2DArrayFloatS32:
- case NVPTXISD::TexUnified2DArrayFloatFloat:
- case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
- case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
- case NVPTXISD::TexUnified2DArrayS32S32:
- case NVPTXISD::TexUnified2DArrayS32Float:
- case NVPTXISD::TexUnified2DArrayS32FloatLevel:
- case NVPTXISD::TexUnified2DArrayS32FloatGrad:
- case NVPTXISD::TexUnified2DArrayU32S32:
- case NVPTXISD::TexUnified2DArrayU32Float:
- case NVPTXISD::TexUnified2DArrayU32FloatLevel:
- case NVPTXISD::TexUnified2DArrayU32FloatGrad:
- case NVPTXISD::TexUnified3DFloatS32:
- case NVPTXISD::TexUnified3DFloatFloat:
- case NVPTXISD::TexUnified3DFloatFloatLevel:
- case NVPTXISD::TexUnified3DFloatFloatGrad:
- case NVPTXISD::TexUnified3DS32S32:
- case NVPTXISD::TexUnified3DS32Float:
- case NVPTXISD::TexUnified3DS32FloatLevel:
- case NVPTXISD::TexUnified3DS32FloatGrad:
- case NVPTXISD::TexUnified3DU32S32:
- case NVPTXISD::TexUnified3DU32Float:
- case NVPTXISD::TexUnified3DU32FloatLevel:
- case NVPTXISD::TexUnified3DU32FloatGrad:
- case NVPTXISD::TexUnifiedCubeFloatFloat:
- case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
- case NVPTXISD::TexUnifiedCubeS32Float:
- case NVPTXISD::TexUnifiedCubeS32FloatLevel:
- case NVPTXISD::TexUnifiedCubeU32Float:
- case NVPTXISD::TexUnifiedCubeU32FloatLevel:
- case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
- case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
- case NVPTXISD::TexUnifiedCubeArrayS32Float:
- case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
- case NVPTXISD::TexUnifiedCubeArrayU32Float:
- case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
- case NVPTXISD::TexUnifiedCubeFloatFloatGrad:
- case NVPTXISD::TexUnifiedCubeS32FloatGrad:
- case NVPTXISD::TexUnifiedCubeU32FloatGrad:
- case NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad:
- case NVPTXISD::TexUnifiedCubeArrayS32FloatGrad:
- case NVPTXISD::TexUnifiedCubeArrayU32FloatGrad:
- case NVPTXISD::Tld4UnifiedR2DFloatFloat:
- case NVPTXISD::Tld4UnifiedG2DFloatFloat:
- case NVPTXISD::Tld4UnifiedB2DFloatFloat:
- case NVPTXISD::Tld4UnifiedA2DFloatFloat:
- case NVPTXISD::Tld4UnifiedR2DS64Float:
- case NVPTXISD::Tld4UnifiedG2DS64Float:
- case NVPTXISD::Tld4UnifiedB2DS64Float:
- case NVPTXISD::Tld4UnifiedA2DS64Float:
- case NVPTXISD::Tld4UnifiedR2DU64Float:
- case NVPTXISD::Tld4UnifiedG2DU64Float:
- case NVPTXISD::Tld4UnifiedB2DU64Float:
- case NVPTXISD::Tld4UnifiedA2DU64Float:
- if (tryTextureIntrinsic(N))
- return;
- break;
- case NVPTXISD::Suld1DI8Clamp:
- case NVPTXISD::Suld1DI16Clamp:
- case NVPTXISD::Suld1DI32Clamp:
- case NVPTXISD::Suld1DI64Clamp:
- case NVPTXISD::Suld1DV2I8Clamp:
- case NVPTXISD::Suld1DV2I16Clamp:
- case NVPTXISD::Suld1DV2I32Clamp:
- case NVPTXISD::Suld1DV2I64Clamp:
- case NVPTXISD::Suld1DV4I8Clamp:
- case NVPTXISD::Suld1DV4I16Clamp:
- case NVPTXISD::Suld1DV4I32Clamp:
- case NVPTXISD::Suld1DArrayI8Clamp:
- case NVPTXISD::Suld1DArrayI16Clamp:
- case NVPTXISD::Suld1DArrayI32Clamp:
- case NVPTXISD::Suld1DArrayI64Clamp:
- case NVPTXISD::Suld1DArrayV2I8Clamp:
- case NVPTXISD::Suld1DArrayV2I16Clamp:
- case NVPTXISD::Suld1DArrayV2I32Clamp:
- case NVPTXISD::Suld1DArrayV2I64Clamp:
- case NVPTXISD::Suld1DArrayV4I8Clamp:
- case NVPTXISD::Suld1DArrayV4I16Clamp:
- case NVPTXISD::Suld1DArrayV4I32Clamp:
- case NVPTXISD::Suld2DI8Clamp:
- case NVPTXISD::Suld2DI16Clamp:
- case NVPTXISD::Suld2DI32Clamp:
- case NVPTXISD::Suld2DI64Clamp:
- case NVPTXISD::Suld2DV2I8Clamp:
- case NVPTXISD::Suld2DV2I16Clamp:
- case NVPTXISD::Suld2DV2I32Clamp:
- case NVPTXISD::Suld2DV2I64Clamp:
- case NVPTXISD::Suld2DV4I8Clamp:
- case NVPTXISD::Suld2DV4I16Clamp:
- case NVPTXISD::Suld2DV4I32Clamp:
- case NVPTXISD::Suld2DArrayI8Clamp:
- case NVPTXISD::Suld2DArrayI16Clamp:
- case NVPTXISD::Suld2DArrayI32Clamp:
- case NVPTXISD::Suld2DArrayI64Clamp:
- case NVPTXISD::Suld2DArrayV2I8Clamp:
- case NVPTXISD::Suld2DArrayV2I16Clamp:
- case NVPTXISD::Suld2DArrayV2I32Clamp:
- case NVPTXISD::Suld2DArrayV2I64Clamp:
- case NVPTXISD::Suld2DArrayV4I8Clamp:
- case NVPTXISD::Suld2DArrayV4I16Clamp:
- case NVPTXISD::Suld2DArrayV4I32Clamp:
- case NVPTXISD::Suld3DI8Clamp:
- case NVPTXISD::Suld3DI16Clamp:
- case NVPTXISD::Suld3DI32Clamp:
- case NVPTXISD::Suld3DI64Clamp:
- case NVPTXISD::Suld3DV2I8Clamp:
- case NVPTXISD::Suld3DV2I16Clamp:
- case NVPTXISD::Suld3DV2I32Clamp:
- case NVPTXISD::Suld3DV2I64Clamp:
- case NVPTXISD::Suld3DV4I8Clamp:
- case NVPTXISD::Suld3DV4I16Clamp:
- case NVPTXISD::Suld3DV4I32Clamp:
- case NVPTXISD::Suld1DI8Trap:
- case NVPTXISD::Suld1DI16Trap:
- case NVPTXISD::Suld1DI32Trap:
- case NVPTXISD::Suld1DI64Trap:
- case NVPTXISD::Suld1DV2I8Trap:
- case NVPTXISD::Suld1DV2I16Trap:
- case NVPTXISD::Suld1DV2I32Trap:
- case NVPTXISD::Suld1DV2I64Trap:
- case NVPTXISD::Suld1DV4I8Trap:
- case NVPTXISD::Suld1DV4I16Trap:
- case NVPTXISD::Suld1DV4I32Trap:
- case NVPTXISD::Suld1DArrayI8Trap:
- case NVPTXISD::Suld1DArrayI16Trap:
- case NVPTXISD::Suld1DArrayI32Trap:
- case NVPTXISD::Suld1DArrayI64Trap:
- case NVPTXISD::Suld1DArrayV2I8Trap:
- case NVPTXISD::Suld1DArrayV2I16Trap:
- case NVPTXISD::Suld1DArrayV2I32Trap:
- case NVPTXISD::Suld1DArrayV2I64Trap:
- case NVPTXISD::Suld1DArrayV4I8Trap:
- case NVPTXISD::Suld1DArrayV4I16Trap:
- case NVPTXISD::Suld1DArrayV4I32Trap:
- case NVPTXISD::Suld2DI8Trap:
- case NVPTXISD::Suld2DI16Trap:
- case NVPTXISD::Suld2DI32Trap:
- case NVPTXISD::Suld2DI64Trap:
- case NVPTXISD::Suld2DV2I8Trap:
- case NVPTXISD::Suld2DV2I16Trap:
- case NVPTXISD::Suld2DV2I32Trap:
- case NVPTXISD::Suld2DV2I64Trap:
- case NVPTXISD::Suld2DV4I8Trap:
- case NVPTXISD::Suld2DV4I16Trap:
- case NVPTXISD::Suld2DV4I32Trap:
- case NVPTXISD::Suld2DArrayI8Trap:
- case NVPTXISD::Suld2DArrayI16Trap:
- case NVPTXISD::Suld2DArrayI32Trap:
- case NVPTXISD::Suld2DArrayI64Trap:
- case NVPTXISD::Suld2DArrayV2I8Trap:
- case NVPTXISD::Suld2DArrayV2I16Trap:
- case NVPTXISD::Suld2DArrayV2I32Trap:
- case NVPTXISD::Suld2DArrayV2I64Trap:
- case NVPTXISD::Suld2DArrayV4I8Trap:
- case NVPTXISD::Suld2DArrayV4I16Trap:
- case NVPTXISD::Suld2DArrayV4I32Trap:
- case NVPTXISD::Suld3DI8Trap:
- case NVPTXISD::Suld3DI16Trap:
- case NVPTXISD::Suld3DI32Trap:
- case NVPTXISD::Suld3DI64Trap:
- case NVPTXISD::Suld3DV2I8Trap:
- case NVPTXISD::Suld3DV2I16Trap:
- case NVPTXISD::Suld3DV2I32Trap:
- case NVPTXISD::Suld3DV2I64Trap:
- case NVPTXISD::Suld3DV4I8Trap:
- case NVPTXISD::Suld3DV4I16Trap:
- case NVPTXISD::Suld3DV4I32Trap:
- case NVPTXISD::Suld1DI8Zero:
- case NVPTXISD::Suld1DI16Zero:
- case NVPTXISD::Suld1DI32Zero:
- case NVPTXISD::Suld1DI64Zero:
- case NVPTXISD::Suld1DV2I8Zero:
- case NVPTXISD::Suld1DV2I16Zero:
- case NVPTXISD::Suld1DV2I32Zero:
- case NVPTXISD::Suld1DV2I64Zero:
- case NVPTXISD::Suld1DV4I8Zero:
- case NVPTXISD::Suld1DV4I16Zero:
- case NVPTXISD::Suld1DV4I32Zero:
- case NVPTXISD::Suld1DArrayI8Zero:
- case NVPTXISD::Suld1DArrayI16Zero:
- case NVPTXISD::Suld1DArrayI32Zero:
- case NVPTXISD::Suld1DArrayI64Zero:
- case NVPTXISD::Suld1DArrayV2I8Zero:
- case NVPTXISD::Suld1DArrayV2I16Zero:
- case NVPTXISD::Suld1DArrayV2I32Zero:
- case NVPTXISD::Suld1DArrayV2I64Zero:
- case NVPTXISD::Suld1DArrayV4I8Zero:
- case NVPTXISD::Suld1DArrayV4I16Zero:
- case NVPTXISD::Suld1DArrayV4I32Zero:
- case NVPTXISD::Suld2DI8Zero:
- case NVPTXISD::Suld2DI16Zero:
- case NVPTXISD::Suld2DI32Zero:
- case NVPTXISD::Suld2DI64Zero:
- case NVPTXISD::Suld2DV2I8Zero:
- case NVPTXISD::Suld2DV2I16Zero:
- case NVPTXISD::Suld2DV2I32Zero:
- case NVPTXISD::Suld2DV2I64Zero:
- case NVPTXISD::Suld2DV4I8Zero:
- case NVPTXISD::Suld2DV4I16Zero:
- case NVPTXISD::Suld2DV4I32Zero:
- case NVPTXISD::Suld2DArrayI8Zero:
- case NVPTXISD::Suld2DArrayI16Zero:
- case NVPTXISD::Suld2DArrayI32Zero:
- case NVPTXISD::Suld2DArrayI64Zero:
- case NVPTXISD::Suld2DArrayV2I8Zero:
- case NVPTXISD::Suld2DArrayV2I16Zero:
- case NVPTXISD::Suld2DArrayV2I32Zero:
- case NVPTXISD::Suld2DArrayV2I64Zero:
- case NVPTXISD::Suld2DArrayV4I8Zero:
- case NVPTXISD::Suld2DArrayV4I16Zero:
- case NVPTXISD::Suld2DArrayV4I32Zero:
- case NVPTXISD::Suld3DI8Zero:
- case NVPTXISD::Suld3DI16Zero:
- case NVPTXISD::Suld3DI32Zero:
- case NVPTXISD::Suld3DI64Zero:
- case NVPTXISD::Suld3DV2I8Zero:
- case NVPTXISD::Suld3DV2I16Zero:
- case NVPTXISD::Suld3DV2I32Zero:
- case NVPTXISD::Suld3DV2I64Zero:
- case NVPTXISD::Suld3DV4I8Zero:
- case NVPTXISD::Suld3DV4I16Zero:
- case NVPTXISD::Suld3DV4I32Zero:
- if (trySurfaceIntrinsic(N))
- return;
- break;
case ISD::AND:
case ISD::SRA:
case ISD::SRL:
@@ -2604,1053 +2259,6 @@ bool NVPTXDAGToDAGISel::tryStoreParam(SDNode *N) {
return true;
}
-bool NVPTXDAGToDAGISel::tryTextureIntrinsic(SDNode *N) {
- unsigned Opc = 0;
-
- switch (N->getOpcode()) {
- default: return false;
- case NVPTXISD::Tex1DFloatS32:
- Opc = NVPTX::TEX_1D_F32_S32_RR;
- break;
- case NVPTXISD::Tex1DFloatFloat:
- Opc = NVPTX::TEX_1D_F32_F32_RR;
- break;
- case NVPTXISD::Tex1DFloatFloatLevel:
- Opc = NVPTX::TEX_1D_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex1DFloatFloatGrad:
- Opc = NVPTX::TEX_1D_F32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex1DS32S32:
- Opc = NVPTX::TEX_1D_S32_S32_RR;
- break;
- case NVPTXISD::Tex1DS32Float:
- Opc = NVPTX::TEX_1D_S32_F32_RR;
- break;
- case NVPTXISD::Tex1DS32FloatLevel:
- Opc = NVPTX::TEX_1D_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex1DS32FloatGrad:
- Opc = NVPTX::TEX_1D_S32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex1DU32S32:
- Opc = NVPTX::TEX_1D_U32_S32_RR;
- break;
- case NVPTXISD::Tex1DU32Float:
- Opc = NVPTX::TEX_1D_U32_F32_RR;
- break;
- case NVPTXISD::Tex1DU32FloatLevel:
- Opc = NVPTX::TEX_1D_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex1DU32FloatGrad:
- Opc = NVPTX::TEX_1D_U32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex1DArrayFloatS32:
- Opc = NVPTX::TEX_1D_ARRAY_F32_S32_RR;
- break;
- case NVPTXISD::Tex1DArrayFloatFloat:
- Opc = NVPTX::TEX_1D_ARRAY_F32_F32_RR;
- break;
- case NVPTXISD::Tex1DArrayFloatFloatLevel:
- Opc = NVPTX::TEX_1D_ARRAY_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex1DArrayFloatFloatGrad:
- Opc = NVPTX::TEX_1D_ARRAY_F32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex1DArrayS32S32:
- Opc = NVPTX::TEX_1D_ARRAY_S32_S32_RR;
- break;
- case NVPTXISD::Tex1DArrayS32Float:
- Opc = NVPTX::TEX_1D_ARRAY_S32_F32_RR;
- break;
- case NVPTXISD::Tex1DArrayS32FloatLevel:
- Opc = NVPTX::TEX_1D_ARRAY_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex1DArrayS32FloatGrad:
- Opc = NVPTX::TEX_1D_ARRAY_S32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex1DArrayU32S32:
- Opc = NVPTX::TEX_1D_ARRAY_U32_S32_RR;
- break;
- case NVPTXISD::Tex1DArrayU32Float:
- Opc = NVPTX::TEX_1D_ARRAY_U32_F32_RR;
- break;
- case NVPTXISD::Tex1DArrayU32FloatLevel:
- Opc = NVPTX::TEX_1D_ARRAY_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex1DArrayU32FloatGrad:
- Opc = NVPTX::TEX_1D_ARRAY_U32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex2DFloatS32:
- Opc = NVPTX::TEX_2D_F32_S32_RR;
- break;
- case NVPTXISD::Tex2DFloatFloat:
- Opc = NVPTX::TEX_2D_F32_F32_RR;
- break;
- case NVPTXISD::Tex2DFloatFloatLevel:
- Opc = NVPTX::TEX_2D_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex2DFloatFloatGrad:
- Opc = NVPTX::TEX_2D_F32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex2DS32S32:
- Opc = NVPTX::TEX_2D_S32_S32_RR;
- break;
- case NVPTXISD::Tex2DS32Float:
- Opc = NVPTX::TEX_2D_S32_F32_RR;
- break;
- case NVPTXISD::Tex2DS32FloatLevel:
- Opc = NVPTX::TEX_2D_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex2DS32FloatGrad:
- Opc = NVPTX::TEX_2D_S32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex2DU32S32:
- Opc = NVPTX::TEX_2D_U32_S32_RR;
- break;
- case NVPTXISD::Tex2DU32Float:
- Opc = NVPTX::TEX_2D_U32_F32_RR;
- break;
- case NVPTXISD::Tex2DU32FloatLevel:
- Opc = NVPTX::TEX_2D_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex2DU32FloatGrad:
- Opc = NVPTX::TEX_2D_U32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex2DArrayFloatS32:
- Opc = NVPTX::TEX_2D_ARRAY_F32_S32_RR;
- break;
- case NVPTXISD::Tex2DArrayFloatFloat:
- Opc = NVPTX::TEX_2D_ARRAY_F32_F32_RR;
- break;
- case NVPTXISD::Tex2DArrayFloatFloatLevel:
- Opc = NVPTX::TEX_2D_ARRAY_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex2DArrayFloatFloatGrad:
- Opc = NVPTX::TEX_2D_ARRAY_F32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex2DArrayS32S32:
- Opc = NVPTX::TEX_2D_ARRAY_S32_S32_RR;
- break;
- case NVPTXISD::Tex2DArrayS32Float:
- Opc = NVPTX::TEX_2D_ARRAY_S32_F32_RR;
- break;
- case NVPTXISD::Tex2DArrayS32FloatLevel:
- Opc = NVPTX::TEX_2D_ARRAY_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex2DArrayS32FloatGrad:
- Opc = NVPTX::TEX_2D_ARRAY_S32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex2DArrayU32S32:
- Opc = NVPTX::TEX_2D_ARRAY_U32_S32_RR;
- break;
- case NVPTXISD::Tex2DArrayU32Float:
- Opc = NVPTX::TEX_2D_ARRAY_U32_F32_RR;
- break;
- case NVPTXISD::Tex2DArrayU32FloatLevel:
- Opc = NVPTX::TEX_2D_ARRAY_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex2DArrayU32FloatGrad:
- Opc = NVPTX::TEX_2D_ARRAY_U32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex3DFloatS32:
- Opc = NVPTX::TEX_3D_F32_S32_RR;
- break;
- case NVPTXISD::Tex3DFloatFloat:
- Opc = NVPTX::TEX_3D_F32_F32_RR;
- break;
- case NVPTXISD::Tex3DFloatFloatLevel:
- Opc = NVPTX::TEX_3D_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex3DFloatFloatGrad:
- Opc = NVPTX::TEX_3D_F32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex3DS32S32:
- Opc = NVPTX::TEX_3D_S32_S32_RR;
- break;
- case NVPTXISD::Tex3DS32Float:
- Opc = NVPTX::TEX_3D_S32_F32_RR;
- break;
- case NVPTXISD::Tex3DS32FloatLevel:
- Opc = NVPTX::TEX_3D_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex3DS32FloatGrad:
- Opc = NVPTX::TEX_3D_S32_F32_GRAD_RR;
- break;
- case NVPTXISD::Tex3DU32S32:
- Opc = NVPTX::TEX_3D_U32_S32_RR;
- break;
- case NVPTXISD::Tex3DU32Float:
- Opc = NVPTX::TEX_3D_U32_F32_RR;
- break;
- case NVPTXISD::Tex3DU32FloatLevel:
- Opc = NVPTX::TEX_3D_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tex3DU32FloatGrad:
- Opc = NVPTX::TEX_3D_U32_F32_GRAD_RR;
- break;
- case NVPTXISD::TexCubeFloatFloat:
- Opc = NVPTX::TEX_CUBE_F32_F32_RR;
- break;
- case NVPTXISD::TexCubeFloatFloatLevel:
- Opc = NVPTX::TEX_CUBE_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::TexCubeS32Float:
- Opc = NVPTX::TEX_CUBE_S32_F32_RR;
- break;
- case NVPTXISD::TexCubeS32FloatLevel:
- Opc = NVPTX::TEX_CUBE_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::TexCubeU32Float:
- Opc = NVPTX::TEX_CUBE_U32_F32_RR;
- break;
- case NVPTXISD::TexCubeU32FloatLevel:
- Opc = NVPTX::TEX_CUBE_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::TexCubeArrayFloatFloat:
- Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_RR;
- break;
- case NVPTXISD::TexCubeArrayFloatFloatLevel:
- Opc = NVPTX::TEX_CUBE_ARRAY_F32_F32_LEVEL_RR;
- break;
- case NVPTXISD::TexCubeArrayS32Float:
- Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_RR;
- break;
- case NVPTXISD::TexCubeArrayS32FloatLevel:
- Opc = NVPTX::TEX_CUBE_ARRAY_S32_F32_LEVEL_RR;
- break;
- case NVPTXISD::TexCubeArrayU32Float:
- Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_RR;
- break;
- case NVPTXISD::TexCubeArrayU32FloatLevel:
- Opc = NVPTX::TEX_CUBE_ARRAY_U32_F32_LEVEL_RR;
- break;
- case NVPTXISD::Tld4R2DFloatFloat:
- Opc = NVPTX::TLD4_R_2D_F32_F32_RR;
- break;
- case NVPTXISD::Tld4G2DFloatFloat:
- Opc = NVPTX::TLD4_G_2D_F32_F32_RR;
- break;
- case NVPTXISD::Tld4B2DFloatFloat:
- Opc = NVPTX::TLD4_B_2D_F32_F32_RR;
- break;
- case NVPTXISD::Tld4A2DFloatFloat:
- Opc = NVPTX::TLD4_A_2D_F32_F32_RR;
- break;
- case NVPTXISD::Tld4R2DS64Float:
- Opc = NVPTX::TLD4_R_2D_S32_F32_RR;
- break;
- case NVPTXISD::Tld4G2DS64Float:
- Opc = NVPTX::TLD4_G_2D_S32_F32_RR;
- break;
- case NVPTXISD::Tld4B2DS64Float:
- Opc = NVPTX::TLD4_B_2D_S32_F32_RR;
- break;
- case NVPTXISD::Tld4A2DS64Float:
- Opc = NVPTX::TLD4_A_2D_S32_F32_RR;
- break;
- case NVPTXISD::Tld4R2DU64Float:
- Opc = NVPTX::TLD4_R_2D_U32_F32_RR;
- break;
- case NVPTXISD::Tld4G2DU64Float:
- Opc = NVPTX::TLD4_G_2D_U32_F32_RR;
- break;
- case NVPTXISD::Tld4B2DU64Float:
- Opc = NVPTX::TLD4_B_2D_U32_F32_RR;
- break;
- case NVPTXISD::Tld4A2DU64Float:
- Opc = NVPTX::TLD4_A_2D_U32_F32_RR;
- break;
- case NVPTXISD::TexUnified1DFloatS32:
- Opc = NVPTX::TEX_UNIFIED_1D_F32_S32_R;
- break;
- case NVPTXISD::TexUnified1DFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_R;
- break;
- case NVPTXISD::TexUnified1DFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified1DFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_1D_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified1DS32S32:
- Opc = NVPTX::TEX_UNIFIED_1D_S32_S32_R;
- break;
- case NVPTXISD::TexUnified1DS32Float:
- Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_R;
- break;
- case NVPTXISD::TexUnified1DS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified1DS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_1D_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified1DU32S32:
- Opc = NVPTX::TEX_UNIFIED_1D_U32_S32_R;
- break;
- case NVPTXISD::TexUnified1DU32Float:
- Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_R;
- break;
- case NVPTXISD::TexUnified1DU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified1DU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_1D_U32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified1DArrayFloatS32:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_S32_R;
- break;
- case NVPTXISD::TexUnified1DArrayFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_R;
- break;
- case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified1DArrayS32S32:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_S32_R;
- break;
- case NVPTXISD::TexUnified1DArrayS32Float:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_R;
- break;
- case NVPTXISD::TexUnified1DArrayS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified1DArrayS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified1DArrayU32S32:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_S32_R;
- break;
- case NVPTXISD::TexUnified1DArrayU32Float:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_R;
- break;
- case NVPTXISD::TexUnified1DArrayU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified1DArrayU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified2DFloatS32:
- Opc = NVPTX::TEX_UNIFIED_2D_F32_S32_R;
- break;
- case NVPTXISD::TexUnified2DFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_R;
- break;
- case NVPTXISD::TexUnified2DFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified2DFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_2D_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified2DS32S32:
- Opc = NVPTX::TEX_UNIFIED_2D_S32_S32_R;
- break;
- case NVPTXISD::TexUnified2DS32Float:
- Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_R;
- break;
- case NVPTXISD::TexUnified2DS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified2DS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_2D_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified2DU32S32:
- Opc = NVPTX::TEX_UNIFIED_2D_U32_S32_R;
- break;
- case NVPTXISD::TexUnified2DU32Float:
- Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_R;
- break;
- case NVPTXISD::TexUnified2DU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified2DU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_2D_U32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified2DArrayFloatS32:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_S32_R;
- break;
- case NVPTXISD::TexUnified2DArrayFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_R;
- break;
- case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified2DArrayS32S32:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_S32_R;
- break;
- case NVPTXISD::TexUnified2DArrayS32Float:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_R;
- break;
- case NVPTXISD::TexUnified2DArrayS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified2DArrayS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified2DArrayU32S32:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_S32_R;
- break;
- case NVPTXISD::TexUnified2DArrayU32Float:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_R;
- break;
- case NVPTXISD::TexUnified2DArrayU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified2DArrayU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified3DFloatS32:
- Opc = NVPTX::TEX_UNIFIED_3D_F32_S32_R;
- break;
- case NVPTXISD::TexUnified3DFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_R;
- break;
- case NVPTXISD::TexUnified3DFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified3DFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_3D_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified3DS32S32:
- Opc = NVPTX::TEX_UNIFIED_3D_S32_S32_R;
- break;
- case NVPTXISD::TexUnified3DS32Float:
- Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_R;
- break;
- case NVPTXISD::TexUnified3DS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified3DS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_3D_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnified3DU32S32:
- Opc = NVPTX::TEX_UNIFIED_3D_U32_S32_R;
- break;
- case NVPTXISD::TexUnified3DU32Float:
- Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_R;
- break;
- case NVPTXISD::TexUnified3DU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnified3DU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_3D_U32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnifiedCubeFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnifiedCubeS32Float:
- Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnifiedCubeU32Float:
- Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayS32Float:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayU32Float:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_R;
- break;
- case NVPTXISD::Tld4UnifiedR2DFloatFloat:
- Opc = NVPTX::TLD4_UNIFIED_R_2D_F32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedG2DFloatFloat:
- Opc = NVPTX::TLD4_UNIFIED_G_2D_F32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedB2DFloatFloat:
- Opc = NVPTX::TLD4_UNIFIED_B_2D_F32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedA2DFloatFloat:
- Opc = NVPTX::TLD4_UNIFIED_A_2D_F32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedR2DS64Float:
- Opc = NVPTX::TLD4_UNIFIED_R_2D_S32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedG2DS64Float:
- Opc = NVPTX::TLD4_UNIFIED_G_2D_S32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedB2DS64Float:
- Opc = NVPTX::TLD4_UNIFIED_B_2D_S32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedA2DS64Float:
- Opc = NVPTX::TLD4_UNIFIED_A_2D_S32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedR2DU64Float:
- Opc = NVPTX::TLD4_UNIFIED_R_2D_U32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedG2DU64Float:
- Opc = NVPTX::TLD4_UNIFIED_G_2D_U32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedB2DU64Float:
- Opc = NVPTX::TLD4_UNIFIED_B_2D_U32_F32_R;
- break;
- case NVPTXISD::Tld4UnifiedA2DU64Float:
- Opc = NVPTX::TLD4_UNIFIED_A_2D_U32_F32_R;
- break;
- case NVPTXISD::TexUnifiedCubeFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_CUBE_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnifiedCubeS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_CUBE_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnifiedCubeU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_CUBE_U32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayS32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R;
- break;
- case NVPTXISD::TexUnifiedCubeArrayU32FloatGrad:
- Opc = NVPTX::TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R;
- break;
- }
-
- // Copy over operands
- SmallVector<SDValue, 8> Ops(drop_begin(N->ops()));
- Ops.push_back(N->getOperand(0)); // Move chain to the back.
-
- ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
- return true;
-}
-
-bool NVPTXDAGToDAGISel::trySurfaceIntrinsic(SDNode *N) {
- unsigned Opc = 0;
- switch (N->getOpcode()) {
- default: return false;
- case NVPTXISD::Suld1DI8Clamp:
- Opc = NVPTX::SULD_1D_I8_CLAMP_R;
- break;
- case NVPTXISD::Suld1DI16Clamp:
- Opc = NVPTX::SULD_1D_I16_CLAMP_R;
- break;
- case NVPTXISD::Suld1DI32Clamp:
- Opc = NVPTX::SULD_1D_I32_CLAMP_R;
- break;
- case NVPTXISD::Suld1DI64Clamp:
- Opc = NVPTX::SULD_1D_I64_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV2I8Clamp:
- Opc = NVPTX::SULD_1D_V2I8_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV2I16Clamp:
- Opc = NVPTX::SULD_1D_V2I16_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV2I32Clamp:
- Opc = NVPTX::SULD_1D_V2I32_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV2I64Clamp:
- Opc = NVPTX::SULD_1D_V2I64_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV4I8Clamp:
- Opc = NVPTX::SULD_1D_V4I8_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV4I16Clamp:
- Opc = NVPTX::SULD_1D_V4I16_CLAMP_R;
- break;
- case NVPTXISD::Suld1DV4I32Clamp:
- Opc = NVPTX::SULD_1D_V4I32_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayI8Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_I8_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayI16Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_I16_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayI32Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_I32_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayI64Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_I64_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I8Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V2I8_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I16Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V2I16_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I32Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V2I32_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I64Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V2I64_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV4I8Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V4I8_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV4I16Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V4I16_CLAMP_R;
- break;
- case NVPTXISD::Suld1DArrayV4I32Clamp:
- Opc = NVPTX::SULD_1D_ARRAY_V4I32_CLAMP_R;
- break;
- case NVPTXISD::Suld2DI8Clamp:
- Opc = NVPTX::SULD_2D_I8_CLAMP_R;
- break;
- case NVPTXISD::Suld2DI16Clamp:
- Opc = NVPTX::SULD_2D_I16_CLAMP_R;
- break;
- case NVPTXISD::Suld2DI32Clamp:
- Opc = NVPTX::SULD_2D_I32_CLAMP_R;
- break;
- case NVPTXISD::Suld2DI64Clamp:
- Opc = NVPTX::SULD_2D_I64_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV2I8Clamp:
- Opc = NVPTX::SULD_2D_V2I8_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV2I16Clamp:
- Opc = NVPTX::SULD_2D_V2I16_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV2I32Clamp:
- Opc = NVPTX::SULD_2D_V2I32_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV2I64Clamp:
- Opc = NVPTX::SULD_2D_V2I64_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV4I8Clamp:
- Opc = NVPTX::SULD_2D_V4I8_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV4I16Clamp:
- Opc = NVPTX::SULD_2D_V4I16_CLAMP_R;
- break;
- case NVPTXISD::Suld2DV4I32Clamp:
- Opc = NVPTX::SULD_2D_V4I32_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayI8Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_I8_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayI16Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_I16_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayI32Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_I32_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayI64Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_I64_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I8Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V2I8_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I16Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V2I16_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I32Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V2I32_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I64Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V2I64_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV4I8Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V4I8_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV4I16Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V4I16_CLAMP_R;
- break;
- case NVPTXISD::Suld2DArrayV4I32Clamp:
- Opc = NVPTX::SULD_2D_ARRAY_V4I32_CLAMP_R;
- break;
- case NVPTXISD::Suld3DI8Clamp:
- Opc = NVPTX::SULD_3D_I8_CLAMP_R;
- break;
- case NVPTXISD::Suld3DI16Clamp:
- Opc = NVPTX::SULD_3D_I16_CLAMP_R;
- break;
- case NVPTXISD::Suld3DI32Clamp:
- Opc = NVPTX::SULD_3D_I32_CLAMP_R;
- break;
- case NVPTXISD::Suld3DI64Clamp:
- Opc = NVPTX::SULD_3D_I64_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV2I8Clamp:
- Opc = NVPTX::SULD_3D_V2I8_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV2I16Clamp:
- Opc = NVPTX::SULD_3D_V2I16_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV2I32Clamp:
- Opc = NVPTX::SULD_3D_V2I32_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV2I64Clamp:
- Opc = NVPTX::SULD_3D_V2I64_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV4I8Clamp:
- Opc = NVPTX::SULD_3D_V4I8_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV4I16Clamp:
- Opc = NVPTX::SULD_3D_V4I16_CLAMP_R;
- break;
- case NVPTXISD::Suld3DV4I32Clamp:
- Opc = NVPTX::SULD_3D_V4I32_CLAMP_R;
- break;
- case NVPTXISD::Suld1DI8Trap:
- Opc = NVPTX::SULD_1D_I8_TRAP_R;
- break;
- case NVPTXISD::Suld1DI16Trap:
- Opc = NVPTX::SULD_1D_I16_TRAP_R;
- break;
- case NVPTXISD::Suld1DI32Trap:
- Opc = NVPTX::SULD_1D_I32_TRAP_R;
- break;
- case NVPTXISD::Suld1DI64Trap:
- Opc = NVPTX::SULD_1D_I64_TRAP_R;
- break;
- case NVPTXISD::Suld1DV2I8Trap:
- Opc = NVPTX::SULD_1D_V2I8_TRAP_R;
- break;
- case NVPTXISD::Suld1DV2I16Trap:
- Opc = NVPTX::SULD_1D_V2I16_TRAP_R;
- break;
- case NVPTXISD::Suld1DV2I32Trap:
- Opc = NVPTX::SULD_1D_V2I32_TRAP_R;
- break;
- case NVPTXISD::Suld1DV2I64Trap:
- Opc = NVPTX::SULD_1D_V2I64_TRAP_R;
- break;
- case NVPTXISD::Suld1DV4I8Trap:
- Opc = NVPTX::SULD_1D_V4I8_TRAP_R;
- break;
- case NVPTXISD::Suld1DV4I16Trap:
- Opc = NVPTX::SULD_1D_V4I16_TRAP_R;
- break;
- case NVPTXISD::Suld1DV4I32Trap:
- Opc = NVPTX::SULD_1D_V4I32_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayI8Trap:
- Opc = NVPTX::SULD_1D_ARRAY_I8_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayI16Trap:
- Opc = NVPTX::SULD_1D_ARRAY_I16_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayI32Trap:
- Opc = NVPTX::SULD_1D_ARRAY_I32_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayI64Trap:
- Opc = NVPTX::SULD_1D_ARRAY_I64_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I8Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V2I8_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I16Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V2I16_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I32Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V2I32_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV2I64Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V2I64_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV4I8Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V4I8_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV4I16Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V4I16_TRAP_R;
- break;
- case NVPTXISD::Suld1DArrayV4I32Trap:
- Opc = NVPTX::SULD_1D_ARRAY_V4I32_TRAP_R;
- break;
- case NVPTXISD::Suld2DI8Trap:
- Opc = NVPTX::SULD_2D_I8_TRAP_R;
- break;
- case NVPTXISD::Suld2DI16Trap:
- Opc = NVPTX::SULD_2D_I16_TRAP_R;
- break;
- case NVPTXISD::Suld2DI32Trap:
- Opc = NVPTX::SULD_2D_I32_TRAP_R;
- break;
- case NVPTXISD::Suld2DI64Trap:
- Opc = NVPTX::SULD_2D_I64_TRAP_R;
- break;
- case NVPTXISD::Suld2DV2I8Trap:
- Opc = NVPTX::SULD_2D_V2I8_TRAP_R;
- break;
- case NVPTXISD::Suld2DV2I16Trap:
- Opc = NVPTX::SULD_2D_V2I16_TRAP_R;
- break;
- case NVPTXISD::Suld2DV2I32Trap:
- Opc = NVPTX::SULD_2D_V2I32_TRAP_R;
- break;
- case NVPTXISD::Suld2DV2I64Trap:
- Opc = NVPTX::SULD_2D_V2I64_TRAP_R;
- break;
- case NVPTXISD::Suld2DV4I8Trap:
- Opc = NVPTX::SULD_2D_V4I8_TRAP_R;
- break;
- case NVPTXISD::Suld2DV4I16Trap:
- Opc = NVPTX::SULD_2D_V4I16_TRAP_R;
- break;
- case NVPTXISD::Suld2DV4I32Trap:
- Opc = NVPTX::SULD_2D_V4I32_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayI8Trap:
- Opc = NVPTX::SULD_2D_ARRAY_I8_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayI16Trap:
- Opc = NVPTX::SULD_2D_ARRAY_I16_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayI32Trap:
- Opc = NVPTX::SULD_2D_ARRAY_I32_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayI64Trap:
- Opc = NVPTX::SULD_2D_ARRAY_I64_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I8Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V2I8_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I16Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V2I16_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I32Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V2I32_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV2I64Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V2I64_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV4I8Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V4I8_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV4I16Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V4I16_TRAP_R;
- break;
- case NVPTXISD::Suld2DArrayV4I32Trap:
- Opc = NVPTX::SULD_2D_ARRAY_V4I32_TRAP_R;
- break;
- case NVPTXISD::Suld3DI8Trap:
- Opc = NVPTX::SULD_3D_I8_TRAP_R;
- break;
- case NVPTXISD::Suld3DI16Trap:
- Opc = NVPTX::SULD_3D_I16_TRAP_R;
- break;
- case NVPTXISD::Suld3DI32Trap:
- Opc = NVPTX::SULD_3D_I32_TRAP_R;
- break;
- case NVPTXISD::Suld3DI64Trap:
- Opc = NVPTX::SULD_3D_I64_TRAP_R;
- break;
- case NVPTXISD::Suld3DV2I8Trap:
- Opc = NVPTX::SULD_3D_V2I8_TRAP_R;
- break;
- case NVPTXISD::Suld3DV2I16Trap:
- Opc = NVPTX::SULD_3D_V2I16_TRAP_R;
- break;
- case NVPTXISD::Suld3DV2I32Trap:
- Opc = NVPTX::SULD_3D_V2I32_TRAP_R;
- break;
- case NVPTXISD::Suld3DV2I64Trap:
- Opc = NVPTX::SULD_3D_V2I64_TRAP_R;
- break;
- case NVPTXISD::Suld3DV4I8Trap:
- Opc = NVPTX::SULD_3D_V4I8_TRAP_R;
- break;
- case NVPTXISD::Suld3DV4I16Trap:
- Opc = NVPTX::SULD_3D_V4I16_TRAP_R;
- break;
- case NVPTXISD::Suld3DV4I32Trap:
- Opc = NVPTX::SULD_3D_V4I32_TRAP_R;
- break;
- case NVPTXISD::Suld1DI8Zero:
- Opc = NVPTX::SULD_1D_I8_ZERO_R;
- break;
- case NVPTXISD::Suld1DI16Zero:
- Opc = NVPTX::SULD_1D_I16_ZERO_R;
- break;
- case NVPTXISD::Suld1DI32Zero:
- Opc = NVPTX::SULD_1D_I32_ZERO_R;
- break;
- case NVPTXISD::Suld1DI64Zero:
- Opc = NVPTX::SULD_1D_I64_ZERO_R;
- break;
- case NVPTXISD::Suld1DV2I8Zero:
- Opc = NVPTX::SULD_1D_V2I8_ZERO_R;
- break;
- case NVPTXISD::Suld1DV2I16Zero:
- Opc = NVPTX::SULD_1D_V2I16_ZERO_R;
- break;
- case NVPTXISD::Suld1DV2I32Zero:
- Opc = NVPTX::SULD_1D_V2I32_ZERO_R;
- break;
- case NVPTXISD::Suld1DV2I64Zero:
- Opc = NVPTX::SULD_1D_V2I64_ZERO_R;
- break;
- case NVPTXISD::Suld1DV4I8Zero:
- Opc = NVPTX::SULD_1D_V4I8_ZERO_R;
- break;
- case NVPTXISD::Suld1DV4I16Zero:
- Opc = NVPTX::SULD_1D_V4I16_ZERO_R;
- break;
- case NVPTXISD::Suld1DV4I32Zero:
- Opc = NVPTX::SULD_1D_V4I32_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayI8Zero:
- Opc = NVPTX::SULD_1D_ARRAY_I8_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayI16Zero:
- Opc = NVPTX::SULD_1D_ARRAY_I16_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayI32Zero:
- Opc = NVPTX::SULD_1D_ARRAY_I32_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayI64Zero:
- Opc = NVPTX::SULD_1D_ARRAY_I64_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV2I8Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V2I8_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV2I16Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V2I16_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV2I32Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V2I32_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV2I64Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V2I64_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV4I8Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V4I8_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV4I16Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V4I16_ZERO_R;
- break;
- case NVPTXISD::Suld1DArrayV4I32Zero:
- Opc = NVPTX::SULD_1D_ARRAY_V4I32_ZERO_R;
- break;
- case NVPTXISD::Suld2DI8Zero:
- Opc = NVPTX::SULD_2D_I8_ZERO_R;
- break;
- case NVPTXISD::Suld2DI16Zero:
- Opc = NVPTX::SULD_2D_I16_ZERO_R;
- break;
- case NVPTXISD::Suld2DI32Zero:
- Opc = NVPTX::SULD_2D_I32_ZERO_R;
- break;
- case NVPTXISD::Suld2DI64Zero:
- Opc = NVPTX::SULD_2D_I64_ZERO_R;
- break;
- case NVPTXISD::Suld2DV2I8Zero:
- Opc = NVPTX::SULD_2D_V2I8_ZERO_R;
- break;
- case NVPTXISD::Suld2DV2I16Zero:
- Opc = NVPTX::SULD_2D_V2I16_ZERO_R;
- break;
- case NVPTXISD::Suld2DV2I32Zero:
- Opc = NVPTX::SULD_2D_V2I32_ZERO_R;
- break;
- case NVPTXISD::Suld2DV2I64Zero:
- Opc = NVPTX::SULD_2D_V2I64_ZERO_R;
- break;
- case NVPTXISD::Suld2DV4I8Zero:
- Opc = NVPTX::SULD_2D_V4I8_ZERO_R;
- break;
- case NVPTXISD::Suld2DV4I16Zero:
- Opc = NVPTX::SULD_2D_V4I16_ZERO_R;
- break;
- case NVPTXISD::Suld2DV4I32Zero:
- Opc = NVPTX::SULD_2D_V4I32_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayI8Zero:
- Opc = NVPTX::SULD_2D_ARRAY_I8_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayI16Zero:
- Opc = NVPTX::SULD_2D_ARRAY_I16_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayI32Zero:
- Opc = NVPTX::SULD_2D_ARRAY_I32_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayI64Zero:
- Opc = NVPTX::SULD_2D_ARRAY_I64_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV2I8Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V2I8_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV2I16Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V2I16_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV2I32Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V2I32_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV2I64Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V2I64_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV4I8Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V4I8_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV4I16Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V4I16_ZERO_R;
- break;
- case NVPTXISD::Suld2DArrayV4I32Zero:
- Opc = NVPTX::SULD_2D_ARRAY_V4I32_ZERO_R;
- break;
- case NVPTXISD::Suld3DI8Zero:
- Opc = NVPTX::SULD_3D_I8_ZERO_R;
- break;
- case NVPTXISD::Suld3DI16Zero:
- Opc = NVPTX::SULD_3D_I16_ZERO_R;
- break;
- case NVPTXISD::Suld3DI32Zero:
- Opc = NVPTX::SULD_3D_I32_ZERO_R;
- break;
- case NVPTXISD::Suld3DI64Zero:
- Opc = NVPTX::SULD_3D_I64_ZERO_R;
- break;
- case NVPTXISD::Suld3DV2I8Zero:
- Opc = NVPTX::SULD_3D_V2I8_ZERO_R;
- break;
- case NVPTXISD::Suld3DV2I16Zero:
- Opc = NVPTX::SULD_3D_V2I16_ZERO_R;
- break;
- case NVPTXISD::Suld3DV2I32Zero:
- Opc = NVPTX::SULD_3D_V2I32_ZERO_R;
- break;
- case NVPTXISD::Suld3DV2I64Zero:
- Opc = NVPTX::SULD_3D_V2I64_ZERO_R;
- break;
- case NVPTXISD::Suld3DV4I8Zero:
- Opc = NVPTX::SULD_3D_V4I8_ZERO_R;
- break;
- case NVPTXISD::Suld3DV4I16Zero:
- Opc = NVPTX::SULD_3D_V4I16_ZERO_R;
- break;
- case NVPTXISD::Suld3DV4I32Zero:
- Opc = NVPTX::SULD_3D_V4I32_ZERO_R;
- break;
- }
-
- // Copy over operands
- SmallVector<SDValue, 8> Ops(drop_begin(N->ops()));
- Ops.push_back(N->getOperand(0)); // Move chain to the back.
-
- ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops));
- return true;
-}
-
-
/// SelectBFE - Look for instruction sequences that can be made more efficient
/// by using the 'bfe' (bit-field extract) PTX instruction
bool NVPTXDAGToDAGISel::tryBFE(SDNode *N) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
index 8cc270a6829009..c307f28fcc6c0a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
@@ -83,8 +83,6 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
bool tryStoreParam(SDNode *N);
bool tryFence(SDNode *N);
void SelectAddrSpaceCast(SDNode *N);
- bool tryTextureIntrinsic(SDNode *N);
- bool trySurfaceIntrinsic(SDNode *N);
bool tryBFE(SDNode *N);
bool tryConstantFP(SDNode *N);
bool SelectSETP_F16X2(SDNode *N);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index ce94dded815b8f..a02607efb7fc28 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -990,361 +990,6 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
MAKE_CASE(NVPTXISD::BrxEnd)
MAKE_CASE(NVPTXISD::BrxItem)
MAKE_CASE(NVPTXISD::BrxStart)
- MAKE_CASE(NVPTXISD::Tex1DFloatS32)
- MAKE_CASE(NVPTXISD::Tex1DFloatFloat)
- MAKE_CASE(NVPTXISD::Tex1DFloatFloatLevel)
- MAKE_CASE(NVPTXISD::Tex1DFloatFloatGrad)
- MAKE_CASE(NVPTXISD::Tex1DS32S32)
- MAKE_CASE(NVPTXISD::Tex1DS32Float)
- MAKE_CASE(NVPTXISD::Tex1DS32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex1DS32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex1DU32S32)
- MAKE_CASE(NVPTXISD::Tex1DU32Float)
- MAKE_CASE(NVPTXISD::Tex1DU32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex1DU32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex1DArrayFloatS32)
- MAKE_CASE(NVPTXISD::Tex1DArrayFloatFloat)
- MAKE_CASE(NVPTXISD::Tex1DArrayFloatFloatLevel)
- MAKE_CASE(NVPTXISD::Tex1DArrayFloatFloatGrad)
- MAKE_CASE(NVPTXISD::Tex1DArrayS32S32)
- MAKE_CASE(NVPTXISD::Tex1DArrayS32Float)
- MAKE_CASE(NVPTXISD::Tex1DArrayS32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex1DArrayS32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex1DArrayU32S32)
- MAKE_CASE(NVPTXISD::Tex1DArrayU32Float)
- MAKE_CASE(NVPTXISD::Tex1DArrayU32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex1DArrayU32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex2DFloatS32)
- MAKE_CASE(NVPTXISD::Tex2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tex2DFloatFloatLevel)
- MAKE_CASE(NVPTXISD::Tex2DFloatFloatGrad)
- MAKE_CASE(NVPTXISD::Tex2DS32S32)
- MAKE_CASE(NVPTXISD::Tex2DS32Float)
- MAKE_CASE(NVPTXISD::Tex2DS32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex2DS32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex2DU32S32)
- MAKE_CASE(NVPTXISD::Tex2DU32Float)
- MAKE_CASE(NVPTXISD::Tex2DU32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex2DU32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex2DArrayFloatS32)
- MAKE_CASE(NVPTXISD::Tex2DArrayFloatFloat)
- MAKE_CASE(NVPTXISD::Tex2DArrayFloatFloatLevel)
- MAKE_CASE(NVPTXISD::Tex2DArrayFloatFloatGrad)
- MAKE_CASE(NVPTXISD::Tex2DArrayS32S32)
- MAKE_CASE(NVPTXISD::Tex2DArrayS32Float)
- MAKE_CASE(NVPTXISD::Tex2DArrayS32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex2DArrayS32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex2DArrayU32S32)
- MAKE_CASE(NVPTXISD::Tex2DArrayU32Float)
- MAKE_CASE(NVPTXISD::Tex2DArrayU32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex2DArrayU32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex3DFloatS32)
- MAKE_CASE(NVPTXISD::Tex3DFloatFloat)
- MAKE_CASE(NVPTXISD::Tex3DFloatFloatLevel)
- MAKE_CASE(NVPTXISD::Tex3DFloatFloatGrad)
- MAKE_CASE(NVPTXISD::Tex3DS32S32)
- MAKE_CASE(NVPTXISD::Tex3DS32Float)
- MAKE_CASE(NVPTXISD::Tex3DS32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex3DS32FloatGrad)
- MAKE_CASE(NVPTXISD::Tex3DU32S32)
- MAKE_CASE(NVPTXISD::Tex3DU32Float)
- MAKE_CASE(NVPTXISD::Tex3DU32FloatLevel)
- MAKE_CASE(NVPTXISD::Tex3DU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexCubeFloatFloat)
- MAKE_CASE(NVPTXISD::TexCubeFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexCubeS32Float)
- MAKE_CASE(NVPTXISD::TexCubeS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexCubeU32Float)
- MAKE_CASE(NVPTXISD::TexCubeU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexCubeArrayFloatFloat)
- MAKE_CASE(NVPTXISD::TexCubeArrayFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexCubeArrayS32Float)
- MAKE_CASE(NVPTXISD::TexCubeArrayS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexCubeArrayU32Float)
- MAKE_CASE(NVPTXISD::TexCubeArrayU32FloatLevel)
- MAKE_CASE(NVPTXISD::Tld4R2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4G2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4B2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4A2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4R2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4G2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4B2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4A2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4R2DU64Float)
- MAKE_CASE(NVPTXISD::Tld4G2DU64Float)
- MAKE_CASE(NVPTXISD::Tld4B2DU64Float)
- MAKE_CASE(NVPTXISD::Tld4A2DU64Float)
-
- MAKE_CASE(NVPTXISD::TexUnified1DFloatS32)
- MAKE_CASE(NVPTXISD::TexUnified1DFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnified1DFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified1DFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified1DS32S32)
- MAKE_CASE(NVPTXISD::TexUnified1DS32Float)
- MAKE_CASE(NVPTXISD::TexUnified1DS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified1DS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified1DU32S32)
- MAKE_CASE(NVPTXISD::TexUnified1DU32Float)
- MAKE_CASE(NVPTXISD::TexUnified1DU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified1DU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayFloatS32)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayS32S32)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayS32Float)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayU32S32)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayU32Float)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified1DArrayU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified2DFloatS32)
- MAKE_CASE(NVPTXISD::TexUnified2DFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnified2DFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified2DFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified2DS32S32)
- MAKE_CASE(NVPTXISD::TexUnified2DS32Float)
- MAKE_CASE(NVPTXISD::TexUnified2DS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified2DS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified2DU32S32)
- MAKE_CASE(NVPTXISD::TexUnified2DU32Float)
- MAKE_CASE(NVPTXISD::TexUnified2DU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified2DU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayFloatS32)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayS32S32)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayS32Float)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayU32S32)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayU32Float)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified2DArrayU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified3DFloatS32)
- MAKE_CASE(NVPTXISD::TexUnified3DFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnified3DFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified3DFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified3DS32S32)
- MAKE_CASE(NVPTXISD::TexUnified3DS32Float)
- MAKE_CASE(NVPTXISD::TexUnified3DS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified3DS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnified3DU32S32)
- MAKE_CASE(NVPTXISD::TexUnified3DU32Float)
- MAKE_CASE(NVPTXISD::TexUnified3DU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnified3DU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeS32Float)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeU32Float)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayFloatFloat)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayS32Float)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayS32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayU32Float)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayU32FloatLevel)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeU32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayS32FloatGrad)
- MAKE_CASE(NVPTXISD::TexUnifiedCubeArrayU32FloatGrad)
- MAKE_CASE(NVPTXISD::Tld4UnifiedR2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4UnifiedG2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4UnifiedB2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4UnifiedA2DFloatFloat)
- MAKE_CASE(NVPTXISD::Tld4UnifiedR2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedG2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedB2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedA2DS64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedR2DU64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedG2DU64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedB2DU64Float)
- MAKE_CASE(NVPTXISD::Tld4UnifiedA2DU64Float)
-
- MAKE_CASE(NVPTXISD::Suld1DI8Clamp)
- MAKE_CASE(NVPTXISD::Suld1DI16Clamp)
- MAKE_CASE(NVPTXISD::Suld1DI32Clamp)
- MAKE_CASE(NVPTXISD::Suld1DI64Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV2I8Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV2I16Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV2I32Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV2I64Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV4I8Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV4I16Clamp)
- MAKE_CASE(NVPTXISD::Suld1DV4I32Clamp)
-
- MAKE_CASE(NVPTXISD::Suld1DArrayI8Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayI16Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayI32Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayI64Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I8Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I16Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I32Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I64Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I8Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I16Clamp)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I32Clamp)
-
- MAKE_CASE(NVPTXISD::Suld2DI8Clamp)
- MAKE_CASE(NVPTXISD::Suld2DI16Clamp)
- MAKE_CASE(NVPTXISD::Suld2DI32Clamp)
- MAKE_CASE(NVPTXISD::Suld2DI64Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV2I8Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV2I16Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV2I32Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV2I64Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV4I8Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV4I16Clamp)
- MAKE_CASE(NVPTXISD::Suld2DV4I32Clamp)
-
- MAKE_CASE(NVPTXISD::Suld2DArrayI8Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayI16Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayI32Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayI64Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I8Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I16Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I32Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I64Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I8Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I16Clamp)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I32Clamp)
-
- MAKE_CASE(NVPTXISD::Suld3DI8Clamp)
- MAKE_CASE(NVPTXISD::Suld3DI16Clamp)
- MAKE_CASE(NVPTXISD::Suld3DI32Clamp)
- MAKE_CASE(NVPTXISD::Suld3DI64Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV2I8Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV2I16Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV2I32Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV2I64Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV4I8Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV4I16Clamp)
- MAKE_CASE(NVPTXISD::Suld3DV4I32Clamp)
-
- MAKE_CASE(NVPTXISD::Suld1DI8Trap)
- MAKE_CASE(NVPTXISD::Suld1DI16Trap)
- MAKE_CASE(NVPTXISD::Suld1DI32Trap)
- MAKE_CASE(NVPTXISD::Suld1DI64Trap)
- MAKE_CASE(NVPTXISD::Suld1DV2I8Trap)
- MAKE_CASE(NVPTXISD::Suld1DV2I16Trap)
- MAKE_CASE(NVPTXISD::Suld1DV2I32Trap)
- MAKE_CASE(NVPTXISD::Suld1DV2I64Trap)
- MAKE_CASE(NVPTXISD::Suld1DV4I8Trap)
- MAKE_CASE(NVPTXISD::Suld1DV4I16Trap)
- MAKE_CASE(NVPTXISD::Suld1DV4I32Trap)
-
- MAKE_CASE(NVPTXISD::Suld1DArrayI8Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayI16Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayI32Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayI64Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I8Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I16Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I32Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I64Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I8Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I16Trap)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I32Trap)
-
- MAKE_CASE(NVPTXISD::Suld2DI8Trap)
- MAKE_CASE(NVPTXISD::Suld2DI16Trap)
- MAKE_CASE(NVPTXISD::Suld2DI32Trap)
- MAKE_CASE(NVPTXISD::Suld2DI64Trap)
- MAKE_CASE(NVPTXISD::Suld2DV2I8Trap)
- MAKE_CASE(NVPTXISD::Suld2DV2I16Trap)
- MAKE_CASE(NVPTXISD::Suld2DV2I32Trap)
- MAKE_CASE(NVPTXISD::Suld2DV2I64Trap)
- MAKE_CASE(NVPTXISD::Suld2DV4I8Trap)
- MAKE_CASE(NVPTXISD::Suld2DV4I16Trap)
- MAKE_CASE(NVPTXISD::Suld2DV4I32Trap)
-
- MAKE_CASE(NVPTXISD::Suld2DArrayI8Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayI16Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayI32Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayI64Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I8Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I16Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I32Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I64Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I8Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I16Trap)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I32Trap)
-
- MAKE_CASE(NVPTXISD::Suld3DI8Trap)
- MAKE_CASE(NVPTXISD::Suld3DI16Trap)
- MAKE_CASE(NVPTXISD::Suld3DI32Trap)
- MAKE_CASE(NVPTXISD::Suld3DI64Trap)
- MAKE_CASE(NVPTXISD::Suld3DV2I8Trap)
- MAKE_CASE(NVPTXISD::Suld3DV2I16Trap)
- MAKE_CASE(NVPTXISD::Suld3DV2I32Trap)
- MAKE_CASE(NVPTXISD::Suld3DV2I64Trap)
- MAKE_CASE(NVPTXISD::Suld3DV4I8Trap)
- MAKE_CASE(NVPTXISD::Suld3DV4I16Trap)
- MAKE_CASE(NVPTXISD::Suld3DV4I32Trap)
-
- MAKE_CASE(NVPTXISD::Suld1DI8Zero)
- MAKE_CASE(NVPTXISD::Suld1DI16Zero)
- MAKE_CASE(NVPTXISD::Suld1DI32Zero)
- MAKE_CASE(NVPTXISD::Suld1DI64Zero)
- MAKE_CASE(NVPTXISD::Suld1DV2I8Zero)
- MAKE_CASE(NVPTXISD::Suld1DV2I16Zero)
- MAKE_CASE(NVPTXISD::Suld1DV2I32Zero)
- MAKE_CASE(NVPTXISD::Suld1DV2I64Zero)
- MAKE_CASE(NVPTXISD::Suld1DV4I8Zero)
- MAKE_CASE(NVPTXISD::Suld1DV4I16Zero)
- MAKE_CASE(NVPTXISD::Suld1DV4I32Zero)
-
- MAKE_CASE(NVPTXISD::Suld1DArrayI8Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayI16Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayI32Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayI64Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I8Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I16Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I32Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV2I64Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I8Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I16Zero)
- MAKE_CASE(NVPTXISD::Suld1DArrayV4I32Zero)
-
- MAKE_CASE(NVPTXISD::Suld2DI8Zero)
- MAKE_CASE(NVPTXISD::Suld2DI16Zero)
- MAKE_CASE(NVPTXISD::Suld2DI32Zero)
- MAKE_CASE(NVPTXISD::Suld2DI64Zero)
- MAKE_CASE(NVPTXISD::Suld2DV2I8Zero)
- MAKE_CASE(NVPTXISD::Suld2DV2I16Zero)
- MAKE_CASE(NVPTXISD::Suld2DV2I32Zero)
- MAKE_CASE(NVPTXISD::Suld2DV2I64Zero)
- MAKE_CASE(NVPTXISD::Suld2DV4I8Zero)
- MAKE_CASE(NVPTXISD::Suld2DV4I16Zero)
- MAKE_CASE(NVPTXISD::Suld2DV4I32Zero)
-
- MAKE_CASE(NVPTXISD::Suld2DArrayI8Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayI16Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayI32Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayI64Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I8Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I16Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I32Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV2I64Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I8Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I16Zero)
- MAKE_CASE(NVPTXISD::Suld2DArrayV4I32Zero)
-
- MAKE_CASE(NVPTXISD::Suld3DI8Zero)
- MAKE_CASE(NVPTXISD::Suld3DI16Zero)
- MAKE_CASE(NVPTXISD::Suld3DI32Zero)
- MAKE_CASE(NVPTXISD::Suld3DI64Zero)
- MAKE_CASE(NVPTXISD::Suld3DV2I8Zero)
- MAKE_CASE(NVPTXISD::Suld3DV2I16Zero)
- MAKE_CASE(NVPTXISD::Suld3DV2I32Zero)
- MAKE_CASE(NVPTXISD::Suld3DV2I64Zero)
- MAKE_CASE(NVPTXISD::Suld3DV4I8Zero)
- MAKE_CASE(NVPTXISD::Suld3DV4I16Zero)
- MAKE_CASE(NVPTXISD::Suld3DV4I32Zero)
}
return nullptr;
@@ -3713,715 +3358,6 @@ void NVPTXTargetLowering::LowerAsmOperandForConstraint(
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
}
-static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
- switch (Intrinsic) {
- default:
- return 0;
-
- case Intrinsic::nvvm_tex_1d_v4f32_s32:
- return NVPTXISD::Tex1DFloatS32;
- case Intrinsic::nvvm_tex_1d_v4f32_f32:
- return NVPTXISD::Tex1DFloatFloat;
- case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
- return NVPTXISD::Tex1DFloatFloatLevel;
- case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
- return NVPTXISD::Tex1DFloatFloatGrad;
- case Intrinsic::nvvm_tex_1d_v4s32_s32:
- return NVPTXISD::Tex1DS32S32;
- case Intrinsic::nvvm_tex_1d_v4s32_f32:
- return NVPTXISD::Tex1DS32Float;
- case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
- return NVPTXISD::Tex1DS32FloatLevel;
- case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
- return NVPTXISD::Tex1DS32FloatGrad;
- case Intrinsic::nvvm_tex_1d_v4u32_s32:
- return NVPTXISD::Tex1DU32S32;
- case Intrinsic::nvvm_tex_1d_v4u32_f32:
- return NVPTXISD::Tex1DU32Float;
- case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
- return NVPTXISD::Tex1DU32FloatLevel;
- case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
- return NVPTXISD::Tex1DU32FloatGrad;
-
- case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
- return NVPTXISD::Tex1DArrayFloatS32;
- case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
- return NVPTXISD::Tex1DArrayFloatFloat;
- case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
- return NVPTXISD::Tex1DArrayFloatFloatLevel;
- case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
- return NVPTXISD::Tex1DArrayFloatFloatGrad;
- case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
- return NVPTXISD::Tex1DArrayS32S32;
- case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
- return NVPTXISD::Tex1DArrayS32Float;
- case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
- return NVPTXISD::Tex1DArrayS32FloatLevel;
- case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
- return NVPTXISD::Tex1DArrayS32FloatGrad;
- case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
- return NVPTXISD::Tex1DArrayU32S32;
- case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
- return NVPTXISD::Tex1DArrayU32Float;
- case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
- return NVPTXISD::Tex1DArrayU32FloatLevel;
- case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
- return NVPTXISD::Tex1DArrayU32FloatGrad;
-
- case Intrinsic::nvvm_tex_2d_v4f32_s32:
- return NVPTXISD::Tex2DFloatS32;
- case Intrinsic::nvvm_tex_2d_v4f32_f32:
- return NVPTXISD::Tex2DFloatFloat;
- case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
- return NVPTXISD::Tex2DFloatFloatLevel;
- case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
- return NVPTXISD::Tex2DFloatFloatGrad;
- case Intrinsic::nvvm_tex_2d_v4s32_s32:
- return NVPTXISD::Tex2DS32S32;
- case Intrinsic::nvvm_tex_2d_v4s32_f32:
- return NVPTXISD::Tex2DS32Float;
- case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
- return NVPTXISD::Tex2DS32FloatLevel;
- case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
- return NVPTXISD::Tex2DS32FloatGrad;
- case Intrinsic::nvvm_tex_2d_v4u32_s32:
- return NVPTXISD::Tex2DU32S32;
- case Intrinsic::nvvm_tex_2d_v4u32_f32:
- return NVPTXISD::Tex2DU32Float;
- case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
- return NVPTXISD::Tex2DU32FloatLevel;
- case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
- return NVPTXISD::Tex2DU32FloatGrad;
-
- case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
- return NVPTXISD::Tex2DArrayFloatS32;
- case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
- return NVPTXISD::Tex2DArrayFloatFloat;
- case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
- return NVPTXISD::Tex2DArrayFloatFloatLevel;
- case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
- return NVPTXISD::Tex2DArrayFloatFloatGrad;
- case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
- return NVPTXISD::Tex2DArrayS32S32;
- case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
- return NVPTXISD::Tex2DArrayS32Float;
- case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
- return NVPTXISD::Tex2DArrayS32FloatLevel;
- case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
- return NVPTXISD::Tex2DArrayS32FloatGrad;
- case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
- return NVPTXISD::Tex2DArrayU32S32;
- case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
- return NVPTXISD::Tex2DArrayU32Float;
- case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
- return NVPTXISD::Tex2DArrayU32FloatLevel;
- case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
- return NVPTXISD::Tex2DArrayU32FloatGrad;
-
- case Intrinsic::nvvm_tex_3d_v4f32_s32:
- return NVPTXISD::Tex3DFloatS32;
- case Intrinsic::nvvm_tex_3d_v4f32_f32:
- return NVPTXISD::Tex3DFloatFloat;
- case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
- return NVPTXISD::Tex3DFloatFloatLevel;
- case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
- return NVPTXISD::Tex3DFloatFloatGrad;
- case Intrinsic::nvvm_tex_3d_v4s32_s32:
- return NVPTXISD::Tex3DS32S32;
- case Intrinsic::nvvm_tex_3d_v4s32_f32:
- return NVPTXISD::Tex3DS32Float;
- case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
- return NVPTXISD::Tex3DS32FloatLevel;
- case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
- return NVPTXISD::Tex3DS32FloatGrad;
- case Intrinsic::nvvm_tex_3d_v4u32_s32:
- return NVPTXISD::Tex3DU32S32;
- case Intrinsic::nvvm_tex_3d_v4u32_f32:
- return NVPTXISD::Tex3DU32Float;
- case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
- return NVPTXISD::Tex3DU32FloatLevel;
- case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
- return NVPTXISD::Tex3DU32FloatGrad;
-
- case Intrinsic::nvvm_tex_cube_v4f32_f32:
- return NVPTXISD::TexCubeFloatFloat;
- case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
- return NVPTXISD::TexCubeFloatFloatLevel;
- case Intrinsic::nvvm_tex_cube_v4s32_f32:
- return NVPTXISD::TexCubeS32Float;
- case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
- return NVPTXISD::TexCubeS32FloatLevel;
- case Intrinsic::nvvm_tex_cube_v4u32_f32:
- return NVPTXISD::TexCubeU32Float;
- case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
- return NVPTXISD::TexCubeU32FloatLevel;
-
- case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
- return NVPTXISD::TexCubeArrayFloatFloat;
- case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
- return NVPTXISD::TexCubeArrayFloatFloatLevel;
- case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
- return NVPTXISD::TexCubeArrayS32Float;
- case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
- return NVPTXISD::TexCubeArrayS32FloatLevel;
- case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
- return NVPTXISD::TexCubeArrayU32Float;
- case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
- return NVPTXISD::TexCubeArrayU32FloatLevel;
-
- case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
- return NVPTXISD::Tld4R2DFloatFloat;
- case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
- return NVPTXISD::Tld4G2DFloatFloat;
- case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
- return NVPTXISD::Tld4B2DFloatFloat;
- case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
- return NVPTXISD::Tld4A2DFloatFloat;
- case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
- return NVPTXISD::Tld4R2DS64Float;
- case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
- return NVPTXISD::Tld4G2DS64Float;
- case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
- return NVPTXISD::Tld4B2DS64Float;
- case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
- return NVPTXISD::Tld4A2DS64Float;
- case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
- return NVPTXISD::Tld4R2DU64Float;
- case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
- return NVPTXISD::Tld4G2DU64Float;
- case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
- return NVPTXISD::Tld4B2DU64Float;
- case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
- return NVPTXISD::Tld4A2DU64Float;
-
- case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
- return NVPTXISD::TexUnified1DFloatS32;
- case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
- return NVPTXISD::TexUnified1DFloatFloat;
- case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
- return NVPTXISD::TexUnified1DFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
- return NVPTXISD::TexUnified1DFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
- return NVPTXISD::TexUnified1DS32S32;
- case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
- return NVPTXISD::TexUnified1DS32Float;
- case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
- return NVPTXISD::TexUnified1DS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
- return NVPTXISD::TexUnified1DS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
- return NVPTXISD::TexUnified1DU32S32;
- case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
- return NVPTXISD::TexUnified1DU32Float;
- case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
- return NVPTXISD::TexUnified1DU32FloatLevel;
- case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
- return NVPTXISD::TexUnified1DU32FloatGrad;
-
- case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
- return NVPTXISD::TexUnified1DArrayFloatS32;
- case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
- return NVPTXISD::TexUnified1DArrayFloatFloat;
- case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
- return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
- return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
- return NVPTXISD::TexUnified1DArrayS32S32;
- case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
- return NVPTXISD::TexUnified1DArrayS32Float;
- case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
- return NVPTXISD::TexUnified1DArrayS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
- return NVPTXISD::TexUnified1DArrayS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
- return NVPTXISD::TexUnified1DArrayU32S32;
- case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
- return NVPTXISD::TexUnified1DArrayU32Float;
- case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
- return NVPTXISD::TexUnified1DArrayU32FloatLevel;
- case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
- return NVPTXISD::TexUnified1DArrayU32FloatGrad;
-
- case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
- return NVPTXISD::TexUnified2DFloatS32;
- case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
- return NVPTXISD::TexUnified2DFloatFloat;
- case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
- return NVPTXISD::TexUnified2DFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
- return NVPTXISD::TexUnified2DFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
- return NVPTXISD::TexUnified2DS32S32;
- case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
- return NVPTXISD::TexUnified2DS32Float;
- case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
- return NVPTXISD::TexUnified2DS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
- return NVPTXISD::TexUnified2DS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
- return NVPTXISD::TexUnified2DU32S32;
- case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
- return NVPTXISD::TexUnified2DU32Float;
- case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
- return NVPTXISD::TexUnified2DU32FloatLevel;
- case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
- return NVPTXISD::TexUnified2DU32FloatGrad;
-
- case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
- return NVPTXISD::TexUnified2DArrayFloatS32;
- case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
- return NVPTXISD::TexUnified2DArrayFloatFloat;
- case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
- return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
- return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
- return NVPTXISD::TexUnified2DArrayS32S32;
- case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
- return NVPTXISD::TexUnified2DArrayS32Float;
- case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
- return NVPTXISD::TexUnified2DArrayS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
- return NVPTXISD::TexUnified2DArrayS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
- return NVPTXISD::TexUnified2DArrayU32S32;
- case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
- return NVPTXISD::TexUnified2DArrayU32Float;
- case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
- return NVPTXISD::TexUnified2DArrayU32FloatLevel;
- case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
- return NVPTXISD::TexUnified2DArrayU32FloatGrad;
-
- case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
- return NVPTXISD::TexUnified3DFloatS32;
- case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
- return NVPTXISD::TexUnified3DFloatFloat;
- case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
- return NVPTXISD::TexUnified3DFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
- return NVPTXISD::TexUnified3DFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
- return NVPTXISD::TexUnified3DS32S32;
- case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
- return NVPTXISD::TexUnified3DS32Float;
- case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
- return NVPTXISD::TexUnified3DS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
- return NVPTXISD::TexUnified3DS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
- return NVPTXISD::TexUnified3DU32S32;
- case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
- return NVPTXISD::TexUnified3DU32Float;
- case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
- return NVPTXISD::TexUnified3DU32FloatLevel;
- case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
- return NVPTXISD::TexUnified3DU32FloatGrad;
-
- case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
- return NVPTXISD::TexUnifiedCubeFloatFloat;
- case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
- return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
- return NVPTXISD::TexUnifiedCubeS32Float;
- case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
- return NVPTXISD::TexUnifiedCubeS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
- return NVPTXISD::TexUnifiedCubeU32Float;
- case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
- return NVPTXISD::TexUnifiedCubeU32FloatLevel;
-
- case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
- return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
- case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
- return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
- case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
- return NVPTXISD::TexUnifiedCubeArrayS32Float;
- case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
- return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
- case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
- return NVPTXISD::TexUnifiedCubeArrayU32Float;
- case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
- return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
-
- case Intrinsic::nvvm_tex_unified_cube_grad_v4f32_f32:
- return NVPTXISD::TexUnifiedCubeFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_cube_grad_v4s32_f32:
- return NVPTXISD::TexUnifiedCubeS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_cube_grad_v4u32_f32:
- return NVPTXISD::TexUnifiedCubeU32FloatGrad;
- case Intrinsic::nvvm_tex_unified_cube_array_grad_v4f32_f32:
- return NVPTXISD::TexUnifiedCubeArrayFloatFloatGrad;
- case Intrinsic::nvvm_tex_unified_cube_array_grad_v4s32_f32:
- return NVPTXISD::TexUnifiedCubeArrayS32FloatGrad;
- case Intrinsic::nvvm_tex_unified_cube_array_grad_v4u32_f32:
- return NVPTXISD::TexUnifiedCubeArrayU32FloatGrad;
-
- case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
- return NVPTXISD::Tld4UnifiedR2DFloatFloat;
- case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
- return NVPTXISD::Tld4UnifiedG2DFloatFloat;
- case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
- return NVPTXISD::Tld4UnifiedB2DFloatFloat;
- case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
- return NVPTXISD::Tld4UnifiedA2DFloatFloat;
- case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
- return NVPTXISD::Tld4UnifiedR2DS64Float;
- case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
- return NVPTXISD::Tld4UnifiedG2DS64Float;
- case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
- return NVPTXISD::Tld4UnifiedB2DS64Float;
- case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
- return NVPTXISD::Tld4UnifiedA2DS64Float;
- case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
- return NVPTXISD::Tld4UnifiedR2DU64Float;
- case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
- return NVPTXISD::Tld4UnifiedG2DU64Float;
- case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
- return NVPTXISD::Tld4UnifiedB2DU64Float;
- case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
- return NVPTXISD::Tld4UnifiedA2DU64Float;
- }
-}
-
-static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
- switch (Intrinsic) {
- default:
- return 0;
- case Intrinsic::nvvm_suld_1d_i8_clamp:
- return NVPTXISD::Suld1DI8Clamp;
- case Intrinsic::nvvm_suld_1d_i16_clamp:
- return NVPTXISD::Suld1DI16Clamp;
- case Intrinsic::nvvm_suld_1d_i32_clamp:
- return NVPTXISD::Suld1DI32Clamp;
- case Intrinsic::nvvm_suld_1d_i64_clamp:
- return NVPTXISD::Suld1DI64Clamp;
- case Intrinsic::nvvm_suld_1d_v2i8_clamp:
- return NVPTXISD::Suld1DV2I8Clamp;
- case Intrinsic::nvvm_suld_1d_v2i16_clamp:
- return NVPTXISD::Suld1DV2I16Clamp;
- case Intrinsic::nvvm_suld_1d_v2i32_clamp:
- return NVPTXISD::Suld1DV2I32Clamp;
- case Intrinsic::nvvm_suld_1d_v2i64_clamp:
- return NVPTXISD::Suld1DV2I64Clamp;
- case Intrinsic::nvvm_suld_1d_v4i8_clamp:
- return NVPTXISD::Suld1DV4I8Clamp;
- case Intrinsic::nvvm_suld_1d_v4i16_clamp:
- return NVPTXISD::Suld1DV4I16Clamp;
- case Intrinsic::nvvm_suld_1d_v4i32_clamp:
- return NVPTXISD::Suld1DV4I32Clamp;
- case Intrinsic::nvvm_suld_1d_array_i8_clamp:
- return NVPTXISD::Suld1DArrayI8Clamp;
- case Intrinsic::nvvm_suld_1d_array_i16_clamp:
- return NVPTXISD::Suld1DArrayI16Clamp;
- case Intrinsic::nvvm_suld_1d_array_i32_clamp:
- return NVPTXISD::Suld1DArrayI32Clamp;
- case Intrinsic::nvvm_suld_1d_array_i64_clamp:
- return NVPTXISD::Suld1DArrayI64Clamp;
- case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
- return NVPTXISD::Suld1DArrayV2I8Clamp;
- case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
- return NVPTXISD::Suld1DArrayV2I16Clamp;
- case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
- return NVPTXISD::Suld1DArrayV2I32Clamp;
- case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
- return NVPTXISD::Suld1DArrayV2I64Clamp;
- case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
- return NVPTXISD::Suld1DArrayV4I8Clamp;
- case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
- return NVPTXISD::Suld1DArrayV4I16Clamp;
- case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
- return NVPTXISD::Suld1DArrayV4I32Clamp;
- case Intrinsic::nvvm_suld_2d_i8_clamp:
- return NVPTXISD::Suld2DI8Clamp;
- case Intrinsic::nvvm_suld_2d_i16_clamp:
- return NVPTXISD::Suld2DI16Clamp;
- case Intrinsic::nvvm_suld_2d_i32_clamp:
- return NVPTXISD::Suld2DI32Clamp;
- case Intrinsic::nvvm_suld_2d_i64_clamp:
- return NVPTXISD::Suld2DI64Clamp;
- case Intrinsic::nvvm_suld_2d_v2i8_clamp:
- return NVPTXISD::Suld2DV2I8Clamp;
- case Intrinsic::nvvm_suld_2d_v2i16_clamp:
- return NVPTXISD::Suld2DV2I16Clamp;
- case Intrinsic::nvvm_suld_2d_v2i32_clamp:
- return NVPTXISD::Suld2DV2I32Clamp;
- case Intrinsic::nvvm_suld_2d_v2i64_clamp:
- return NVPTXISD::Suld2DV2I64Clamp;
- case Intrinsic::nvvm_suld_2d_v4i8_clamp:
- return NVPTXISD::Suld2DV4I8Clamp;
- case Intrinsic::nvvm_suld_2d_v4i16_clamp:
- return NVPTXISD::Suld2DV4I16Clamp;
- case Intrinsic::nvvm_suld_2d_v4i32_clamp:
- return NVPTXISD::Suld2DV4I32Clamp;
- case Intrinsic::nvvm_suld_2d_array_i8_clamp:
- return NVPTXISD::Suld2DArrayI8Clamp;
- case Intrinsic::nvvm_suld_2d_array_i16_clamp:
- return NVPTXISD::Suld2DArrayI16Clamp;
- case Intrinsic::nvvm_suld_2d_array_i32_clamp:
- return NVPTXISD::Suld2DArrayI32Clamp;
- case Intrinsic::nvvm_suld_2d_array_i64_clamp:
- return NVPTXISD::Suld2DArrayI64Clamp;
- case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
- return NVPTXISD::Suld2DArrayV2I8Clamp;
- case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
- return NVPTXISD::Suld2DArrayV2I16Clamp;
- case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
- return NVPTXISD::Suld2DArrayV2I32Clamp;
- case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
- return NVPTXISD::Suld2DArrayV2I64Clamp;
- case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
- return NVPTXISD::Suld2DArrayV4I8Clamp;
- case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
- return NVPTXISD::Suld2DArrayV4I16Clamp;
- case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
- return NVPTXISD::Suld2DArrayV4I32Clamp;
- case Intrinsic::nvvm_suld_3d_i8_clamp:
- return NVPTXISD::Suld3DI8Clamp;
- case Intrinsic::nvvm_suld_3d_i16_clamp:
- return NVPTXISD::Suld3DI16Clamp;
- case Intrinsic::nvvm_suld_3d_i32_clamp:
- return NVPTXISD::Suld3DI32Clamp;
- case Intrinsic::nvvm_suld_3d_i64_clamp:
- return NVPTXISD::Suld3DI64Clamp;
- case Intrinsic::nvvm_suld_3d_v2i8_clamp:
- return NVPTXISD::Suld3DV2I8Clamp;
- case Intrinsic::nvvm_suld_3d_v2i16_clamp:
- return NVPTXISD::Suld3DV2I16Clamp;
- case Intrinsic::nvvm_suld_3d_v2i32_clamp:
- return NVPTXISD::Suld3DV2I32Clamp;
- case Intrinsic::nvvm_suld_3d_v2i64_clamp:
- return NVPTXISD::Suld3DV2I64Clamp;
- case Intrinsic::nvvm_suld_3d_v4i8_clamp:
- return NVPTXISD::Suld3DV4I8Clamp;
- case Intrinsic::nvvm_suld_3d_v4i16_clamp:
- return NVPTXISD::Suld3DV4I16Clamp;
- case Intrinsic::nvvm_suld_3d_v4i32_clamp:
- return NVPTXISD::Suld3DV4I32Clamp;
- case Intrinsic::nvvm_suld_1d_i8_trap:
- return NVPTXISD::Suld1DI8Trap;
- case Intrinsic::nvvm_suld_1d_i16_trap:
- return NVPTXISD::Suld1DI16Trap;
- case Intrinsic::nvvm_suld_1d_i32_trap:
- return NVPTXISD::Suld1DI32Trap;
- case Intrinsic::nvvm_suld_1d_i64_trap:
- return NVPTXISD::Suld1DI64Trap;
- case Intrinsic::nvvm_suld_1d_v2i8_trap:
- return NVPTXISD::Suld1DV2I8Trap;
- case Intrinsic::nvvm_suld_1d_v2i16_trap:
- return NVPTXISD::Suld1DV2I16Trap;
- case Intrinsic::nvvm_suld_1d_v2i32_trap:
- return NVPTXISD::Suld1DV2I32Trap;
- case Intrinsic::nvvm_suld_1d_v2i64_trap:
- return NVPTXISD::Suld1DV2I64Trap;
- case Intrinsic::nvvm_suld_1d_v4i8_trap:
- return NVPTXISD::Suld1DV4I8Trap;
- case Intrinsic::nvvm_suld_1d_v4i16_trap:
- return NVPTXISD::Suld1DV4I16Trap;
- case Intrinsic::nvvm_suld_1d_v4i32_trap:
- return NVPTXISD::Suld1DV4I32Trap;
- case Intrinsic::nvvm_suld_1d_array_i8_trap:
- return NVPTXISD::Suld1DArrayI8Trap;
- case Intrinsic::nvvm_suld_1d_array_i16_trap:
- return NVPTXISD::Suld1DArrayI16Trap;
- case Intrinsic::nvvm_suld_1d_array_i32_trap:
- return NVPTXISD::Suld1DArrayI32Trap;
- case Intrinsic::nvvm_suld_1d_array_i64_trap:
- return NVPTXISD::Suld1DArrayI64Trap;
- case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
- return NVPTXISD::Suld1DArrayV2I8Trap;
- case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
- return NVPTXISD::Suld1DArrayV2I16Trap;
- case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
- return NVPTXISD::Suld1DArrayV2I32Trap;
- case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
- return NVPTXISD::Suld1DArrayV2I64Trap;
- case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
- return NVPTXISD::Suld1DArrayV4I8Trap;
- case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
- return NVPTXISD::Suld1DArrayV4I16Trap;
- case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
- return NVPTXISD::Suld1DArrayV4I32Trap;
- case Intrinsic::nvvm_suld_2d_i8_trap:
- return NVPTXISD::Suld2DI8Trap;
- case Intrinsic::nvvm_suld_2d_i16_trap:
- return NVPTXISD::Suld2DI16Trap;
- case Intrinsic::nvvm_suld_2d_i32_trap:
- return NVPTXISD::Suld2DI32Trap;
- case Intrinsic::nvvm_suld_2d_i64_trap:
- return NVPTXISD::Suld2DI64Trap;
- case Intrinsic::nvvm_suld_2d_v2i8_trap:
- return NVPTXISD::Suld2DV2I8Trap;
- case Intrinsic::nvvm_suld_2d_v2i16_trap:
- return NVPTXISD::Suld2DV2I16Trap;
- case Intrinsic::nvvm_suld_2d_v2i32_trap:
- return NVPTXISD::Suld2DV2I32Trap;
- case Intrinsic::nvvm_suld_2d_v2i64_trap:
- return NVPTXISD::Suld2DV2I64Trap;
- case Intrinsic::nvvm_suld_2d_v4i8_trap:
- return NVPTXISD::Suld2DV4I8Trap;
- case Intrinsic::nvvm_suld_2d_v4i16_trap:
- return NVPTXISD::Suld2DV4I16Trap;
- case Intrinsic::nvvm_suld_2d_v4i32_trap:
- return NVPTXISD::Suld2DV4I32Trap;
- case Intrinsic::nvvm_suld_2d_array_i8_trap:
- return NVPTXISD::Suld2DArrayI8Trap;
- case Intrinsic::nvvm_suld_2d_array_i16_trap:
- return NVPTXISD::Suld2DArrayI16Trap;
- case Intrinsic::nvvm_suld_2d_array_i32_trap:
- return NVPTXISD::Suld2DArrayI32Trap;
- case Intrinsic::nvvm_suld_2d_array_i64_trap:
- return NVPTXISD::Suld2DArrayI64Trap;
- case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
- return NVPTXISD::Suld2DArrayV2I8Trap;
- case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
- return NVPTXISD::Suld2DArrayV2I16Trap;
- case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
- return NVPTXISD::Suld2DArrayV2I32Trap;
- case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
- return NVPTXISD::Suld2DArrayV2I64Trap;
- case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
- return NVPTXISD::Suld2DArrayV4I8Trap;
- case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
- return NVPTXISD::Suld2DArrayV4I16Trap;
- case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
- return NVPTXISD::Suld2DArrayV4I32Trap;
- case Intrinsic::nvvm_suld_3d_i8_trap:
- return NVPTXISD::Suld3DI8Trap;
- case Intrinsic::nvvm_suld_3d_i16_trap:
- return NVPTXISD::Suld3DI16Trap;
- case Intrinsic::nvvm_suld_3d_i32_trap:
- return NVPTXISD::Suld3DI32Trap;
- case Intrinsic::nvvm_suld_3d_i64_trap:
- return NVPTXISD::Suld3DI64Trap;
- case Intrinsic::nvvm_suld_3d_v2i8_trap:
- return NVPTXISD::Suld3DV2I8Trap;
- case Intrinsic::nvvm_suld_3d_v2i16_trap:
- return NVPTXISD::Suld3DV2I16Trap;
- case Intrinsic::nvvm_suld_3d_v2i32_trap:
- return NVPTXISD::Suld3DV2I32Trap;
- case Intrinsic::nvvm_suld_3d_v2i64_trap:
- return NVPTXISD::Suld3DV2I64Trap;
- case Intrinsic::nvvm_suld_3d_v4i8_trap:
- return NVPTXISD::Suld3DV4I8Trap;
- case Intrinsic::nvvm_suld_3d_v4i16_trap:
- return NVPTXISD::Suld3DV4I16Trap;
- case Intrinsic::nvvm_suld_3d_v4i32_trap:
- return NVPTXISD::Suld3DV4I32Trap;
- case Intrinsic::nvvm_suld_1d_i8_zero:
- return NVPTXISD::Suld1DI8Zero;
- case Intrinsic::nvvm_suld_1d_i16_zero:
- return NVPTXISD::Suld1DI16Zero;
- case Intrinsic::nvvm_suld_1d_i32_zero:
- return NVPTXISD::Suld1DI32Zero;
- case Intrinsic::nvvm_suld_1d_i64_zero:
- return NVPTXISD::Suld1DI64Zero;
- case Intrinsic::nvvm_suld_1d_v2i8_zero:
- return NVPTXISD::Suld1DV2I8Zero;
- case Intrinsic::nvvm_suld_1d_v2i16_zero:
- return NVPTXISD::Suld1DV2I16Zero;
- case Intrinsic::nvvm_suld_1d_v2i32_zero:
- return NVPTXISD::Suld1DV2I32Zero;
- case Intrinsic::nvvm_suld_1d_v2i64_zero:
- return NVPTXISD::Suld1DV2I64Zero;
- case Intrinsic::nvvm_suld_1d_v4i8_zero:
- return NVPTXISD::Suld1DV4I8Zero;
- case Intrinsic::nvvm_suld_1d_v4i16_zero:
- return NVPTXISD::Suld1DV4I16Zero;
- case Intrinsic::nvvm_suld_1d_v4i32_zero:
- return NVPTXISD::Suld1DV4I32Zero;
- case Intrinsic::nvvm_suld_1d_array_i8_zero:
- return NVPTXISD::Suld1DArrayI8Zero;
- case Intrinsic::nvvm_suld_1d_array_i16_zero:
- return NVPTXISD::Suld1DArrayI16Zero;
- case Intrinsic::nvvm_suld_1d_array_i32_zero:
- return NVPTXISD::Suld1DArrayI32Zero;
- case Intrinsic::nvvm_suld_1d_array_i64_zero:
- return NVPTXISD::Suld1DArrayI64Zero;
- case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
- return NVPTXISD::Suld1DArrayV2I8Zero;
- case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
- return NVPTXISD::Suld1DArrayV2I16Zero;
- case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
- return NVPTXISD::Suld1DArrayV2I32Zero;
- case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
- return NVPTXISD::Suld1DArrayV2I64Zero;
- case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
- return NVPTXISD::Suld1DArrayV4I8Zero;
- case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
- return NVPTXISD::Suld1DArrayV4I16Zero;
- case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
- return NVPTXISD::Suld1DArrayV4I32Zero;
- case Intrinsic::nvvm_suld_2d_i8_zero:
- return NVPTXISD::Suld2DI8Zero;
- case Intrinsic::nvvm_suld_2d_i16_zero:
- return NVPTXISD::Suld2DI16Zero;
- case Intrinsic::nvvm_suld_2d_i32_zero:
- return NVPTXISD::Suld2DI32Zero;
- case Intrinsic::nvvm_suld_2d_i64_zero:
- return NVPTXISD::Suld2DI64Zero;
- case Intrinsic::nvvm_suld_2d_v2i8_zero:
- return NVPTXISD::Suld2DV2I8Zero;
- case Intrinsic::nvvm_suld_2d_v2i16_zero:
- return NVPTXISD::Suld2DV2I16Zero;
- case Intrinsic::nvvm_suld_2d_v2i32_zero:
- return NVPTXISD::Suld2DV2I32Zero;
- case Intrinsic::nvvm_suld_2d_v2i64_zero:
- return NVPTXISD::Suld2DV2I64Zero;
- case Intrinsic::nvvm_suld_2d_v4i8_zero:
- return NVPTXISD::Suld2DV4I8Zero;
- case Intrinsic::nvvm_suld_2d_v4i16_zero:
- return NVPTXISD::Suld2DV4I16Zero;
- case Intrinsic::nvvm_suld_2d_v4i32_zero:
- return NVPTXISD::Suld2DV4I32Zero;
- case Intrinsic::nvvm_suld_2d_array_i8_zero:
- return NVPTXISD::Suld2DArrayI8Zero;
- case Intrinsic::nvvm_suld_2d_array_i16_zero:
- return NVPTXISD::Suld2DArrayI16Zero;
- case Intrinsic::nvvm_suld_2d_array_i32_zero:
- return NVPTXISD::Suld2DArrayI32Zero;
- case Intrinsic::nvvm_suld_2d_array_i64_zero:
- return NVPTXISD::Suld2DArrayI64Zero;
- case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
- return NVPTXISD::Suld2DArrayV2I8Zero;
- case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
- return NVPTXISD::Suld2DArrayV2I16Zero;
- case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
- return NVPTXISD::Suld2DArrayV2I32Zero;
- case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
- return NVPTXISD::Suld2DArrayV2I64Zero;
- case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
- return NVPTXISD::Suld2DArrayV4I8Zero;
- case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
- return NVPTXISD::Suld2DArrayV4I16Zero;
- case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
- return NVPTXISD::Suld2DArrayV4I32Zero;
- case Intrinsic::nvvm_suld_3d_i8_zero:
- return NVPTXISD::Suld3DI8Zero;
- case Intrinsic::nvvm_suld_3d_i16_zero:
- return NVPTXISD::Suld3DI16Zero;
- case Intrinsic::nvvm_suld_3d_i32_zero:
- return NVPTXISD::Suld3DI32Zero;
- case Intrinsic::nvvm_suld_3d_i64_zero:
- return NVPTXISD::Suld3DI64Zero;
- case Intrinsic::nvvm_suld_3d_v2i8_zero:
- return NVPTXISD::Suld3DV2I8Zero;
- case Intrinsic::nvvm_suld_3d_v2i16_zero:
- return NVPTXISD::Suld3DV2I16Zero;
- case Intrinsic::nvvm_suld_3d_v2i32_zero:
- return NVPTXISD::Suld3DV2I32Zero;
- case Intrinsic::nvvm_suld_3d_v2i64_zero:
- return NVPTXISD::Suld3DV2I64Zero;
- case Intrinsic::nvvm_suld_3d_v4i8_zero:
- return NVPTXISD::Suld3DV4I8Zero;
- case Intrinsic::nvvm_suld_3d_v4i16_zero:
- return NVPTXISD::Suld3DV4I16Zero;
- case Intrinsic::nvvm_suld_3d_v4i32_zero:
- return NVPTXISD::Suld3DV4I32Zero;
- }
-}
-
// llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
// TgtMemIntrinsic
// because we need the information that is only available in the "Value" type
@@ -4928,7 +3864,7 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(
case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
- Info.opc = getOpcForTextureInstr(Intrinsic);
+ Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::v4f32;
Info.ptrVal = nullptr;
Info.offset = 0;
@@ -5052,7 +3988,7 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(
case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
- Info.opc = getOpcForTextureInstr(Intrinsic);
+ Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::v4i32;
Info.ptrVal = nullptr;
Info.offset = 0;
@@ -5105,7 +4041,7 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(
case Intrinsic::nvvm_suld_3d_i8_zero:
case Intrinsic::nvvm_suld_3d_v2i8_zero:
case Intrinsic::nvvm_suld_3d_v4i8_zero:
- Info.opc = getOpcForSurfaceInstr(Intrinsic);
+ Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::i8;
Info.ptrVal = nullptr;
Info.offset = 0;
@@ -5158,7 +4094,7 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(
case Intrinsic::nvvm_suld_3d_i16_zero:
case Intrinsic::nvvm_suld_3d_v2i16_zero:
case Intrinsic::nvvm_suld_3d_v4i16_zero:
- Info.opc = getOpcForSurfaceInstr(Intrinsic);
+ Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::i16;
Info.ptrVal = nullptr;
Info.offset = 0;
@@ -5211,7 +4147,7 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(
case Intrinsic::nvvm_suld_3d_i32_zero:
case Intrinsic::nvvm_suld_3d_v2i32_zero:
case Intrinsic::nvvm_suld_3d_v4i32_zero:
- Info.opc = getOpcForSurfaceInstr(Intrinsic);
+ Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::i32;
Info.ptrVal = nullptr;
Info.offset = 0;
@@ -5249,7 +4185,7 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(
case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
case Intrinsic::nvvm_suld_3d_i64_zero:
case Intrinsic::nvvm_suld_3d_v2i64_zero:
- Info.opc = getOpcForSurfaceInstr(Intrinsic);
+ Info.opc = ISD::INTRINSIC_W_CHAIN;
Info.memVT = MVT::i64;
Info.ptrVal = nullptr;
Info.offset = 0;
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index c8b589ae39413e..0244a0c5bec9d5 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -87,363 +87,6 @@ enum NodeType : unsigned {
StoreRetval,
StoreRetvalV2,
StoreRetvalV4,
-
- // Texture intrinsics
- Tex1DFloatS32,
- Tex1DFloatFloat,
- Tex1DFloatFloatLevel,
- Tex1DFloatFloatGrad,
- Tex1DS32S32,
- Tex1DS32Float,
- Tex1DS32FloatLevel,
- Tex1DS32FloatGrad,
- Tex1DU32S32,
- Tex1DU32Float,
- Tex1DU32FloatLevel,
- Tex1DU32FloatGrad,
- Tex1DArrayFloatS32,
- Tex1DArrayFloatFloat,
- Tex1DArrayFloatFloatLevel,
- Tex1DArrayFloatFloatGrad,
- Tex1DArrayS32S32,
- Tex1DArrayS32Float,
- Tex1DArrayS32FloatLevel,
- Tex1DArrayS32FloatGrad,
- Tex1DArrayU32S32,
- Tex1DArrayU32Float,
- Tex1DArrayU32FloatLevel,
- Tex1DArrayU32FloatGrad,
- Tex2DFloatS32,
- Tex2DFloatFloat,
- Tex2DFloatFloatLevel,
- Tex2DFloatFloatGrad,
- Tex2DS32S32,
- Tex2DS32Float,
- Tex2DS32FloatLevel,
- Tex2DS32FloatGrad,
- Tex2DU32S32,
- Tex2DU32Float,
- Tex2DU32FloatLevel,
- Tex2DU32FloatGrad,
- Tex2DArrayFloatS32,
- Tex2DArrayFloatFloat,
- Tex2DArrayFloatFloatLevel,
- Tex2DArrayFloatFloatGrad,
- Tex2DArrayS32S32,
- Tex2DArrayS32Float,
- Tex2DArrayS32FloatLevel,
- Tex2DArrayS32FloatGrad,
- Tex2DArrayU32S32,
- Tex2DArrayU32Float,
- Tex2DArrayU32FloatLevel,
- Tex2DArrayU32FloatGrad,
- Tex3DFloatS32,
- Tex3DFloatFloat,
- Tex3DFloatFloatLevel,
- Tex3DFloatFloatGrad,
- Tex3DS32S32,
- Tex3DS32Float,
- Tex3DS32FloatLevel,
- Tex3DS32FloatGrad,
- Tex3DU32S32,
- Tex3DU32Float,
- Tex3DU32FloatLevel,
- Tex3DU32FloatGrad,
- TexCubeFloatFloat,
- TexCubeFloatFloatLevel,
- TexCubeS32Float,
- TexCubeS32FloatLevel,
- TexCubeU32Float,
- TexCubeU32FloatLevel,
- TexCubeArrayFloatFloat,
- TexCubeArrayFloatFloatLevel,
- TexCubeArrayS32Float,
- TexCubeArrayS32FloatLevel,
- TexCubeArrayU32Float,
- TexCubeArrayU32FloatLevel,
- Tld4R2DFloatFloat,
- Tld4G2DFloatFloat,
- Tld4B2DFloatFloat,
- Tld4A2DFloatFloat,
- Tld4R2DS64Float,
- Tld4G2DS64Float,
- Tld4B2DS64Float,
- Tld4A2DS64Float,
- Tld4R2DU64Float,
- Tld4G2DU64Float,
- Tld4B2DU64Float,
- Tld4A2DU64Float,
- TexUnified1DFloatS32,
- TexUnified1DFloatFloat,
- TexUnified1DFloatFloatLevel,
- TexUnified1DFloatFloatGrad,
- TexUnified1DS32S32,
- TexUnified1DS32Float,
- TexUnified1DS32FloatLevel,
- TexUnified1DS32FloatGrad,
- TexUnified1DU32S32,
- TexUnified1DU32Float,
- TexUnified1DU32FloatLevel,
- TexUnified1DU32FloatGrad,
- TexUnified1DArrayFloatS32,
- TexUnified1DArrayFloatFloat,
- TexUnified1DArrayFloatFloatLevel,
- TexUnified1DArrayFloatFloatGrad,
- TexUnified1DArrayS32S32,
- TexUnified1DArrayS32Float,
- TexUnified1DArrayS32FloatLevel,
- TexUnified1DArrayS32FloatGrad,
- TexUnified1DArrayU32S32,
- TexUnified1DArrayU32Float,
- TexUnified1DArrayU32FloatLevel,
- TexUnified1DArrayU32FloatGrad,
- TexUnified2DFloatS32,
- TexUnified2DFloatFloat,
- TexUnified2DFloatFloatLevel,
- TexUnified2DFloatFloatGrad,
- TexUnified2DS32S32,
- TexUnified2DS32Float,
- TexUnified2DS32FloatLevel,
- TexUnified2DS32FloatGrad,
- TexUnified2DU32S32,
- TexUnified2DU32Float,
- TexUnified2DU32FloatLevel,
- TexUnified2DU32FloatGrad,
- TexUnified2DArrayFloatS32,
- TexUnified2DArrayFloatFloat,
- TexUnified2DArrayFloatFloatLevel,
- TexUnified2DArrayFloatFloatGrad,
- TexUnified2DArrayS32S32,
- TexUnified2DArrayS32Float,
- TexUnified2DArrayS32FloatLevel,
- TexUnified2DArrayS32FloatGrad,
- TexUnified2DArrayU32S32,
- TexUnified2DArrayU32Float,
- TexUnified2DArrayU32FloatLevel,
- TexUnified2DArrayU32FloatGrad,
- TexUnified3DFloatS32,
- TexUnified3DFloatFloat,
- TexUnified3DFloatFloatLevel,
- TexUnified3DFloatFloatGrad,
- TexUnified3DS32S32,
- TexUnified3DS32Float,
- TexUnified3DS32FloatLevel,
- TexUnified3DS32FloatGrad,
- TexUnified3DU32S32,
- TexUnified3DU32Float,
- TexUnified3DU32FloatLevel,
- TexUnified3DU32FloatGrad,
- TexUnifiedCubeFloatFloat,
- TexUnifiedCubeFloatFloatLevel,
- TexUnifiedCubeS32Float,
- TexUnifiedCubeS32FloatLevel,
- TexUnifiedCubeU32Float,
- TexUnifiedCubeU32FloatLevel,
- TexUnifiedCubeArrayFloatFloat,
- TexUnifiedCubeArrayFloatFloatLevel,
- TexUnifiedCubeArrayS32Float,
- TexUnifiedCubeArrayS32FloatLevel,
- TexUnifiedCubeArrayU32Float,
- TexUnifiedCubeArrayU32FloatLevel,
- TexUnifiedCubeFloatFloatGrad,
- TexUnifiedCubeS32FloatGrad,
- TexUnifiedCubeU32FloatGrad,
- TexUnifiedCubeArrayFloatFloatGrad,
- TexUnifiedCubeArrayS32FloatGrad,
- TexUnifiedCubeArrayU32FloatGrad,
- Tld4UnifiedR2DFloatFloat,
- Tld4UnifiedG2DFloatFloat,
- Tld4UnifiedB2DFloatFloat,
- Tld4UnifiedA2DFloatFloat,
- Tld4UnifiedR2DS64Float,
- Tld4UnifiedG2DS64Float,
- Tld4UnifiedB2DS64Float,
- Tld4UnifiedA2DS64Float,
- Tld4UnifiedR2DU64Float,
- Tld4UnifiedG2DU64Float,
- Tld4UnifiedB2DU64Float,
- Tld4UnifiedA2DU64Float,
-
- // Surface intrinsics
- Suld1DI8Clamp,
- Suld1DI16Clamp,
- Suld1DI32Clamp,
- Suld1DI64Clamp,
- Suld1DV2I8Clamp,
- Suld1DV2I16Clamp,
- Suld1DV2I32Clamp,
- Suld1DV2I64Clamp,
- Suld1DV4I8Clamp,
- Suld1DV4I16Clamp,
- Suld1DV4I32Clamp,
-
- Suld1DArrayI8Clamp,
- Suld1DArrayI16Clamp,
- Suld1DArrayI32Clamp,
- Suld1DArrayI64Clamp,
- Suld1DArrayV2I8Clamp,
- Suld1DArrayV2I16Clamp,
- Suld1DArrayV2I32Clamp,
- Suld1DArrayV2I64Clamp,
- Suld1DArrayV4I8Clamp,
- Suld1DArrayV4I16Clamp,
- Suld1DArrayV4I32Clamp,
-
- Suld2DI8Clamp,
- Suld2DI16Clamp,
- Suld2DI32Clamp,
- Suld2DI64Clamp,
- Suld2DV2I8Clamp,
- Suld2DV2I16Clamp,
- Suld2DV2I32Clamp,
- Suld2DV2I64Clamp,
- Suld2DV4I8Clamp,
- Suld2DV4I16Clamp,
- Suld2DV4I32Clamp,
-
- Suld2DArrayI8Clamp,
- Suld2DArrayI16Clamp,
- Suld2DArrayI32Clamp,
- Suld2DArrayI64Clamp,
- Suld2DArrayV2I8Clamp,
- Suld2DArrayV2I16Clamp,
- Suld2DArrayV2I32Clamp,
- Suld2DArrayV2I64Clamp,
- Suld2DArrayV4I8Clamp,
- Suld2DArrayV4I16Clamp,
- Suld2DArrayV4I32Clamp,
-
- Suld3DI8Clamp,
- Suld3DI16Clamp,
- Suld3DI32Clamp,
- Suld3DI64Clamp,
- Suld3DV2I8Clamp,
- Suld3DV2I16Clamp,
- Suld3DV2I32Clamp,
- Suld3DV2I64Clamp,
- Suld3DV4I8Clamp,
- Suld3DV4I16Clamp,
- Suld3DV4I32Clamp,
-
- Suld1DI8Trap,
- Suld1DI16Trap,
- Suld1DI32Trap,
- Suld1DI64Trap,
- Suld1DV2I8Trap,
- Suld1DV2I16Trap,
- Suld1DV2I32Trap,
- Suld1DV2I64Trap,
- Suld1DV4I8Trap,
- Suld1DV4I16Trap,
- Suld1DV4I32Trap,
-
- Suld1DArrayI8Trap,
- Suld1DArrayI16Trap,
- Suld1DArrayI32Trap,
- Suld1DArrayI64Trap,
- Suld1DArrayV2I8Trap,
- Suld1DArrayV2I16Trap,
- Suld1DArrayV2I32Trap,
- Suld1DArrayV2I64Trap,
- Suld1DArrayV4I8Trap,
- Suld1DArrayV4I16Trap,
- Suld1DArrayV4I32Trap,
-
- Suld2DI8Trap,
- Suld2DI16Trap,
- Suld2DI32Trap,
- Suld2DI64Trap,
- Suld2DV2I8Trap,
- Suld2DV2I16Trap,
- Suld2DV2I32Trap,
- Suld2DV2I64Trap,
- Suld2DV4I8Trap,
- Suld2DV4I16Trap,
- Suld2DV4I32Trap,
-
- Suld2DArrayI8Trap,
- Suld2DArrayI16Trap,
- Suld2DArrayI32Trap,
- Suld2DArrayI64Trap,
- Suld2DArrayV2I8Trap,
- Suld2DArrayV2I16Trap,
- Suld2DArrayV2I32Trap,
- Suld2DArrayV2I64Trap,
- Suld2DArrayV4I8Trap,
- Suld2DArrayV4I16Trap,
- Suld2DArrayV4I32Trap,
-
- Suld3DI8Trap,
- Suld3DI16Trap,
- Suld3DI32Trap,
- Suld3DI64Trap,
- Suld3DV2I8Trap,
- Suld3DV2I16Trap,
- Suld3DV2I32Trap,
- Suld3DV2I64Trap,
- Suld3DV4I8Trap,
- Suld3DV4I16Trap,
- Suld3DV4I32Trap,
-
- Suld1DI8Zero,
- Suld1DI16Zero,
- Suld1DI32Zero,
- Suld1DI64Zero,
- Suld1DV2I8Zero,
- Suld1DV2I16Zero,
- Suld1DV2I32Zero,
- Suld1DV2I64Zero,
- Suld1DV4I8Zero,
- Suld1DV4I16Zero,
- Suld1DV4I32Zero,
-
- Suld1DArrayI8Zero,
- Suld1DArrayI16Zero,
- Suld1DArrayI32Zero,
- Suld1DArrayI64Zero,
- Suld1DArrayV2I8Zero,
- Suld1DArrayV2I16Zero,
- Suld1DArrayV2I32Zero,
- Suld1DArrayV2I64Zero,
- Suld1DArrayV4I8Zero,
- Suld1DArrayV4I16Zero,
- Suld1DArrayV4I32Zero,
-
- Suld2DI8Zero,
- Suld2DI16Zero,
- Suld2DI32Zero,
- Suld2DI64Zero,
- Suld2DV2I8Zero,
- Suld2DV2I16Zero,
- Suld2DV2I32Zero,
- Suld2DV2I64Zero,
- Suld2DV4I8Zero,
- Suld2DV4I16Zero,
- Suld2DV4I32Zero,
-
- Suld2DArrayI8Zero,
- Suld2DArrayI16Zero,
- Suld2DArrayI32Zero,
- Suld2DArrayI64Zero,
- Suld2DArrayV2I8Zero,
- Suld2DArrayV2I16Zero,
- Suld2DArrayV2I32Zero,
- Suld2DArrayV2I64Zero,
- Suld2DArrayV4I8Zero,
- Suld2DArrayV4I16Zero,
- Suld2DArrayV4I32Zero,
-
- Suld3DI8Zero,
- Suld3DI16Zero,
- Suld3DI32Zero,
- Suld3DI64Zero,
- Suld3DV2I8Zero,
- Suld3DV2I16Zero,
- Suld3DV2I32Zero,
- Suld3DV2I64Zero,
- Suld3DV4I8Zero,
- Suld3DV4I16Zero,
- Suld3DV4I32Zero
};
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 429e019163a388..d227e09ce6660d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -7078,3 +7078,738 @@ defm INT_SET_MAXNREG_DEC : SET_MAXNREG<"dec", int_nvvm_setmaxnreg_dec_sync_align
} // isConvergent
def INT_EXIT : NVPTXInst<(outs), (ins), "exit;", [(int_nvvm_exit)]>;
+
+def : Pat<(int_nvvm_tex_1d_v4f32_s32 i64:$t, i64:$s, i32:$x),
+ (TEX_1D_F32_S32_RR $t, $s, $x)>;
+def : Pat<(int_nvvm_tex_1d_v4f32_f32 i64:$t, i64:$s, f32:$x),
+ (TEX_1D_F32_F32_RR $t, $s, $x)>;
+def : Pat<(int_nvvm_tex_1d_v4s32_s32 i64:$t, i64:$s, i32:$x),
+ (TEX_1D_S32_S32_RR $t, $s, $x)>;
+def : Pat<(int_nvvm_tex_1d_v4s32_f32 i64:$t, i64:$s, f32:$x),
+ (TEX_1D_S32_F32_RR $t, $s, $x)>;
+def : Pat<(int_nvvm_tex_1d_v4u32_s32 i64:$t, i64:$s, i32:$x),
+ (TEX_1D_U32_S32_RR $t, $s, $x)>;
+def : Pat<(int_nvvm_tex_1d_v4u32_f32 i64:$t, i64:$s, f32:$x),
+ (TEX_1D_U32_F32_RR $t, $s, $x)>;
+
+def : Pat<(int_nvvm_tex_1d_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$lod),
+ (TEX_1D_F32_F32_LEVEL_RR $t, $s, $x, $lod)>;
+def : Pat<(int_nvvm_tex_1d_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$lod),
+ (TEX_1D_S32_F32_LEVEL_RR $t, $s, $x, $lod)>;
+def : Pat<(int_nvvm_tex_1d_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$lod),
+ (TEX_1D_U32_F32_LEVEL_RR $t, $s, $x, $lod)>;
+
+def : Pat<(int_nvvm_tex_1d_grad_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_1D_F32_F32_GRAD_RR $t, $s, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_1d_grad_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_1D_S32_F32_GRAD_RR $t, $s, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_1d_grad_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_1D_U32_F32_GRAD_RR $t, $s, $x, $gradx, $grady)>;
+
+def : Pat<(int_nvvm_tex_1d_array_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x),
+ (TEX_1D_ARRAY_F32_F32_RR $t, $s, $l, $x)>;
+def : Pat<(int_nvvm_tex_1d_array_v4f32_s32 i64:$t, i64:$s, i32:$l, i32:$x),
+ (TEX_1D_ARRAY_F32_S32_RR $t, $s, $l, $x)>;
+def : Pat<(int_nvvm_tex_1d_array_v4s32_s32 i64:$t, i64:$s, i32:$l, i32:$x),
+ (TEX_1D_ARRAY_S32_S32_RR $t, $s, $l, $x)>;
+def : Pat<(int_nvvm_tex_1d_array_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x),
+ (TEX_1D_ARRAY_S32_F32_RR $t, $s, $l, $x)>;
+def : Pat<(int_nvvm_tex_1d_array_v4u32_s32 i64:$t, i64:$s, i32:$l, i32:$x),
+ (TEX_1D_ARRAY_U32_S32_RR $t, $s, $l, $x)>;
+def : Pat<(int_nvvm_tex_1d_array_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x),
+ (TEX_1D_ARRAY_U32_F32_RR $t, $s, $l, $x)>;
+
+def : Pat<(int_nvvm_tex_1d_array_level_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$lod),
+ (TEX_1D_ARRAY_F32_F32_LEVEL_RR $t, $s, $l, $x, $lod)>;
+def : Pat<(int_nvvm_tex_1d_array_level_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$lod),
+ (TEX_1D_ARRAY_S32_F32_LEVEL_RR $t, $s, $l, $x, $lod)>;
+def : Pat<(int_nvvm_tex_1d_array_level_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$lod),
+ (TEX_1D_ARRAY_U32_F32_LEVEL_RR $t, $s, $l, $x, $lod)>;
+
+def : Pat<(int_nvvm_tex_1d_array_grad_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_1D_ARRAY_F32_F32_GRAD_RR $t, $s, $l, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_1d_array_grad_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_1D_ARRAY_S32_F32_GRAD_RR $t, $s, $l, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_1d_array_grad_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_1D_ARRAY_U32_F32_GRAD_RR $t, $s, $l, $x, $gradx, $grady)>;
+
+def : Pat<(int_nvvm_tex_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TEX_2D_F32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_v4f32_s32 i64:$t, i64:$s, i32:$x, i32:$y),
+ (TEX_2D_F32_S32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_v4s32_s32 i64:$t, i64:$s, i32:$x, i32:$y),
+ (TEX_2D_S32_S32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TEX_2D_S32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_v4u32_s32 i64:$t, i64:$s, i32:$x, i32:$y),
+ (TEX_2D_U32_S32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TEX_2D_U32_F32_RR $t, $s, $x, $y)>;
+
+def : Pat<(int_nvvm_tex_2d_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$lod),
+ (TEX_2D_F32_F32_LEVEL_RR $t, $s, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_2d_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$lod),
+ (TEX_2D_S32_F32_LEVEL_RR $t, $s, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_2d_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$lod),
+ (TEX_2D_U32_F32_LEVEL_RR $t, $s, $x, $y, $lod)>;
+
+def : Pat<(int_nvvm_tex_2d_grad_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_2D_F32_F32_GRAD_RR $t, $s, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_2d_grad_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_2D_S32_F32_GRAD_RR $t, $s, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_2d_grad_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_2D_U32_F32_GRAD_RR $t, $s, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+
+def : Pat<(int_nvvm_tex_2d_array_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y),
+ (TEX_2D_ARRAY_F32_F32_RR $t, $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_array_v4f32_s32 i64:$t, i64:$s, i32:$l, i32:$x, i32:$y),
+ (TEX_2D_ARRAY_F32_S32_RR $t, $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_array_v4s32_s32 i64:$t, i64:$s, i32:$l, i32:$x, i32:$y),
+ (TEX_2D_ARRAY_S32_S32_RR $t, $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_array_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y),
+ (TEX_2D_ARRAY_S32_F32_RR $t, $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_array_v4u32_s32 i64:$t, i64:$s, i32:$l, i32:$x, i32:$y),
+ (TEX_2D_ARRAY_U32_S32_RR $t, $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_2d_array_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y),
+ (TEX_2D_ARRAY_U32_F32_RR $t, $s, $l, $x, $y)>;
+
+def : Pat<(int_nvvm_tex_2d_array_level_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$lod),
+ (TEX_2D_ARRAY_F32_F32_LEVEL_RR $t, $s, $l, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_2d_array_level_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$lod),
+ (TEX_2D_ARRAY_S32_F32_LEVEL_RR $t, $s, $l, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_2d_array_level_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$lod),
+ (TEX_2D_ARRAY_U32_F32_LEVEL_RR $t, $s, $l, $x, $y, $lod)>;
+
+def : Pat<(int_nvvm_tex_2d_array_grad_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_2D_ARRAY_F32_F32_GRAD_RR $t, $s, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_2d_array_grad_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_2D_ARRAY_S32_F32_GRAD_RR $t, $s, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_2d_array_grad_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_2D_ARRAY_U32_F32_GRAD_RR $t, $s, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+
+def : Pat<(int_nvvm_tex_3d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
+ (TEX_3D_F32_F32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_3d_v4f32_s32 i64:$t, i64:$s, i32:$x, i32:$y, i32:$z),
+ (TEX_3D_F32_S32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_3d_v4s32_s32 i64:$t, i64:$s, i32:$x, i32:$y, i32:$z),
+ (TEX_3D_S32_S32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_3d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
+ (TEX_3D_S32_F32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_3d_v4u32_s32 i64:$t, i64:$s, i32:$x, i32:$y, i32:$z),
+ (TEX_3D_U32_S32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_3d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
+ (TEX_3D_U32_F32_RR $t, $s, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_tex_3d_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_3D_F32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_3d_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_3D_S32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_3d_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_3D_U32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
+
+def : Pat<(int_nvvm_tex_3d_grad_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_3D_F32_F32_GRAD_RR $t, $s, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_3d_grad_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_3D_S32_F32_GRAD_RR $t, $s, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_3d_grad_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_3D_U32_F32_GRAD_RR $t, $s, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+
+def : Pat<(int_nvvm_tex_cube_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
+ (TEX_CUBE_F32_F32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_cube_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
+ (TEX_CUBE_S32_F32_RR $t, $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_cube_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
+ (TEX_CUBE_U32_F32_RR $t, $s, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_tex_cube_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_CUBE_F32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_cube_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_CUBE_S32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_cube_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_CUBE_U32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
+
+def : Pat<(int_nvvm_tex_cube_array_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z),
+ (TEX_CUBE_ARRAY_F32_F32_RR $t, $s, $l, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_cube_array_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z),
+ (TEX_CUBE_ARRAY_S32_F32_RR $t, $s, $l, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_cube_array_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z),
+ (TEX_CUBE_ARRAY_U32_F32_RR $t, $s, $l, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_tex_cube_array_level_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_CUBE_ARRAY_F32_F32_LEVEL_RR $t, $s, $l, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_cube_array_level_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_CUBE_ARRAY_S32_F32_LEVEL_RR $t, $s, $l, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_cube_array_level_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_CUBE_ARRAY_U32_F32_LEVEL_RR $t, $s, $l, $x, $y, $z, $lod)>;
+
+def : Pat<(int_nvvm_tld4_r_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_R_2D_F32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_g_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_G_2D_F32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_b_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_B_2D_F32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_a_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_A_2D_F32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_r_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_R_2D_S32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_g_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_G_2D_S32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_b_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_B_2D_S32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_a_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_A_2D_S32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_r_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_R_2D_U32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_g_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_G_2D_U32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_b_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_B_2D_U32_F32_RR $t, $s, $x, $y)>;
+def : Pat<(int_nvvm_tld4_a_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
+ (TLD4_A_2D_U32_F32_RR $t, $s, $x, $y)>;
+
+def : Pat<(int_nvvm_tex_unified_1d_v4f32_s32 i64:$t, i32:$x),
+ (TEX_UNIFIED_1D_F32_S32_R $t, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_v4f32_f32 i64:$t, f32:$x),
+ (TEX_UNIFIED_1D_F32_F32_R $t, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_v4s32_s32 i64:$t, i32:$x),
+ (TEX_UNIFIED_1D_S32_S32_R $t, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_v4s32_f32 i64:$t, f32:$x),
+ (TEX_UNIFIED_1D_S32_F32_R $t, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_v4u32_s32 i64:$t, i32:$x),
+ (TEX_UNIFIED_1D_U32_S32_R $t, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_v4u32_f32 i64:$t, f32:$x),
+ (TEX_UNIFIED_1D_U32_F32_R $t, $x)>;
+
+def : Pat<(int_nvvm_tex_unified_1d_level_v4f32_f32 i64:$t, f32:$x, f32:$lod),
+ (TEX_UNIFIED_1D_F32_F32_LEVEL_R $t, $x, $lod)>;
+def : Pat<(int_nvvm_tex_unified_1d_level_v4s32_f32 i64:$t, f32:$x, f32:$lod),
+ (TEX_UNIFIED_1D_S32_F32_LEVEL_R $t, $x, $lod)>;
+def : Pat<(int_nvvm_tex_unified_1d_level_v4u32_f32 i64:$t, f32:$x, f32:$lod),
+ (TEX_UNIFIED_1D_U32_F32_LEVEL_R $t, $x, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_1d_grad_v4f32_f32 i64:$t, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_UNIFIED_1D_F32_F32_GRAD_R $t, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_unified_1d_grad_v4s32_f32 i64:$t, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_UNIFIED_1D_S32_F32_GRAD_R $t, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_unified_1d_grad_v4u32_f32 i64:$t, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_UNIFIED_1D_U32_F32_GRAD_R $t, $x, $gradx, $grady)>;
+
+def : Pat<(int_nvvm_tex_unified_1d_array_v4f32_s32 i64:$t, i32:$l, i32:$x),
+ (TEX_UNIFIED_1D_ARRAY_F32_S32_R $t, $l, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_v4f32_f32 i64:$t, i32:$l, f32:$x),
+ (TEX_UNIFIED_1D_ARRAY_F32_F32_R $t, $l, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_v4s32_s32 i64:$t, i32:$l, i32:$x),
+ (TEX_UNIFIED_1D_ARRAY_S32_S32_R $t, $l, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_v4s32_f32 i64:$t, i32:$l, f32:$x),
+ (TEX_UNIFIED_1D_ARRAY_S32_F32_R $t, $l, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_v4u32_s32 i64:$t, i32:$l, i32:$x),
+ (TEX_UNIFIED_1D_ARRAY_U32_S32_R $t, $l, $x)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_v4u32_f32 i64:$t, i32:$l, f32:$x),
+ (TEX_UNIFIED_1D_ARRAY_U32_F32_R $t, $l, $x)>;
+
+def : Pat<(int_nvvm_tex_unified_1d_array_level_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$lod),
+ (TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL_R $t, $l, $x, $lod)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_level_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$lod),
+ (TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL_R $t, $l, $x, $lod)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_level_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$lod),
+ (TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL_R $t, $l, $x, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_1d_array_grad_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD_R $t, $l, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_grad_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD_R $t, $l, $x, $gradx, $grady)>;
+def : Pat<(int_nvvm_tex_unified_1d_array_grad_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$gradx, f32:$grady),
+ (TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD_R $t, $l, $x, $gradx, $grady)>;
+
+def : Pat<(int_nvvm_tex_unified_2d_v4f32_s32 i64:$t, i32:$x, i32:$y),
+ (TEX_UNIFIED_2D_F32_S32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
+ (TEX_UNIFIED_2D_F32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_v4s32_s32 i64:$t, i32:$x, i32:$y),
+ (TEX_UNIFIED_2D_S32_S32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
+ (TEX_UNIFIED_2D_S32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_v4u32_s32 i64:$t, i32:$x, i32:$y),
+ (TEX_UNIFIED_2D_U32_S32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
+ (TEX_UNIFIED_2D_U32_F32_R $t, $x, $y)>;
+
+def : Pat<(int_nvvm_tex_unified_2d_level_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$lod),
+ (TEX_UNIFIED_2D_F32_F32_LEVEL_R $t, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_unified_2d_level_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$lod),
+ (TEX_UNIFIED_2D_S32_F32_LEVEL_R $t, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_unified_2d_level_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$lod),
+ (TEX_UNIFIED_2D_U32_F32_LEVEL_R $t, $x, $y, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_2d_grad_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_UNIFIED_2D_F32_F32_GRAD_R $t, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_unified_2d_grad_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_UNIFIED_2D_S32_F32_GRAD_R $t, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_unified_2d_grad_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_UNIFIED_2D_U32_F32_GRAD_R $t, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+
+def : Pat<(int_nvvm_tex_unified_2d_array_v4f32_s32 i64:$t, i32:$l, i32:$x, i32:$y),
+ (TEX_UNIFIED_2D_ARRAY_F32_S32_R $t, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y),
+ (TEX_UNIFIED_2D_ARRAY_F32_F32_R $t, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_v4s32_s32 i64:$t, i32:$l, i32:$x, i32:$y),
+ (TEX_UNIFIED_2D_ARRAY_S32_S32_R $t, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y),
+ (TEX_UNIFIED_2D_ARRAY_S32_F32_R $t, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_v4u32_s32 i64:$t, i32:$l, i32:$x, i32:$y),
+ (TEX_UNIFIED_2D_ARRAY_U32_S32_R $t, $l, $x, $y)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y),
+ (TEX_UNIFIED_2D_ARRAY_U32_F32_R $t, $l, $x, $y)>;
+
+def : Pat<(int_nvvm_tex_unified_2d_array_level_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$lod),
+ (TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL_R $t, $l, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_level_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$lod),
+ (TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL_R $t, $l, $x, $y, $lod)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_level_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$lod),
+ (TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL_R $t, $l, $x, $y, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_2d_array_grad_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD_R $t, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_grad_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD_R $t, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+def : Pat<(int_nvvm_tex_unified_2d_array_grad_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
+ (TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD_R $t, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
+
+def : Pat<(int_nvvm_tex_unified_3d_v4f32_s32 i64:$t, i32:$x, i32:$y, i32:$z),
+ (TEX_UNIFIED_3D_F32_S32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_3d_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_3D_F32_F32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_3d_v4s32_s32 i64:$t, i32:$x, i32:$y, i32:$z),
+ (TEX_UNIFIED_3D_S32_S32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_3d_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_3D_S32_F32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_3d_v4u32_s32 i64:$t, i32:$x, i32:$y, i32:$z),
+ (TEX_UNIFIED_3D_U32_S32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_3d_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_3D_U32_F32_R $t, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_tex_unified_3d_level_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_3D_F32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_unified_3d_level_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_3D_S32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_unified_3d_level_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_3D_U32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_3d_grad_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_3D_F32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_unified_3d_grad_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_3D_S32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_unified_3d_grad_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_3D_U32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+
+def : Pat<(int_nvvm_tex_unified_cube_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_CUBE_F32_F32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_cube_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_CUBE_S32_F32_R $t, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_cube_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_CUBE_U32_F32_R $t, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_tex_unified_cube_level_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_CUBE_F32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_unified_cube_level_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_CUBE_S32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_unified_cube_level_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_CUBE_U32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_cube_array_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_CUBE_ARRAY_F32_F32_R $t, $l, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_cube_array_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_CUBE_ARRAY_S32_F32_R $t, $l, $x, $y, $z)>;
+def : Pat<(int_nvvm_tex_unified_cube_array_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z),
+ (TEX_UNIFIED_CUBE_ARRAY_U32_F32_R $t, $l, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_tex_unified_cube_array_level_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL_R $t, $l, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_unified_cube_array_level_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL_R $t, $l, $x, $y, $z, $lod)>;
+def : Pat<(int_nvvm_tex_unified_cube_array_level_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
+ (TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_R $t, $l, $x, $y, $z, $lod)>;
+
+def : Pat<(int_nvvm_tex_unified_cube_grad_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_CUBE_F32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_unified_cube_grad_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_CUBE_S32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_unified_cube_grad_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_CUBE_U32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+
+def : Pat<(int_nvvm_tex_unified_cube_array_grad_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R $t, $l, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_unified_cube_array_grad_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R $t, $l, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+def : Pat<(int_nvvm_tex_unified_cube_array_grad_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
+ (TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R $t, $l, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
+
+def : Pat<(int_nvvm_tld4_unified_r_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_R_2D_F32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_g_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_G_2D_F32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_b_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_B_2D_F32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_a_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_A_2D_F32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_r_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_R_2D_S32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_g_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_G_2D_S32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_b_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_B_2D_S32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_a_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_A_2D_S32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_r_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_R_2D_U32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_g_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_G_2D_U32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_b_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_B_2D_U32_F32_R $t, $x, $y)>;
+def : Pat<(int_nvvm_tld4_unified_a_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
+ (TLD4_UNIFIED_A_2D_U32_F32_R $t, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_1d_i8_clamp i64:$s, i32:$x),
+ (SULD_1D_I8_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i16_clamp i64:$s, i32:$x),
+ (SULD_1D_I16_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i32_clamp i64:$s, i32:$x),
+ (SULD_1D_I32_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i64_clamp i64:$s, i32:$x),
+ (SULD_1D_I64_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i8_clamp i64:$s, i32:$x),
+ (SULD_1D_V2I8_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i16_clamp i64:$s, i32:$x),
+ (SULD_1D_V2I16_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i32_clamp i64:$s, i32:$x),
+ (SULD_1D_V2I32_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i64_clamp i64:$s, i32:$x),
+ (SULD_1D_V2I64_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i8_clamp i64:$s, i32:$x),
+ (SULD_1D_V4I8_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i16_clamp i64:$s, i32:$x),
+ (SULD_1D_V4I16_CLAMP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i32_clamp i64:$s, i32:$x),
+ (SULD_1D_V4I32_CLAMP_R $s, $x)>;
+
+def : Pat<(int_nvvm_suld_1d_array_i8_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I8_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i16_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I16_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i32_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I32_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i64_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I64_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i8_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I8_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i16_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I16_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i32_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I32_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i64_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I64_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i8_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I8_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i16_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I16_CLAMP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i32_clamp i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I32_CLAMP_R $s, $l, $x)>;
+
+def : Pat<(int_nvvm_suld_2d_i8_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I8_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i16_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I16_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i32_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I32_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i64_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I64_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i8_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I8_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i16_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I16_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i32_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I32_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i64_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I64_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i8_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I8_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i16_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I16_CLAMP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i32_clamp i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I32_CLAMP_R $s, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_2d_array_i8_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I8_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i16_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I16_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i32_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I32_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i64_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I64_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i8_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I8_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i16_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I16_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i32_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I32_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i64_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I64_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i8_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I8_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i16_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I16_CLAMP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i32_clamp i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I32_CLAMP_R $s, $l, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_3d_i8_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I8_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i16_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I16_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i32_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I32_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i64_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I64_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i8_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I8_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i16_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I16_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i32_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I32_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i64_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I64_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i8_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I8_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i16_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I16_CLAMP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i32_clamp i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I32_CLAMP_R $s, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_suld_1d_i8_trap i64:$s, i32:$x),
+ (SULD_1D_I8_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i16_trap i64:$s, i32:$x),
+ (SULD_1D_I16_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i32_trap i64:$s, i32:$x),
+ (SULD_1D_I32_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i64_trap i64:$s, i32:$x),
+ (SULD_1D_I64_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i8_trap i64:$s, i32:$x),
+ (SULD_1D_V2I8_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i16_trap i64:$s, i32:$x),
+ (SULD_1D_V2I16_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i32_trap i64:$s, i32:$x),
+ (SULD_1D_V2I32_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i64_trap i64:$s, i32:$x),
+ (SULD_1D_V2I64_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i8_trap i64:$s, i32:$x),
+ (SULD_1D_V4I8_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i16_trap i64:$s, i32:$x),
+ (SULD_1D_V4I16_TRAP_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i32_trap i64:$s, i32:$x),
+ (SULD_1D_V4I32_TRAP_R $s, $x)>;
+
+def : Pat<(int_nvvm_suld_1d_array_i8_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I8_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i16_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I16_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i32_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I32_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i64_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I64_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i8_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I8_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i16_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I16_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i32_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I32_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i64_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I64_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i8_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I8_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i16_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I16_TRAP_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i32_trap i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I32_TRAP_R $s, $l, $x)>;
+
+def : Pat<(int_nvvm_suld_2d_i8_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I8_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i16_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I16_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i32_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I32_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i64_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I64_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i8_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I8_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i16_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I16_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i32_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I32_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i64_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I64_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i8_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I8_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i16_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I16_TRAP_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i32_trap i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I32_TRAP_R $s, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_2d_array_i8_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I8_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i16_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I16_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i32_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I32_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i64_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I64_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i8_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I8_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i16_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I16_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i32_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I32_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i64_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I64_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i8_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I8_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i16_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I16_TRAP_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i32_trap i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I32_TRAP_R $s, $l, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_3d_i8_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I8_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i16_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I16_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i32_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I32_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i64_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I64_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i8_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I8_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i16_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I16_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i32_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I32_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i64_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I64_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i8_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I8_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i16_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I16_TRAP_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i32_trap i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I32_TRAP_R $s, $x, $y, $z)>;
+
+def : Pat<(int_nvvm_suld_1d_i8_zero i64:$s, i32:$x),
+ (SULD_1D_I8_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i16_zero i64:$s, i32:$x),
+ (SULD_1D_I16_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i32_zero i64:$s, i32:$x),
+ (SULD_1D_I32_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_i64_zero i64:$s, i32:$x),
+ (SULD_1D_I64_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i8_zero i64:$s, i32:$x),
+ (SULD_1D_V2I8_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i16_zero i64:$s, i32:$x),
+ (SULD_1D_V2I16_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i32_zero i64:$s, i32:$x),
+ (SULD_1D_V2I32_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v2i64_zero i64:$s, i32:$x),
+ (SULD_1D_V2I64_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i8_zero i64:$s, i32:$x),
+ (SULD_1D_V4I8_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i16_zero i64:$s, i32:$x),
+ (SULD_1D_V4I16_ZERO_R $s, $x)>;
+def : Pat<(int_nvvm_suld_1d_v4i32_zero i64:$s, i32:$x),
+ (SULD_1D_V4I32_ZERO_R $s, $x)>;
+
+def : Pat<(int_nvvm_suld_1d_array_i8_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I8_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i16_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I16_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i32_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I32_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_i64_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_I64_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i8_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I8_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i16_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I16_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i32_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I32_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v2i64_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V2I64_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i8_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I8_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i16_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I16_ZERO_R $s, $l, $x)>;
+def : Pat<(int_nvvm_suld_1d_array_v4i32_zero i64:$s, i32:$l, i32:$x),
+ (SULD_1D_ARRAY_V4I32_ZERO_R $s, $l, $x)>;
+
+def : Pat<(int_nvvm_suld_2d_i8_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I8_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i16_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I16_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i32_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I32_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_i64_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_I64_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i8_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I8_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i16_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I16_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i32_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I32_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v2i64_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V2I64_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i8_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I8_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i16_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I16_ZERO_R $s, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_v4i32_zero i64:$s, i32:$x, i32:$y),
+ (SULD_2D_V4I32_ZERO_R $s, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_2d_array_i8_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I8_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i16_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I16_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i32_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I32_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_i64_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_I64_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i8_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I8_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i16_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I16_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i32_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I32_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v2i64_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V2I64_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i8_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I8_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i16_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I16_ZERO_R $s, $l, $x, $y)>;
+def : Pat<(int_nvvm_suld_2d_array_v4i32_zero i64:$s, i32:$l, i32:$x, i32:$y),
+ (SULD_2D_ARRAY_V4I32_ZERO_R $s, $l, $x, $y)>;
+
+def : Pat<(int_nvvm_suld_3d_i8_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I8_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i16_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I16_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i32_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I32_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_i64_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_I64_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i8_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I8_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i16_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I16_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i32_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I32_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v2i64_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V2I64_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i8_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I8_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i16_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I16_ZERO_R $s, $x, $y, $z)>;
+def : Pat<(int_nvvm_suld_3d_v4i32_zero i64:$s, i32:$x, i32:$y, i32:$z),
+ (SULD_3D_V4I32_ZERO_R $s, $x, $y, $z)>;
>From 50572df7b24fd62effcec8065ec0913fdded7185 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sat, 14 Dec 2024 23:32:24 +0300
Subject: [PATCH 2/4] Integrate surface intrinsic patterns into instructions
---
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 510 ++++++-----------------
1 file changed, 120 insertions(+), 390 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index d227e09ce6660d..618bb691e22587 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -4126,13 +4126,17 @@ defm TLD4_UNIFIED_A_2D_U32_F32
let IsSuld = true in {
-class SULD_1D_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_1D_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r),
!con(surf, (ins Int32Regs:$x)),
inst # " \\{$r\\}, [$s, \\{$x\\}];",
- []>;
+ pattern>;
multiclass SULD_1D<string inst, NVPTXRegClass outtype> {
- def _R : SULD_1D_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_1D_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, (intr i64:$s, i32:$x))]>;
def _I : SULD_1D_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4151,13 +4155,18 @@ defm SULD_1D_I16_ZERO : SULD_1D<"suld.b.1d.b16.zero", Int16Regs>;
defm SULD_1D_I32_ZERO : SULD_1D<"suld.b.1d.b32.zero", Int32Regs>;
defm SULD_1D_I64_ZERO : SULD_1D<"suld.b.1d.b64.zero", Int64Regs>;
-class SULD_1D_ARRAY_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_1D_ARRAY_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r),
!con(surf, (ins Int32Regs:$l, Int32Regs:$x)),
inst # " \\{$r\\}, [$s, \\{$l, $x\\}];",
- []>;
+ pattern>;
multiclass SULD_1D_ARRAY<string inst, NVPTXRegClass outtype> {
- def _R : SULD_1D_ARRAY_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_1D_ARRAY_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r,
+ (intr i64:$s, i32:$l, i32:$x))]>;
def _I : SULD_1D_ARRAY_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4188,13 +4197,17 @@ defm SULD_1D_ARRAY_I32_ZERO
defm SULD_1D_ARRAY_I64_ZERO
: SULD_1D_ARRAY<"suld.b.a1d.b64.zero", Int64Regs>;
-class SULD_2D_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_2D_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r),
!con(surf, (ins Int32Regs:$x, Int32Regs:$y)),
inst # " \\{$r\\}, [$s, \\{$x, $y\\}];",
- []>;
+ pattern>;
multiclass SULD_2D<string inst, NVPTXRegClass outtype> {
- def _R : SULD_2D_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_2D_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, (intr i64:$s, i32:$x, i32:$y))]>;
def _I : SULD_2D_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4213,13 +4226,18 @@ defm SULD_2D_I16_ZERO : SULD_2D<"suld.b.2d.b16.zero", Int16Regs>;
defm SULD_2D_I32_ZERO : SULD_2D<"suld.b.2d.b32.zero", Int32Regs>;
defm SULD_2D_I64_ZERO : SULD_2D<"suld.b.2d.b64.zero", Int64Regs>;
-class SULD_2D_ARRAY_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_2D_ARRAY_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r),
!con(surf, (ins Int32Regs:$l, Int32Regs:$x, Int32Regs:$y)),
inst # " \\{$r\\}, [$s, \\{$l, $x, $y, $y\\}];",
- []>;
+ pattern>;
multiclass SULD_2D_ARRAY<string inst, NVPTXRegClass outtype> {
- def _R : SULD_2D_ARRAY_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_2D_ARRAY_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r,
+ (intr i64:$s, i32:$l, i32:$x, i32:$y))]>;
def _I : SULD_2D_ARRAY_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4238,13 +4256,18 @@ defm SULD_2D_ARRAY_I16_ZERO : SULD_2D_ARRAY<"suld.b.a2d.b16.zero", Int16Regs>;
defm SULD_2D_ARRAY_I32_ZERO : SULD_2D_ARRAY<"suld.b.a2d.b32.zero", Int32Regs>;
defm SULD_2D_ARRAY_I64_ZERO : SULD_2D_ARRAY<"suld.b.a2d.b64.zero", Int64Regs>;
-class SULD_3D_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_3D_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r),
!con(surf, (ins Int32Regs:$x, Int32Regs:$y, Int32Regs:$z)),
inst # " \\{$r\\}, [$s, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
multiclass SULD_3D<string inst, NVPTXRegClass outtype> {
- def _R : SULD_3D_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_3D_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r,
+ (intr i64:$s, i32:$x, i32:$y, i32:$z))]>;
def _I : SULD_3D_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4266,13 +4289,18 @@ defm SULD_3D_I64_ZERO : SULD_3D<"suld.b.3d.b64.zero", Int64Regs>;
let IsSuld = 2 in {
-class SULD_1D_V2_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_1D_V2_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g),
!con(surf, (ins Int32Regs:$x)),
inst # " \\{$r, $g\\}, [$s, \\{$x\\}];",
- []>;
+ pattern>;
multiclass SULD_1D_V2<string inst, NVPTXRegClass outtype> {
- def _R : SULD_1D_V2_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_1D_V2_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g,
+ (intr i64:$s, i32:$x))]>;
def _I : SULD_1D_V2_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4291,13 +4319,18 @@ defm SULD_1D_V2I16_ZERO : SULD_1D_V2<"suld.b.1d.v2.b16.zero", Int16Regs>;
defm SULD_1D_V2I32_ZERO : SULD_1D_V2<"suld.b.1d.v2.b32.zero", Int32Regs>;
defm SULD_1D_V2I64_ZERO : SULD_1D_V2<"suld.b.1d.v2.b64.zero", Int64Regs>;
-class SULD_1D_ARRAY_V2_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_1D_ARRAY_V2_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g),
!con(surf, (ins Int32Regs:$l, Int32Regs:$x)),
inst # " \\{$r, $g\\}, [$s, \\{$l, $x\\}];",
- []>;
+ pattern>;
multiclass SULD_1D_ARRAY_V2<string inst, NVPTXRegClass outtype> {
- def _R : SULD_1D_ARRAY_V2_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_1D_ARRAY_V2_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g,
+ (intr i64:$s, i32:$l, i32:$x))]>;
def _I : SULD_1D_ARRAY_V2_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4328,13 +4361,18 @@ defm SULD_1D_ARRAY_V2I32_ZERO
defm SULD_1D_ARRAY_V2I64_ZERO
: SULD_1D_ARRAY_V2<"suld.b.a1d.v2.b64.zero", Int64Regs>;
-class SULD_2D_V2_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_2D_V2_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g),
!con(surf, (ins Int32Regs:$x, Int32Regs:$y)),
inst # " \\{$r, $g\\}, [$s, \\{$x, $y\\}];",
- []>;
+ pattern>;
multiclass SULD_2D_V2<string inst, NVPTXRegClass outtype> {
- def _R : SULD_2D_V2_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_2D_V2_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g,
+ (intr i64:$s, i32:$x, i32:$y))]>;
def _I : SULD_2D_V2_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4365,13 +4403,18 @@ defm SULD_2D_V2I32_ZERO
defm SULD_2D_V2I64_ZERO
: SULD_2D_V2<"suld.b.2d.v2.b64.zero", Int64Regs>;
-class SULD_2D_ARRAY_V2_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_2D_ARRAY_V2_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g),
!con(surf, (ins Int32Regs:$l, Int32Regs:$x, Int32Regs:$y)),
inst # " \\{$r, $g\\}, [$s, \\{$l, $x, $y, $y\\}];",
- []>;
+ pattern>;
multiclass SULD_2D_ARRAY_V2<string inst, NVPTXRegClass outtype> {
- def _R : SULD_2D_ARRAY_V2_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_2D_ARRAY_V2_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g,
+ (intr i64:$s, i32:$l, i32:$x, i32:$y))]>;
def _I : SULD_2D_ARRAY_V2_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4402,13 +4445,18 @@ defm SULD_2D_ARRAY_V2I32_ZERO
defm SULD_2D_ARRAY_V2I64_ZERO
: SULD_2D_ARRAY_V2<"suld.b.a2d.v2.b64.zero", Int64Regs>;
-class SULD_3D_V2_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_3D_V2_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g),
!con(surf, (ins Int32Regs:$x, Int32Regs:$y, Int32Regs:$z)),
inst # " \\{$r, $g\\}, [$s, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
multiclass SULD_3D_V2<string inst, NVPTXRegClass outtype> {
- def _R : SULD_3D_V2_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_3D_V2_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g,
+ (intr i64:$s, i32:$x, i32:$y, i32:$z))]>;
def _I : SULD_3D_V2_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4431,13 +4479,18 @@ defm SULD_3D_V2I64_ZERO : SULD_3D_V2<"suld.b.3d.v2.b64.zero", Int64Regs>;
let IsSuld = 3 in {
-class SULD_1D_V4_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_1D_V4_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g, outtype:$b, outtype:$a),
!con(surf, (ins Int32Regs:$x)),
inst # " \\{$r, $g, $b, $a\\}, [$s, \\{$x\\}];",
- []>;
+ pattern>;
multiclass SULD_1D_V4<string inst, NVPTXRegClass outtype> {
- def _R : SULD_1D_V4_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_1D_V4_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$s, i32:$x))]>;
def _I : SULD_1D_V4_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4453,13 +4506,19 @@ defm SULD_1D_V4I8_ZERO : SULD_1D_V4<"suld.b.1d.v4.b8.zero", Int16Regs>;
defm SULD_1D_V4I16_ZERO : SULD_1D_V4<"suld.b.1d.v4.b16.zero", Int16Regs>;
defm SULD_1D_V4I32_ZERO : SULD_1D_V4<"suld.b.1d.v4.b32.zero", Int32Regs>;
-class SULD_1D_ARRAY_V4_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_1D_ARRAY_V4_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g, outtype:$b, outtype:$a),
!con(surf, (ins Int32Regs:$l, Int32Regs:$x)),
inst # " \\{$r, $g, $b, $a\\}, [$s, \\{$l, $x\\}];",
- []>;
+ pattern>;
multiclass SULD_1D_ARRAY_V4<string inst, NVPTXRegClass outtype> {
- def _R : SULD_1D_ARRAY_V4_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_1D_ARRAY_V4_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b,
+ outtype:$a,
+ (intr i64:$s, i32:$l, i32:$x))]>;
def _I : SULD_1D_ARRAY_V4_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4484,13 +4543,18 @@ defm SULD_1D_ARRAY_V4I16_ZERO
defm SULD_1D_ARRAY_V4I32_ZERO
: SULD_1D_ARRAY_V4<"suld.b.a1d.v4.b32.zero", Int32Regs>;
-class SULD_2D_V4_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_2D_V4_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g, outtype:$b, outtype:$a),
!con(surf, (ins Int32Regs:$x, Int32Regs:$y)),
inst # " \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y\\}];",
- []>;
+ pattern>;
multiclass SULD_2D_V4<string inst, NVPTXRegClass outtype> {
- def _R : SULD_2D_V4_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_2D_V4_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$s, i32:$x, i32:$y))]>;
def _I : SULD_2D_V4_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4506,13 +4570,19 @@ defm SULD_2D_V4I8_ZERO : SULD_2D_V4<"suld.b.2d.v4.b8.zero", Int16Regs>;
defm SULD_2D_V4I16_ZERO : SULD_2D_V4<"suld.b.2d.v4.b16.zero", Int16Regs>;
defm SULD_2D_V4I32_ZERO : SULD_2D_V4<"suld.b.2d.v4.b32.zero", Int32Regs>;
-class SULD_2D_ARRAY_V4_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_2D_ARRAY_V4_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g, outtype:$b, outtype:$a),
!con(surf, (ins Int32Regs:$l, Int32Regs:$x, Int32Regs:$y)),
inst # " \\{$r, $g, $b, $a\\}, [$s, \\{$l, $x, $y, $y\\}];",
- []>;
+ pattern>;
multiclass SULD_2D_ARRAY_V4<string inst, NVPTXRegClass outtype> {
- def _R : SULD_2D_ARRAY_V4_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_2D_ARRAY_V4_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b,
+ outtype:$a,
+ (intr i64:$s, i32:$l, i32:$x, i32:$y))]>;
def _I : SULD_2D_ARRAY_V4_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -4537,13 +4607,18 @@ defm SULD_2D_ARRAY_V4I16_ZERO
defm SULD_2D_ARRAY_V4I32_ZERO
: SULD_2D_ARRAY_V4<"suld.b.a2d.v4.b32.zero", Int32Regs>;
-class SULD_3D_V4_base<string inst, NVPTXRegClass outtype, dag surf>
+class SULD_3D_V4_base<string inst, NVPTXRegClass outtype, dag surf,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g, outtype:$b, outtype:$a),
!con(surf, (ins Int32Regs:$x, Int32Regs:$y, Int32Regs:$z)),
inst # " \\{$r, $g, $b, $a\\}, [$s, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
multiclass SULD_3D_V4<string inst, NVPTXRegClass outtype> {
- def _R : SULD_3D_V4_base<inst, outtype, (ins Int64Regs:$s)>;
+ defvar intr = !cast<Intrinsic>("int_nvvm_" # !tolower(NAME));
+
+ def _R : SULD_3D_V4_base<inst, outtype, (ins Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$s, i32:$x, i32:$y, i32:$z))]>;
def _I : SULD_3D_V4_base<inst, outtype, (ins i64imm:$s)>;
}
@@ -7468,348 +7543,3 @@ def : Pat<(int_nvvm_tld4_unified_b_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
(TLD4_UNIFIED_B_2D_U32_F32_R $t, $x, $y)>;
def : Pat<(int_nvvm_tld4_unified_a_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
(TLD4_UNIFIED_A_2D_U32_F32_R $t, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_1d_i8_clamp i64:$s, i32:$x),
- (SULD_1D_I8_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i16_clamp i64:$s, i32:$x),
- (SULD_1D_I16_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i32_clamp i64:$s, i32:$x),
- (SULD_1D_I32_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i64_clamp i64:$s, i32:$x),
- (SULD_1D_I64_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i8_clamp i64:$s, i32:$x),
- (SULD_1D_V2I8_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i16_clamp i64:$s, i32:$x),
- (SULD_1D_V2I16_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i32_clamp i64:$s, i32:$x),
- (SULD_1D_V2I32_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i64_clamp i64:$s, i32:$x),
- (SULD_1D_V2I64_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i8_clamp i64:$s, i32:$x),
- (SULD_1D_V4I8_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i16_clamp i64:$s, i32:$x),
- (SULD_1D_V4I16_CLAMP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i32_clamp i64:$s, i32:$x),
- (SULD_1D_V4I32_CLAMP_R $s, $x)>;
-
-def : Pat<(int_nvvm_suld_1d_array_i8_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I8_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i16_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I16_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i32_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I32_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i64_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I64_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i8_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I8_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i16_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I16_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i32_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I32_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i64_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I64_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i8_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I8_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i16_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I16_CLAMP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i32_clamp i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I32_CLAMP_R $s, $l, $x)>;
-
-def : Pat<(int_nvvm_suld_2d_i8_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_I8_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i16_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_I16_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i32_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_I32_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i64_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_I64_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i8_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I8_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i16_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I16_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i32_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I32_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i64_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I64_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i8_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I8_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i16_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I16_CLAMP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i32_clamp i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I32_CLAMP_R $s, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_2d_array_i8_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I8_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i16_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I16_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i32_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I32_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i64_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I64_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i8_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I8_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i16_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I16_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i32_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I32_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i64_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I64_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i8_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I8_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i16_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I16_CLAMP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i32_clamp i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I32_CLAMP_R $s, $l, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_3d_i8_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I8_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i16_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I16_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i32_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I32_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i64_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I64_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i8_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I8_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i16_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I16_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i32_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I32_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i64_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I64_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i8_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I8_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i16_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I16_CLAMP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i32_clamp i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I32_CLAMP_R $s, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_suld_1d_i8_trap i64:$s, i32:$x),
- (SULD_1D_I8_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i16_trap i64:$s, i32:$x),
- (SULD_1D_I16_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i32_trap i64:$s, i32:$x),
- (SULD_1D_I32_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i64_trap i64:$s, i32:$x),
- (SULD_1D_I64_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i8_trap i64:$s, i32:$x),
- (SULD_1D_V2I8_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i16_trap i64:$s, i32:$x),
- (SULD_1D_V2I16_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i32_trap i64:$s, i32:$x),
- (SULD_1D_V2I32_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i64_trap i64:$s, i32:$x),
- (SULD_1D_V2I64_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i8_trap i64:$s, i32:$x),
- (SULD_1D_V4I8_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i16_trap i64:$s, i32:$x),
- (SULD_1D_V4I16_TRAP_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i32_trap i64:$s, i32:$x),
- (SULD_1D_V4I32_TRAP_R $s, $x)>;
-
-def : Pat<(int_nvvm_suld_1d_array_i8_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I8_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i16_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I16_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i32_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I32_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i64_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I64_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i8_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I8_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i16_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I16_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i32_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I32_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i64_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I64_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i8_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I8_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i16_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I16_TRAP_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i32_trap i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I32_TRAP_R $s, $l, $x)>;
-
-def : Pat<(int_nvvm_suld_2d_i8_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_I8_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i16_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_I16_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i32_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_I32_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i64_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_I64_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i8_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I8_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i16_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I16_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i32_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I32_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i64_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I64_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i8_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I8_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i16_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I16_TRAP_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i32_trap i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I32_TRAP_R $s, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_2d_array_i8_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I8_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i16_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I16_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i32_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I32_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i64_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I64_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i8_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I8_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i16_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I16_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i32_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I32_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i64_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I64_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i8_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I8_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i16_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I16_TRAP_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i32_trap i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I32_TRAP_R $s, $l, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_3d_i8_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I8_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i16_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I16_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i32_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I32_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i64_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I64_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i8_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I8_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i16_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I16_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i32_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I32_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i64_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I64_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i8_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I8_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i16_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I16_TRAP_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i32_trap i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I32_TRAP_R $s, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_suld_1d_i8_zero i64:$s, i32:$x),
- (SULD_1D_I8_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i16_zero i64:$s, i32:$x),
- (SULD_1D_I16_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i32_zero i64:$s, i32:$x),
- (SULD_1D_I32_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_i64_zero i64:$s, i32:$x),
- (SULD_1D_I64_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i8_zero i64:$s, i32:$x),
- (SULD_1D_V2I8_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i16_zero i64:$s, i32:$x),
- (SULD_1D_V2I16_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i32_zero i64:$s, i32:$x),
- (SULD_1D_V2I32_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v2i64_zero i64:$s, i32:$x),
- (SULD_1D_V2I64_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i8_zero i64:$s, i32:$x),
- (SULD_1D_V4I8_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i16_zero i64:$s, i32:$x),
- (SULD_1D_V4I16_ZERO_R $s, $x)>;
-def : Pat<(int_nvvm_suld_1d_v4i32_zero i64:$s, i32:$x),
- (SULD_1D_V4I32_ZERO_R $s, $x)>;
-
-def : Pat<(int_nvvm_suld_1d_array_i8_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I8_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i16_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I16_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i32_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I32_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_i64_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_I64_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i8_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I8_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i16_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I16_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i32_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I32_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v2i64_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V2I64_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i8_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I8_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i16_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I16_ZERO_R $s, $l, $x)>;
-def : Pat<(int_nvvm_suld_1d_array_v4i32_zero i64:$s, i32:$l, i32:$x),
- (SULD_1D_ARRAY_V4I32_ZERO_R $s, $l, $x)>;
-
-def : Pat<(int_nvvm_suld_2d_i8_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_I8_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i16_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_I16_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i32_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_I32_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_i64_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_I64_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i8_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I8_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i16_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I16_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i32_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I32_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v2i64_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V2I64_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i8_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I8_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i16_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I16_ZERO_R $s, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_v4i32_zero i64:$s, i32:$x, i32:$y),
- (SULD_2D_V4I32_ZERO_R $s, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_2d_array_i8_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I8_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i16_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I16_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i32_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I32_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_i64_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_I64_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i8_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I8_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i16_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I16_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i32_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I32_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v2i64_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V2I64_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i8_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I8_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i16_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I16_ZERO_R $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_suld_2d_array_v4i32_zero i64:$s, i32:$l, i32:$x, i32:$y),
- (SULD_2D_ARRAY_V4I32_ZERO_R $s, $l, $x, $y)>;
-
-def : Pat<(int_nvvm_suld_3d_i8_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I8_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i16_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I16_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i32_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I32_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_i64_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_I64_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i8_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I8_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i16_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I16_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i32_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I32_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v2i64_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V2I64_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i8_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I8_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i16_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I16_ZERO_R $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_suld_3d_v4i32_zero i64:$s, i32:$x, i32:$y, i32:$z),
- (SULD_3D_V4I32_ZERO_R $s, $x, $y, $z)>;
>From 7a9db7abffdceba22b70cf2c6b231d07bd4877e9 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 15 Dec 2024 04:16:12 +0300
Subject: [PATCH 3/4] Incorporate texture intrinsic patterns into instructions
---
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 1392 ++++++++++------------
1 file changed, 660 insertions(+), 732 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 618bb691e22587..83a67ea3e52805 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -2948,16 +2948,19 @@ let IsTex = true, IsTexModeUnified = false in {
// Texture fetch instructions using handles
class TEX_1D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}];",
- []>;
+ pattern>;
-multiclass TEX_1D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
+multiclass TEX_1D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
+ Intrinsic intr> {
def _RR : TEX_1D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x))]>;
def _RI : TEX_1D_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_1D_base<inst, outtype, intype,
@@ -2966,25 +2969,34 @@ multiclass TEX_1D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
(ins i64imm:$t, i64imm:$s)>;
}
-defm TEX_1D_F32_S32 : TEX_1D<"tex.1d.v4.f32.s32", Float32Regs, Int32Regs>;
-defm TEX_1D_F32_F32 : TEX_1D<"tex.1d.v4.f32.f32", Float32Regs, Float32Regs>;
-defm TEX_1D_S32_S32 : TEX_1D<"tex.1d.v4.s32.s32", Int32Regs, Int32Regs>;
-defm TEX_1D_S32_F32 : TEX_1D<"tex.1d.v4.s32.f32", Int32Regs, Float32Regs>;
-defm TEX_1D_U32_S32 : TEX_1D<"tex.1d.v4.u32.s32", Int32Regs, Int32Regs>;
-defm TEX_1D_U32_F32 : TEX_1D<"tex.1d.v4.u32.f32", Int32Regs, Float32Regs>;
+defm TEX_1D_F32_S32 : TEX_1D<"tex.1d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_1d_v4f32_s32>;
+defm TEX_1D_F32_F32 : TEX_1D<"tex.1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_1d_v4f32_f32>;
+defm TEX_1D_S32_S32 : TEX_1D<"tex.1d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_1d_v4s32_s32>;
+defm TEX_1D_S32_F32 : TEX_1D<"tex.1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_v4s32_f32>;
+defm TEX_1D_U32_S32 : TEX_1D<"tex.1d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_1d_v4u32_s32>;
+defm TEX_1D_U32_F32 : TEX_1D<"tex.1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_v4u32_f32>;
class TEX_1D_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_1D_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_1D_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$lod))]>;
def _RI : TEX_1D_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_1D_LEVEL_base<inst, outtype, intype,
@@ -2994,25 +3006,31 @@ multiclass TEX_1D_LEVEL<string inst, NVPTXRegClass outtype,
}
defm TEX_1D_F32_F32_LEVEL :
- TEX_1D_LEVEL<"tex.level.1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ TEX_1D_LEVEL<"tex.level.1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_1d_level_v4f32_f32>;
defm TEX_1D_S32_F32_LEVEL :
- TEX_1D_LEVEL<"tex.level.1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ TEX_1D_LEVEL<"tex.level.1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_level_v4s32_f32>;
defm TEX_1D_U32_F32_LEVEL :
- TEX_1D_LEVEL<"tex.level.1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ TEX_1D_LEVEL<"tex.level.1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_level_v4u32_f32>;
class TEX_1D_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$gradx, intype:$grady)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x\\}],"
" \\{$gradx\\}, \\{$grady\\};",
- []>;
+ pattern>;
multiclass TEX_1D_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_1D_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$gradx, intype:$grady))]>;
def _RI : TEX_1D_GRAD_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_1D_GRAD_base<inst, outtype, intype,
@@ -3022,24 +3040,30 @@ multiclass TEX_1D_GRAD<string inst, NVPTXRegClass outtype,
}
defm TEX_1D_F32_F32_GRAD
- : TEX_1D_GRAD<"tex.grad.1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_1D_GRAD<"tex.grad.1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_1d_grad_v4f32_f32>;
defm TEX_1D_S32_F32_GRAD
- : TEX_1D_GRAD<"tex.grad.1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_GRAD<"tex.grad.1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_grad_v4s32_f32>;
defm TEX_1D_U32_F32_GRAD
- : TEX_1D_GRAD<"tex.grad.1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_GRAD<"tex.grad.1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_grad_v4u32_f32>;
class TEX_1D_ARRAY_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$l, $x\\}];",
- []>;
+ pattern>;
multiclass TEX_1D_ARRAY<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_1D_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x))]>;
def _RI : TEX_1D_ARRAY_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_1D_ARRAY_base<inst, outtype, intype,
@@ -3049,31 +3073,40 @@ multiclass TEX_1D_ARRAY<string inst, NVPTXRegClass outtype,
}
defm TEX_1D_ARRAY_F32_F32
- : TEX_1D_ARRAY<"tex.a1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_1D_ARRAY<"tex.a1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_v4f32_f32>;
defm TEX_1D_ARRAY_F32_S32
- : TEX_1D_ARRAY<"tex.a1d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_1D_ARRAY<"tex.a1d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_1d_array_v4f32_s32>;
defm TEX_1D_ARRAY_S32_S32
- : TEX_1D_ARRAY<"tex.a1d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_1D_ARRAY<"tex.a1d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_1d_array_v4s32_s32>;
defm TEX_1D_ARRAY_S32_F32
- : TEX_1D_ARRAY<"tex.a1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_ARRAY<"tex.a1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_v4s32_f32>;
defm TEX_1D_ARRAY_U32_S32
- : TEX_1D_ARRAY<"tex.a1d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_1D_ARRAY<"tex.a1d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_1d_array_v4u32_s32>;
defm TEX_1D_ARRAY_U32_F32
- : TEX_1D_ARRAY<"tex.a1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_ARRAY<"tex.a1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_v4u32_f32>;
class TEX_1D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$l, $x\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_1D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_1D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$lod))]>;
def _RI : TEX_1D_ARRAY_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_1D_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -3083,26 +3116,33 @@ multiclass TEX_1D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
}
defm TEX_1D_ARRAY_F32_F32_LEVEL
- : TEX_1D_ARRAY_LEVEL<"tex.level.a1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_1D_ARRAY_LEVEL<"tex.level.a1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_level_v4f32_f32>;
defm TEX_1D_ARRAY_S32_F32_LEVEL
- : TEX_1D_ARRAY_LEVEL<"tex.level.a1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_ARRAY_LEVEL<"tex.level.a1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_level_v4s32_f32>;
defm TEX_1D_ARRAY_U32_F32_LEVEL
- : TEX_1D_ARRAY_LEVEL<"tex.level.a1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_ARRAY_LEVEL<"tex.level.a1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_level_v4u32_f32>;
class TEX_1D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x,
intype:$gradx, intype:$grady)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$l, $x\\}],"
" \\{$gradx\\}, \\{$grady\\};",
- []>;
+ pattern>;
multiclass TEX_1D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_1D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x,
+ intype:$gradx, intype:$grady))]>;
def _RI : TEX_1D_ARRAY_GRAD_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_1D_ARRAY_GRAD_base<inst, outtype, intype,
@@ -3112,48 +3152,63 @@ multiclass TEX_1D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
}
defm TEX_1D_ARRAY_F32_F32_GRAD
- : TEX_1D_ARRAY_GRAD<"tex.grad.a1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_1D_ARRAY_GRAD<"tex.grad.a1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_grad_v4f32_f32>;
defm TEX_1D_ARRAY_S32_F32_GRAD
- : TEX_1D_ARRAY_GRAD<"tex.grad.a1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_ARRAY_GRAD<"tex.grad.a1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_grad_v4s32_f32>;
defm TEX_1D_ARRAY_U32_F32_GRAD
- : TEX_1D_ARRAY_GRAD<"tex.grad.a1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_1D_ARRAY_GRAD<"tex.grad.a1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_1d_array_grad_v4u32_f32>;
class TEX_2D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x, $y\\}];",
- []>;
+ pattern>;
-multiclass TEX_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
+multiclass TEX_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
+ Intrinsic intr> {
def _RR : TEX_2D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y))]>;
def _RI : TEX_2D_base<inst, outtype, intype, (ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_2D_base<inst, outtype, intype, (ins i64imm:$t, Int64Regs:$s)>;
def _II : TEX_2D_base<inst, outtype, intype, (ins i64imm:$t, i64imm:$s)>;
}
-defm TEX_2D_F32_F32 : TEX_2D<"tex.2d.v4.f32.f32", Float32Regs, Float32Regs>;
-defm TEX_2D_F32_S32 : TEX_2D<"tex.2d.v4.f32.s32", Float32Regs, Int32Regs>;
-defm TEX_2D_S32_S32 : TEX_2D<"tex.2d.v4.s32.s32", Int32Regs, Int32Regs>;
-defm TEX_2D_S32_F32 : TEX_2D<"tex.2d.v4.s32.f32", Int32Regs, Float32Regs>;
-defm TEX_2D_U32_S32 : TEX_2D<"tex.2d.v4.u32.s32", Int32Regs, Int32Regs>;
-defm TEX_2D_U32_F32 : TEX_2D<"tex.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+defm TEX_2D_F32_F32 : TEX_2D<"tex.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_2d_v4f32_f32>;
+defm TEX_2D_F32_S32 : TEX_2D<"tex.2d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_2d_v4f32_s32>;
+defm TEX_2D_S32_S32 : TEX_2D<"tex.2d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_2d_v4s32_s32>;
+defm TEX_2D_S32_F32 : TEX_2D<"tex.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_v4s32_f32>;
+defm TEX_2D_U32_S32 : TEX_2D<"tex.2d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_2d_v4u32_s32>;
+defm TEX_2D_U32_F32 : TEX_2D<"tex.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_v4u32_f32>;
class TEX_2D_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$x, $y\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_2D_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_2D_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$lod))]>;
def _RI : TEX_2D_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_2D_LEVEL_base<inst, outtype, intype,
@@ -3163,14 +3218,18 @@ multiclass TEX_2D_LEVEL<string inst, NVPTXRegClass outtype,
}
defm TEX_2D_F32_F32_LEVEL :
- TEX_2D_LEVEL<"tex.level.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ TEX_2D_LEVEL<"tex.level.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_2d_level_v4f32_f32>;
defm TEX_2D_S32_F32_LEVEL :
- TEX_2D_LEVEL<"tex.level.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ TEX_2D_LEVEL<"tex.level.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_level_v4s32_f32>;
defm TEX_2D_U32_F32_LEVEL :
- TEX_2D_LEVEL<"tex.level.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ TEX_2D_LEVEL<"tex.level.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_level_v4u32_f32>;
class TEX_2D_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y,
@@ -3178,12 +3237,16 @@ class TEX_2D_GRAD_base<string inst, NVPTXRegClass outtype,
intype:$grady0, intype:$grady1)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, $s, \\{$x, $y\\}],"
" \\{$gradx0, $gradx1\\}, \\{$grady0, $grady1\\};",
- []>;
+ pattern>;
multiclass TEX_2D_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_2D_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y,
+ intype:$gradx0, intype:$gradx1,
+ intype:$grady0, intype:$grady1))]>;
def _RI : TEX_2D_GRAD_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_2D_GRAD_base<inst, outtype, intype,
@@ -3193,25 +3256,31 @@ multiclass TEX_2D_GRAD<string inst, NVPTXRegClass outtype,
}
defm TEX_2D_F32_F32_GRAD :
- TEX_2D_GRAD<"tex.grad.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ TEX_2D_GRAD<"tex.grad.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_2d_grad_v4f32_f32>;
defm TEX_2D_S32_F32_GRAD :
- TEX_2D_GRAD<"tex.grad.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ TEX_2D_GRAD<"tex.grad.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_grad_v4s32_f32>;
defm TEX_2D_U32_F32_GRAD :
- TEX_2D_GRAD<"tex.grad.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ TEX_2D_GRAD<"tex.grad.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_grad_v4u32_f32>;
class TEX_2D_ARRAY_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x, intype:$y)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$l, $x, $y, $y\\}];",
- []>;
+ pattern>;
multiclass TEX_2D_ARRAY<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_2D_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y))]>;
def _RI : TEX_2D_ARRAY_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_2D_ARRAY_base<inst, outtype, intype,
@@ -3221,32 +3290,41 @@ multiclass TEX_2D_ARRAY<string inst, NVPTXRegClass outtype,
}
defm TEX_2D_ARRAY_F32_F32
- : TEX_2D_ARRAY<"tex.a2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_2D_ARRAY<"tex.a2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_v4f32_f32>;
defm TEX_2D_ARRAY_F32_S32
- : TEX_2D_ARRAY<"tex.a2d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_2D_ARRAY<"tex.a2d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_2d_array_v4f32_s32>;
defm TEX_2D_ARRAY_S32_S32
- : TEX_2D_ARRAY<"tex.a2d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_2D_ARRAY<"tex.a2d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_2d_array_v4s32_s32>;
defm TEX_2D_ARRAY_S32_F32
- : TEX_2D_ARRAY<"tex.a2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_2D_ARRAY<"tex.a2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_v4s32_f32>;
defm TEX_2D_ARRAY_U32_S32
- : TEX_2D_ARRAY<"tex.a2d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_2D_ARRAY<"tex.a2d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_2d_array_v4u32_s32>;
defm TEX_2D_ARRAY_U32_F32
- : TEX_2D_ARRAY<"tex.a2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_2D_ARRAY<"tex.a2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_v4u32_f32>;
class TEX_2D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x, intype:$y,
intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$l, $x, $y, $y\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_2D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_2D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y, intype:$lod))]>;
def _RI : TEX_2D_ARRAY_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_2D_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -3256,14 +3334,18 @@ multiclass TEX_2D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
}
defm TEX_2D_ARRAY_F32_F32_LEVEL
- : TEX_2D_ARRAY_LEVEL<"tex.level.a2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_2D_ARRAY_LEVEL<"tex.level.a2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_level_v4f32_f32>;
defm TEX_2D_ARRAY_S32_F32_LEVEL
- : TEX_2D_ARRAY_LEVEL<"tex.level.a2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_2D_ARRAY_LEVEL<"tex.level.a2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_level_v4s32_f32>;
defm TEX_2D_ARRAY_U32_F32_LEVEL
- : TEX_2D_ARRAY_LEVEL<"tex.level.a2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_2D_ARRAY_LEVEL<"tex.level.a2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_level_v4u32_f32>;
class TEX_2D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x, intype:$y,
@@ -3272,12 +3354,16 @@ class TEX_2D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$l, $x, $y, $y\\}],"
" \\{$gradx0, $gradx1\\}, \\{$grady0, $grady1\\};",
- []>;
+ pattern>;
multiclass TEX_2D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_2D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y,
+ intype:$gradx0, intype:$gradx1,
+ intype:$grady0, intype:$grady1))]>;
def _RI : TEX_2D_ARRAY_GRAD_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_2D_ARRAY_GRAD_base<inst, outtype, intype,
@@ -3287,24 +3373,30 @@ multiclass TEX_2D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
}
defm TEX_2D_ARRAY_F32_F32_GRAD
- : TEX_2D_ARRAY_GRAD<"tex.grad.a2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_2D_ARRAY_GRAD<"tex.grad.a2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_grad_v4f32_f32>;
defm TEX_2D_ARRAY_S32_F32_GRAD
- : TEX_2D_ARRAY_GRAD<"tex.grad.a2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_2D_ARRAY_GRAD<"tex.grad.a2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_grad_v4s32_f32>;
defm TEX_2D_ARRAY_U32_F32_GRAD
- : TEX_2D_ARRAY_GRAD<"tex.grad.a2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_2D_ARRAY_GRAD<"tex.grad.a2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_2d_array_grad_v4u32_f32>;
class TEX_3D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y, intype:$z)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
-multiclass TEX_3D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
+multiclass TEX_3D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
+ Intrinsic intr> {
def _RR : TEX_3D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z))]>;
def _RI : TEX_3D_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_3D_base<inst, outtype, intype,
@@ -3313,27 +3405,37 @@ multiclass TEX_3D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
(ins i64imm:$t, i64imm:$s)>;
}
-defm TEX_3D_F32_F32 : TEX_3D<"tex.3d.v4.f32.f32", Float32Regs, Float32Regs>;
-defm TEX_3D_F32_S32 : TEX_3D<"tex.3d.v4.f32.s32", Float32Regs, Int32Regs>;
-defm TEX_3D_S32_S32 : TEX_3D<"tex.3d.v4.s32.s32", Int32Regs, Int32Regs>;
-defm TEX_3D_S32_F32 : TEX_3D<"tex.3d.v4.s32.f32", Int32Regs, Float32Regs>;
-defm TEX_3D_U32_S32 : TEX_3D<"tex.3d.v4.u32.s32", Int32Regs, Int32Regs>;
-defm TEX_3D_U32_F32 : TEX_3D<"tex.3d.v4.u32.f32", Int32Regs, Float32Regs>;
+defm TEX_3D_F32_F32 : TEX_3D<"tex.3d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_3d_v4f32_f32>;
+defm TEX_3D_F32_S32 : TEX_3D<"tex.3d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_3d_v4f32_s32>;
+defm TEX_3D_S32_S32 : TEX_3D<"tex.3d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_3d_v4s32_s32>;
+defm TEX_3D_S32_F32 : TEX_3D<"tex.3d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_3d_v4s32_f32>;
+defm TEX_3D_U32_S32 : TEX_3D<"tex.3d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_3d_v4u32_s32>;
+defm TEX_3D_U32_F32 : TEX_3D<"tex.3d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_3d_v4u32_f32>;
class TEX_3D_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y, intype:$z,
intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$x, $y, $z, $z\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_3D_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_3D_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z,
+ intype:$lod))]>;
def _RI : TEX_3D_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_3D_LEVEL_base<inst, outtype, intype,
@@ -3343,14 +3445,18 @@ multiclass TEX_3D_LEVEL<string inst, NVPTXRegClass outtype,
}
defm TEX_3D_F32_F32_LEVEL
- : TEX_3D_LEVEL<"tex.level.3d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_3D_LEVEL<"tex.level.3d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_3d_level_v4f32_f32>;
defm TEX_3D_S32_F32_LEVEL
- : TEX_3D_LEVEL<"tex.level.3d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_3D_LEVEL<"tex.level.3d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_3d_level_v4s32_f32>;
defm TEX_3D_U32_F32_LEVEL
- : TEX_3D_LEVEL<"tex.level.3d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_3D_LEVEL<"tex.level.3d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_3d_level_v4u32_f32>;
class TEX_3D_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y, intype:$z,
@@ -3361,12 +3467,16 @@ class TEX_3D_GRAD_base<string inst, NVPTXRegClass outtype,
" [$t, $s, \\{$x, $y, $z, $z\\}],"
" \\{$gradx0, $gradx1, $gradx2, $gradx2\\},"
" \\{$grady0, $grady1, $grady2, $grady2\\};",
- []>;
+ pattern>;
multiclass TEX_3D_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_3D_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z,
+ intype:$gradx0, intype:$gradx1, intype:$gradx2,
+ intype:$grady0, intype:$grady1, intype:$grady2))]>;
def _RI : TEX_3D_GRAD_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_3D_GRAD_base<inst, outtype, intype,
@@ -3376,24 +3486,30 @@ multiclass TEX_3D_GRAD<string inst, NVPTXRegClass outtype,
}
defm TEX_3D_F32_F32_GRAD
- : TEX_3D_GRAD<"tex.grad.3d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_3D_GRAD<"tex.grad.3d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_3d_grad_v4f32_f32>;
defm TEX_3D_S32_F32_GRAD
- : TEX_3D_GRAD<"tex.grad.3d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_3D_GRAD<"tex.grad.3d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_3d_grad_v4s32_f32>;
defm TEX_3D_U32_F32_GRAD
- : TEX_3D_GRAD<"tex.grad.3d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_3D_GRAD<"tex.grad.3d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_3d_grad_v4u32_f32>;
class TEX_CUBE_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y, intype:$z)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
-multiclass TEX_CUBE<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
+multiclass TEX_CUBE<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
+ Intrinsic intr> {
def _RR : TEX_CUBE_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z))]>;
def _RI : TEX_CUBE_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_CUBE_base<inst, outtype, intype,
@@ -3403,26 +3519,33 @@ multiclass TEX_CUBE<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
}
defm TEX_CUBE_F32_F32
- : TEX_CUBE<"tex.cube.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_CUBE<"tex.cube.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_cube_v4f32_f32>;
defm TEX_CUBE_S32_F32
- : TEX_CUBE<"tex.cube.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_CUBE<"tex.cube.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_v4s32_f32>;
defm TEX_CUBE_U32_F32
- : TEX_CUBE<"tex.cube.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_CUBE<"tex.cube.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_v4u32_f32>;
class TEX_CUBE_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins intype:$x, intype:$y, intype:$z,
intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$x, $y, $z, $z\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_CUBE_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_CUBE_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z,
+ intype:$lod))]>;
def _RI : TEX_CUBE_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_CUBE_LEVEL_base<inst, outtype, intype,
@@ -3432,26 +3555,32 @@ multiclass TEX_CUBE_LEVEL<string inst, NVPTXRegClass outtype,
}
defm TEX_CUBE_F32_F32_LEVEL
- : TEX_CUBE_LEVEL<"tex.level.cube.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_CUBE_LEVEL<"tex.level.cube.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_cube_level_v4f32_f32>;
defm TEX_CUBE_S32_F32_LEVEL
- : TEX_CUBE_LEVEL<"tex.level.cube.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_CUBE_LEVEL<"tex.level.cube.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_level_v4s32_f32>;
defm TEX_CUBE_U32_F32_LEVEL
- : TEX_CUBE_LEVEL<"tex.level.cube.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_CUBE_LEVEL<"tex.level.cube.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_level_v4u32_f32>;
class TEX_CUBE_ARRAY_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x, intype:$y,
intype:$z)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$l, $x, $y, $z\\}];",
- []>;
+ pattern>;
multiclass TEX_CUBE_ARRAY<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_CUBE_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y, intype:$z))]>;
def _RI : TEX_CUBE_ARRAY_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_CUBE_ARRAY_base<inst, outtype, intype,
@@ -3461,26 +3590,33 @@ multiclass TEX_CUBE_ARRAY<string inst, NVPTXRegClass outtype,
}
defm TEX_CUBE_ARRAY_F32_F32
- : TEX_CUBE_ARRAY<"tex.acube.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_CUBE_ARRAY<"tex.acube.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_cube_array_v4f32_f32>;
defm TEX_CUBE_ARRAY_S32_F32
- : TEX_CUBE_ARRAY<"tex.acube.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_CUBE_ARRAY<"tex.acube.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_array_v4s32_f32>;
defm TEX_CUBE_ARRAY_U32_F32
- : TEX_CUBE_ARRAY<"tex.acube.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_CUBE_ARRAY<"tex.acube.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_array_v4u32_f32>;
class TEX_CUBE_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(texsamp, (ins Int32Regs:$l, intype:$x, intype:$y,
intype:$z, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, $s, \\{$l, $x, $y, $z\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_CUBE_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _RR : TEX_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y, intype:$z,
+ intype:$lod))]>;
def _RI : TEX_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TEX_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -3491,25 +3627,31 @@ multiclass TEX_CUBE_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
defm TEX_CUBE_ARRAY_F32_F32_LEVEL
: TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_cube_array_level_v4f32_f32>;
defm TEX_CUBE_ARRAY_S32_F32_LEVEL
: TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_array_level_v4s32_f32>;
defm TEX_CUBE_ARRAY_U32_F32_LEVEL
: TEX_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_cube_array_level_v4u32_f32>;
class TLD4_2D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag texsamp>
+ NVPTXRegClass intype, dag texsamp, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$v0, outtype:$v1,
outtype:$v2, outtype:$v3),
!con(texsamp, (ins intype:$x, intype:$y)),
inst # " \t\\{$v0, $v1, $v2, $v3\\}, [$t, $s, \\{$x, $y\\}];",
- []>;
+ pattern>;
-multiclass TLD4_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
+multiclass TLD4_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
+ Intrinsic intr> {
def _RR : TLD4_2D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s)>;
+ (ins Int64Regs:$t, Int64Regs:$s),
+ [(set outtype:$v0, outtype:$v1, outtype:$v2, outtype:$v3,
+ (intr i64:$t, i64:$s, intype:$x, intype:$y))]>;
def _RI : TLD4_2D_base<inst, outtype, intype,
(ins Int64Regs:$t, i64imm:$s)>;
def _IR : TLD4_2D_base<inst, outtype, intype,
@@ -3519,31 +3661,43 @@ multiclass TLD4_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype> {
}
defm TLD4_R_2D_F32_F32
- : TLD4_2D<"tld4.r.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.r.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_r_2d_v4f32_f32>;
defm TLD4_G_2D_F32_F32
- : TLD4_2D<"tld4.g.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.g.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_g_2d_v4f32_f32>;
defm TLD4_B_2D_F32_F32
- : TLD4_2D<"tld4.b.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.b.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_b_2d_v4f32_f32>;
defm TLD4_A_2D_F32_F32
- : TLD4_2D<"tld4.a.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.a.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_a_2d_v4f32_f32>;
defm TLD4_R_2D_S32_F32
- : TLD4_2D<"tld4.r.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.r.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_r_2d_v4s32_f32>;
defm TLD4_G_2D_S32_F32
- : TLD4_2D<"tld4.g.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.g.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_g_2d_v4s32_f32>;
defm TLD4_B_2D_S32_F32
- : TLD4_2D<"tld4.b.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.b.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_b_2d_v4s32_f32>;
defm TLD4_A_2D_S32_F32
- : TLD4_2D<"tld4.a.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.a.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_a_2d_v4s32_f32>;
defm TLD4_R_2D_U32_F32
- : TLD4_2D<"tld4.r.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.r.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_r_2d_v4u32_f32>;
defm TLD4_G_2D_U32_F32
- : TLD4_2D<"tld4.g.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.g.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_g_2d_v4u32_f32>;
defm TLD4_B_2D_U32_F32
- : TLD4_2D<"tld4.b.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.b.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_b_2d_v4u32_f32>;
defm TLD4_A_2D_U32_F32
- : TLD4_2D<"tld4.a.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_2D<"tld4.a.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_a_2d_v4u32_f32>;
}
@@ -3553,206 +3707,262 @@ let IsTex = true, IsTexModeUnified = true in {
// Texture fetch instructions using handles
class TEX_UNIFIED_1D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_1D<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_1D_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_1D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x))]>;
def _I : TEX_UNIFIED_1D_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_1D_F32_S32
- : TEX_UNIFIED_1D<"tex.1d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_UNIFIED_1D<"tex.1d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_unified_1d_v4f32_s32>;
defm TEX_UNIFIED_1D_F32_F32
- : TEX_UNIFIED_1D<"tex.1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D<"tex.1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_v4f32_f32>;
defm TEX_UNIFIED_1D_S32_S32
- : TEX_UNIFIED_1D<"tex.1d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_1D<"tex.1d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_1d_v4s32_s32>;
defm TEX_UNIFIED_1D_S32_F32
- : TEX_UNIFIED_1D<"tex.1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D<"tex.1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_v4s32_f32>;
defm TEX_UNIFIED_1D_U32_S32
- : TEX_UNIFIED_1D<"tex.1d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_1D<"tex.1d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_1d_v4u32_s32>;
defm TEX_UNIFIED_1D_U32_F32
- : TEX_UNIFIED_1D<"tex.1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D<"tex.1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_v4u32_f32>;
class TEX_UNIFIED_1D_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_1D_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_1D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_1D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$lod))]>;
def _I : TEX_UNIFIED_1D_LEVEL_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_1D_F32_F32_LEVEL
- : TEX_UNIFIED_1D_LEVEL<"tex.level.1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_LEVEL<"tex.level.1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_level_v4f32_f32>;
defm TEX_UNIFIED_1D_S32_F32_LEVEL
- : TEX_UNIFIED_1D_LEVEL<"tex.level.1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_LEVEL<"tex.level.1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_level_v4s32_f32>;
defm TEX_UNIFIED_1D_U32_F32_LEVEL
- : TEX_UNIFIED_1D_LEVEL<"tex.level.1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_LEVEL<"tex.level.1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_level_v4u32_f32>;
class TEX_UNIFIED_1D_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$gradx, intype:$grady)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, \\{$x\\}], \\{$gradx\\}, \\{$grady\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_1D_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_1D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_1D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$gradx, intype:$grady))]>;
def _I : TEX_UNIFIED_1D_GRAD_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_1D_F32_F32_GRAD
- : TEX_UNIFIED_1D_GRAD<"tex.grad.1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_GRAD<"tex.grad.1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_grad_v4f32_f32>;
defm TEX_UNIFIED_1D_S32_F32_GRAD
- : TEX_UNIFIED_1D_GRAD<"tex.grad.1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_GRAD<"tex.grad.1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_grad_v4s32_f32>;
defm TEX_UNIFIED_1D_U32_F32_GRAD
- : TEX_UNIFIED_1D_GRAD<"tex.grad.1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_GRAD<"tex.grad.1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_grad_v4u32_f32>;
class TEX_UNIFIED_1D_ARRAY_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_1D_ARRAY<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_1D_ARRAY_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_1D_ARRAY_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x))]>;
def _I : TEX_UNIFIED_1D_ARRAY_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_1D_ARRAY_F32_S32
- : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_unified_1d_array_v4f32_s32>;
defm TEX_UNIFIED_1D_ARRAY_F32_F32
- : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_v4f32_f32>;
defm TEX_UNIFIED_1D_ARRAY_S32_S32
- : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_1d_array_v4s32_s32>;
defm TEX_UNIFIED_1D_ARRAY_S32_F32
- : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_v4s32_f32>;
defm TEX_UNIFIED_1D_ARRAY_U32_S32
- : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_1d_array_v4u32_s32>;
defm TEX_UNIFIED_1D_ARRAY_U32_F32
- : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_1D_ARRAY<"tex.a1d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_v4u32_f32>;
class TEX_UNIFIED_1D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_1D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_1D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$lod))]>;
def _I : TEX_UNIFIED_1D_ARRAY_LEVEL_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL
: TEX_UNIFIED_1D_ARRAY_LEVEL<"tex.level.a1d.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_level_v4f32_f32>;
defm TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL
: TEX_UNIFIED_1D_ARRAY_LEVEL<"tex.level.a1d.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_level_v4s32_f32>;
defm TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL
: TEX_UNIFIED_1D_ARRAY_LEVEL<"tex.level.a1d.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_level_v4u32_f32>;
class TEX_UNIFIED_1D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x,
intype:$gradx, intype:$grady)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, \\{$l, $x\\}], \\{$gradx\\}, \\{$grady\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_1D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_1D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$gradx, intype:$grady))]>;
def _I : TEX_UNIFIED_1D_ARRAY_GRAD_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD
: TEX_UNIFIED_1D_ARRAY_GRAD<"tex.grad.a1d.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_grad_v4f32_f32>;
defm TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD
: TEX_UNIFIED_1D_ARRAY_GRAD<"tex.grad.a1d.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_grad_v4s32_f32>;
defm TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD
: TEX_UNIFIED_1D_ARRAY_GRAD<"tex.grad.a1d.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_1d_array_grad_v4u32_f32>;
class TEX_UNIFIED_2D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_2D<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_2D_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_2D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y))]>;
def _I : TEX_UNIFIED_2D_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_2D_F32_S32
- : TEX_UNIFIED_2D<"tex.2d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_UNIFIED_2D<"tex.2d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_unified_2d_v4f32_s32>;
defm TEX_UNIFIED_2D_F32_F32
- : TEX_UNIFIED_2D<"tex.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D<"tex.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_v4f32_f32>;
defm TEX_UNIFIED_2D_S32_S32
- : TEX_UNIFIED_2D<"tex.2d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_2D<"tex.2d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_2d_v4s32_s32>;
defm TEX_UNIFIED_2D_S32_F32
- : TEX_UNIFIED_2D<"tex.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D<"tex.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_v4s32_f32>;
defm TEX_UNIFIED_2D_U32_S32
- : TEX_UNIFIED_2D<"tex.2d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_2D<"tex.2d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_2d_v4u32_s32>;
defm TEX_UNIFIED_2D_U32_F32
- : TEX_UNIFIED_2D<"tex.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D<"tex.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_v4u32_f32>;
class TEX_UNIFIED_2D_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_2D_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_2D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_2D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$lod))]>;
def _I : TEX_UNIFIED_2D_LEVEL_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_2D_F32_F32_LEVEL
- : TEX_UNIFIED_2D_LEVEL<"tex.level.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_LEVEL<"tex.level.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_level_v4f32_f32>;
defm TEX_UNIFIED_2D_S32_F32_LEVEL
- : TEX_UNIFIED_2D_LEVEL<"tex.level.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_LEVEL<"tex.level.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_level_v4s32_f32>;
defm TEX_UNIFIED_2D_U32_F32_LEVEL
- : TEX_UNIFIED_2D_LEVEL<"tex.level.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_LEVEL<"tex.level.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_level_v4u32_f32>;
class TEX_UNIFIED_2D_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y,
@@ -3760,75 +3970,98 @@ class TEX_UNIFIED_2D_GRAD_base<string inst, NVPTXRegClass outtype,
intype:$grady0, intype:$grady1)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y\\}],"
" \\{$gradx0, $gradx1\\}, \\{$grady0, $grady1\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_2D_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_2D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_2D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y,
+ intype:$gradx0, intype:$gradx1,
+ intype:$grady0, intype:$grady1))]>;
def _I : TEX_UNIFIED_2D_GRAD_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_2D_F32_F32_GRAD
- : TEX_UNIFIED_2D_GRAD<"tex.grad.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_GRAD<"tex.grad.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_grad_v4f32_f32>;
defm TEX_UNIFIED_2D_S32_F32_GRAD
- : TEX_UNIFIED_2D_GRAD<"tex.grad.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_GRAD<"tex.grad.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_grad_v4s32_f32>;
defm TEX_UNIFIED_2D_U32_F32_GRAD
- : TEX_UNIFIED_2D_GRAD<"tex.grad.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_GRAD<"tex.grad.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_grad_v4u32_f32>;
class TEX_UNIFIED_2D_ARRAY_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$y)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x, $y, $y\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_2D_ARRAY<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_2D_ARRAY_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_2D_ARRAY_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$y))]>;
def _I : TEX_UNIFIED_2D_ARRAY_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_2D_ARRAY_F32_S32
- : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_unified_2d_array_v4f32_s32>;
defm TEX_UNIFIED_2D_ARRAY_F32_F32
- : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_v4f32_f32>;
defm TEX_UNIFIED_2D_ARRAY_S32_S32
- : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_2d_array_v4s32_s32>;
defm TEX_UNIFIED_2D_ARRAY_S32_F32
- : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_v4s32_f32>;
defm TEX_UNIFIED_2D_ARRAY_U32_S32
- : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_2d_array_v4u32_s32>;
defm TEX_UNIFIED_2D_ARRAY_U32_F32
- : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_2D_ARRAY<"tex.a2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_v4u32_f32>;
class TEX_UNIFIED_2D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$y,
intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, \\{$l, $x, $y, $y\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_2D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_2D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$lod))]>;
def _I : TEX_UNIFIED_2D_ARRAY_LEVEL_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL
: TEX_UNIFIED_2D_ARRAY_LEVEL<"tex.level.a2d.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_level_v4f32_f32>;
defm TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL
: TEX_UNIFIED_2D_ARRAY_LEVEL<"tex.level.a2d.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_level_v4s32_f32>;
defm TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL
: TEX_UNIFIED_2D_ARRAY_LEVEL<"tex.level.a2d.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_level_v4u32_f32>;
class TEX_UNIFIED_2D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$y,
@@ -3836,74 +4069,96 @@ class TEX_UNIFIED_2D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
intype:$grady0, intype:$grady1)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x, $y, $y\\}],"
" \\{$gradx0, $gradx1\\}, \\{$grady0, $grady1\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_2D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_2D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$y,
+ intype:$gradx0, intype:$gradx1,
+ intype:$grady0, intype:$grady1))]>;
def _I : TEX_UNIFIED_2D_ARRAY_GRAD_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD
: TEX_UNIFIED_2D_ARRAY_GRAD<"tex.grad.a2d.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_grad_v4f32_f32>;
defm TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD
: TEX_UNIFIED_2D_ARRAY_GRAD<"tex.grad.a2d.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_grad_v4s32_f32>;
defm TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD
: TEX_UNIFIED_2D_ARRAY_GRAD<"tex.grad.a2d.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_2d_array_grad_v4u32_f32>;
class TEX_UNIFIED_3D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex, list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$z)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_3D<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_3D_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_3D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$z))]>;
def _I : TEX_UNIFIED_3D_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_3D_F32_S32
- : TEX_UNIFIED_3D<"tex.3d.v4.f32.s32", Float32Regs, Int32Regs>;
+ : TEX_UNIFIED_3D<"tex.3d.v4.f32.s32", Float32Regs, Int32Regs,
+ int_nvvm_tex_unified_3d_v4f32_s32>;
defm TEX_UNIFIED_3D_F32_F32
- : TEX_UNIFIED_3D<"tex.3d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D<"tex.3d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_v4f32_f32>;
defm TEX_UNIFIED_3D_S32_S32
- : TEX_UNIFIED_3D<"tex.3d.v4.s32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_3D<"tex.3d.v4.s32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_3d_v4s32_s32>;
defm TEX_UNIFIED_3D_S32_F32
- : TEX_UNIFIED_3D<"tex.3d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D<"tex.3d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_v4s32_f32>;
defm TEX_UNIFIED_3D_U32_S32
- : TEX_UNIFIED_3D<"tex.3d.v4.u32.s32", Int32Regs, Int32Regs>;
+ : TEX_UNIFIED_3D<"tex.3d.v4.u32.s32", Int32Regs, Int32Regs,
+ int_nvvm_tex_unified_3d_v4u32_s32>;
defm TEX_UNIFIED_3D_U32_F32
- : TEX_UNIFIED_3D<"tex.3d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D<"tex.3d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_v4u32_f32>;
class TEX_UNIFIED_3D_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$z, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, \\{$x, $y, $z, $z\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_3D_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_3D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_3D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$z, intype:$lod))]>;
def _I : TEX_UNIFIED_3D_LEVEL_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_3D_F32_F32_LEVEL
- : TEX_UNIFIED_3D_LEVEL<"tex.level.3d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D_LEVEL<"tex.level.3d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_level_v4f32_f32>;
defm TEX_UNIFIED_3D_S32_F32_LEVEL
- : TEX_UNIFIED_3D_LEVEL<"tex.level.3d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D_LEVEL<"tex.level.3d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_level_v4s32_f32>;
defm TEX_UNIFIED_3D_U32_F32_LEVEL
- : TEX_UNIFIED_3D_LEVEL<"tex.level.3d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D_LEVEL<"tex.level.3d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_level_v4u32_f32>;
class TEX_UNIFIED_3D_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$z,
@@ -3913,117 +4168,149 @@ class TEX_UNIFIED_3D_GRAD_base<string inst, NVPTXRegClass outtype,
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y, $z, $z\\}],"
" \\{$gradx0, $gradx1, $gradx2, $gradx2\\},"
" \\{$grady0, $grady1, $grady2, $grady2\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_3D_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_3D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_3D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$z,
+ intype:$gradx0, intype:$gradx1, intype:$gradx2,
+ intype:$grady0, intype:$grady1, intype:$grady2))]>;
def _I : TEX_UNIFIED_3D_GRAD_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_3D_F32_F32_GRAD
- : TEX_UNIFIED_3D_GRAD<"tex.grad.3d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D_GRAD<"tex.grad.3d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_grad_v4f32_f32>;
defm TEX_UNIFIED_3D_S32_F32_GRAD
- : TEX_UNIFIED_3D_GRAD<"tex.grad.3d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D_GRAD<"tex.grad.3d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_grad_v4s32_f32>;
defm TEX_UNIFIED_3D_U32_F32_GRAD
- : TEX_UNIFIED_3D_GRAD<"tex.grad.3d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_3D_GRAD<"tex.grad.3d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_3d_grad_v4u32_f32>;
class TEX_UNIFIED_CUBE_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$z)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y, $z, $z\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_CUBE<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_CUBE_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_CUBE_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$z))]>;
def _I : TEX_UNIFIED_CUBE_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_CUBE_F32_F32
- : TEX_UNIFIED_CUBE<"tex.cube.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE<"tex.cube.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_v4f32_f32>;
defm TEX_UNIFIED_CUBE_S32_F32
- : TEX_UNIFIED_CUBE<"tex.cube.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE<"tex.cube.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_v4s32_f32>;
defm TEX_UNIFIED_CUBE_U32_F32
- : TEX_UNIFIED_CUBE<"tex.cube.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE<"tex.cube.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_v4u32_f32>;
class TEX_UNIFIED_CUBE_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$z, intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, \\{$x, $y, $z, $z\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_CUBE_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_CUBE_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$z, intype:$lod))]>;
def _I : TEX_UNIFIED_CUBE_LEVEL_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_CUBE_F32_F32_LEVEL
: TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_level_v4f32_f32>;
defm TEX_UNIFIED_CUBE_S32_F32_LEVEL
: TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_level_v4s32_f32>;
defm TEX_UNIFIED_CUBE_U32_F32_LEVEL
: TEX_UNIFIED_CUBE_LEVEL<"tex.level.cube.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_level_v4u32_f32>;
class TEX_UNIFIED_CUBE_ARRAY_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$y, intype:$z)),
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x, $y, $z\\}];",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_CUBE_ARRAY<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_CUBE_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$z))]>;
def _I : TEX_UNIFIED_CUBE_ARRAY_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_CUBE_ARRAY_F32_F32
- : TEX_UNIFIED_CUBE_ARRAY<"tex.acube.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE_ARRAY<"tex.acube.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_v4f32_f32>;
defm TEX_UNIFIED_CUBE_ARRAY_S32_F32
- : TEX_UNIFIED_CUBE_ARRAY<"tex.acube.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE_ARRAY<"tex.acube.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_v4s32_f32>;
defm TEX_UNIFIED_CUBE_ARRAY_U32_F32
- : TEX_UNIFIED_CUBE_ARRAY<"tex.acube.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE_ARRAY<"tex.acube.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_v4u32_f32>;
class TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$y, intype:$z,
intype:$lod)),
inst # " \t\\{$r, $g, $b, $a\\},"
" [$t, \\{$l, $x, $y, $z\\}], $lod;",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_CUBE_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$z, intype:$lod))]>;
def _I : TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL
: TEX_UNIFIED_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_level_v4f32_f32>;
defm TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL
: TEX_UNIFIED_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_level_v4s32_f32>;
defm TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL
: TEX_UNIFIED_CUBE_ARRAY_LEVEL<"tex.level.acube.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_level_v4u32_f32>;
class TEX_UNIFIED_CUBE_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins intype:$x, intype:$y, intype:$z,
@@ -4033,23 +4320,31 @@ class TEX_UNIFIED_CUBE_GRAD_base<string inst, NVPTXRegClass outtype,
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$x, $y, $z, $z\\}],"
" \\{$gradx0, $gradx1, $gradx2, $gradx2\\},"
" \\{$grady0, $grady1, $grady2, $grady2\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_CUBE_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TEX_UNIFIED_CUBE_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TEX_UNIFIED_CUBE_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, intype:$x, intype:$y, intype:$z,
+ intype:$gradx0, intype:$gradx1, intype:$gradx2,
+ intype:$grady0, intype:$grady1, intype:$grady2))]>;
def _I : TEX_UNIFIED_CUBE_GRAD_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TEX_UNIFIED_CUBE_F32_F32_GRAD
- : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_grad_v4f32_f32>;
defm TEX_UNIFIED_CUBE_S32_F32_GRAD
- : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_grad_v4s32_f32>;
defm TEX_UNIFIED_CUBE_U32_F32_GRAD
- : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TEX_UNIFIED_CUBE_GRAD<"tex.grad.cube.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_grad_v4u32_f32>;
class TEX_UNIFIED_CUBE_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$r, outtype:$g,
outtype:$b, outtype:$a),
!con(tex, (ins Int32Regs:$l, intype:$x, intype:$y, intype:$z,
@@ -4059,64 +4354,87 @@ class TEX_UNIFIED_CUBE_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
inst # " \t\\{$r, $g, $b, $a\\}, [$t, \\{$l, $x, $y, $z\\}],"
" \\{$gradx0, $gradx1, $gradx2, $gradx2\\},"
" \\{$grady0, $grady1, $grady2, $grady2\\};",
- []>;
+ pattern>;
multiclass TEX_UNIFIED_CUBE_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
+ NVPTXRegClass intype, Intrinsic intr> {
def _R : TEX_UNIFIED_CUBE_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t)>;
+ (ins Int64Regs:$t),
+ [(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
+ (intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$z,
+ intype:$gradx0, intype:$gradx1,
+ intype:$gradx2, intype:$grady0,
+ intype:$grady1, intype:$grady2))]>;
def _I : TEX_UNIFIED_CUBE_ARRAY_GRAD_base<inst, outtype, intype,
(ins i64imm:$t)>;
}
defm TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD
: TEX_UNIFIED_CUBE_ARRAY_GRAD<"tex.grad.acube.v4.f32.f32",
- Float32Regs, Float32Regs>;
+ Float32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_grad_v4f32_f32>;
defm TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD
: TEX_UNIFIED_CUBE_ARRAY_GRAD<"tex.grad.acube.v4.s32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_grad_v4s32_f32>;
defm TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD
: TEX_UNIFIED_CUBE_ARRAY_GRAD<"tex.grad.acube.v4.u32.f32",
- Int32Regs, Float32Regs>;
+ Int32Regs, Float32Regs,
+ int_nvvm_tex_unified_cube_array_grad_v4u32_f32>;
class TLD4_UNIFIED_2D_base<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype, dag tex>
+ NVPTXRegClass intype, dag tex,
+ list<dag> pattern = []>
: NVPTXInst<(outs outtype:$v0, outtype:$v1,
outtype:$v2, outtype:$v3),
!con(tex, (ins intype:$x, intype:$y)),
inst # " \t\\{$v0, $v1, $v2, $v3\\}, [$t, \\{$x, $y\\}];",
- []>;
+ pattern>;
multiclass TLD4_UNIFIED_2D<string inst, NVPTXRegClass outtype,
- NVPTXRegClass intype> {
- def _R : TLD4_UNIFIED_2D_base<inst, outtype, intype, (ins Int64Regs:$t)>;
+ NVPTXRegClass intype, Intrinsic intr> {
+ def _R : TLD4_UNIFIED_2D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ [(set outtype:$v0, outtype:$v1, outtype:$v2, outtype:$v3,
+ (intr i64:$t, intype:$x, intype:$y))]>;
def _I : TLD4_UNIFIED_2D_base<inst, outtype, intype, (ins i64imm:$t)>;
}
defm TLD4_UNIFIED_R_2D_F32_F32
- : TLD4_UNIFIED_2D<"tld4.r.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.r.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_unified_r_2d_v4f32_f32>;
defm TLD4_UNIFIED_G_2D_F32_F32
- : TLD4_UNIFIED_2D<"tld4.g.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.g.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_unified_g_2d_v4f32_f32>;
defm TLD4_UNIFIED_B_2D_F32_F32
- : TLD4_UNIFIED_2D<"tld4.b.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.b.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_unified_b_2d_v4f32_f32>;
defm TLD4_UNIFIED_A_2D_F32_F32
- : TLD4_UNIFIED_2D<"tld4.a.2d.v4.f32.f32", Float32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.a.2d.v4.f32.f32", Float32Regs, Float32Regs,
+ int_nvvm_tld4_unified_a_2d_v4f32_f32>;
defm TLD4_UNIFIED_R_2D_S32_F32
- : TLD4_UNIFIED_2D<"tld4.r.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.r.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_r_2d_v4s32_f32>;
defm TLD4_UNIFIED_G_2D_S32_F32
- : TLD4_UNIFIED_2D<"tld4.g.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.g.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_g_2d_v4s32_f32>;
defm TLD4_UNIFIED_B_2D_S32_F32
- : TLD4_UNIFIED_2D<"tld4.b.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.b.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_b_2d_v4s32_f32>;
defm TLD4_UNIFIED_A_2D_S32_F32
- : TLD4_UNIFIED_2D<"tld4.a.2d.v4.s32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.a.2d.v4.s32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_a_2d_v4s32_f32>;
defm TLD4_UNIFIED_R_2D_U32_F32
- : TLD4_UNIFIED_2D<"tld4.r.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.r.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_r_2d_v4u32_f32>;
defm TLD4_UNIFIED_G_2D_U32_F32
- : TLD4_UNIFIED_2D<"tld4.g.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.g.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_g_2d_v4u32_f32>;
defm TLD4_UNIFIED_B_2D_U32_F32
- : TLD4_UNIFIED_2D<"tld4.b.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.b.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_b_2d_v4u32_f32>;
defm TLD4_UNIFIED_A_2D_U32_F32
- : TLD4_UNIFIED_2D<"tld4.a.2d.v4.u32.f32", Int32Regs, Float32Regs>;
+ : TLD4_UNIFIED_2D<"tld4.a.2d.v4.u32.f32", Int32Regs, Float32Regs,
+ int_nvvm_tld4_unified_a_2d_v4u32_f32>;
}
@@ -7153,393 +7471,3 @@ defm INT_SET_MAXNREG_DEC : SET_MAXNREG<"dec", int_nvvm_setmaxnreg_dec_sync_align
} // isConvergent
def INT_EXIT : NVPTXInst<(outs), (ins), "exit;", [(int_nvvm_exit)]>;
-
-def : Pat<(int_nvvm_tex_1d_v4f32_s32 i64:$t, i64:$s, i32:$x),
- (TEX_1D_F32_S32_RR $t, $s, $x)>;
-def : Pat<(int_nvvm_tex_1d_v4f32_f32 i64:$t, i64:$s, f32:$x),
- (TEX_1D_F32_F32_RR $t, $s, $x)>;
-def : Pat<(int_nvvm_tex_1d_v4s32_s32 i64:$t, i64:$s, i32:$x),
- (TEX_1D_S32_S32_RR $t, $s, $x)>;
-def : Pat<(int_nvvm_tex_1d_v4s32_f32 i64:$t, i64:$s, f32:$x),
- (TEX_1D_S32_F32_RR $t, $s, $x)>;
-def : Pat<(int_nvvm_tex_1d_v4u32_s32 i64:$t, i64:$s, i32:$x),
- (TEX_1D_U32_S32_RR $t, $s, $x)>;
-def : Pat<(int_nvvm_tex_1d_v4u32_f32 i64:$t, i64:$s, f32:$x),
- (TEX_1D_U32_F32_RR $t, $s, $x)>;
-
-def : Pat<(int_nvvm_tex_1d_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$lod),
- (TEX_1D_F32_F32_LEVEL_RR $t, $s, $x, $lod)>;
-def : Pat<(int_nvvm_tex_1d_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$lod),
- (TEX_1D_S32_F32_LEVEL_RR $t, $s, $x, $lod)>;
-def : Pat<(int_nvvm_tex_1d_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$lod),
- (TEX_1D_U32_F32_LEVEL_RR $t, $s, $x, $lod)>;
-
-def : Pat<(int_nvvm_tex_1d_grad_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$gradx, f32:$grady),
- (TEX_1D_F32_F32_GRAD_RR $t, $s, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_1d_grad_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$gradx, f32:$grady),
- (TEX_1D_S32_F32_GRAD_RR $t, $s, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_1d_grad_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$gradx, f32:$grady),
- (TEX_1D_U32_F32_GRAD_RR $t, $s, $x, $gradx, $grady)>;
-
-def : Pat<(int_nvvm_tex_1d_array_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x),
- (TEX_1D_ARRAY_F32_F32_RR $t, $s, $l, $x)>;
-def : Pat<(int_nvvm_tex_1d_array_v4f32_s32 i64:$t, i64:$s, i32:$l, i32:$x),
- (TEX_1D_ARRAY_F32_S32_RR $t, $s, $l, $x)>;
-def : Pat<(int_nvvm_tex_1d_array_v4s32_s32 i64:$t, i64:$s, i32:$l, i32:$x),
- (TEX_1D_ARRAY_S32_S32_RR $t, $s, $l, $x)>;
-def : Pat<(int_nvvm_tex_1d_array_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x),
- (TEX_1D_ARRAY_S32_F32_RR $t, $s, $l, $x)>;
-def : Pat<(int_nvvm_tex_1d_array_v4u32_s32 i64:$t, i64:$s, i32:$l, i32:$x),
- (TEX_1D_ARRAY_U32_S32_RR $t, $s, $l, $x)>;
-def : Pat<(int_nvvm_tex_1d_array_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x),
- (TEX_1D_ARRAY_U32_F32_RR $t, $s, $l, $x)>;
-
-def : Pat<(int_nvvm_tex_1d_array_level_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$lod),
- (TEX_1D_ARRAY_F32_F32_LEVEL_RR $t, $s, $l, $x, $lod)>;
-def : Pat<(int_nvvm_tex_1d_array_level_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$lod),
- (TEX_1D_ARRAY_S32_F32_LEVEL_RR $t, $s, $l, $x, $lod)>;
-def : Pat<(int_nvvm_tex_1d_array_level_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$lod),
- (TEX_1D_ARRAY_U32_F32_LEVEL_RR $t, $s, $l, $x, $lod)>;
-
-def : Pat<(int_nvvm_tex_1d_array_grad_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$gradx, f32:$grady),
- (TEX_1D_ARRAY_F32_F32_GRAD_RR $t, $s, $l, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_1d_array_grad_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$gradx, f32:$grady),
- (TEX_1D_ARRAY_S32_F32_GRAD_RR $t, $s, $l, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_1d_array_grad_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$gradx, f32:$grady),
- (TEX_1D_ARRAY_U32_F32_GRAD_RR $t, $s, $l, $x, $gradx, $grady)>;
-
-def : Pat<(int_nvvm_tex_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TEX_2D_F32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_v4f32_s32 i64:$t, i64:$s, i32:$x, i32:$y),
- (TEX_2D_F32_S32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_v4s32_s32 i64:$t, i64:$s, i32:$x, i32:$y),
- (TEX_2D_S32_S32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TEX_2D_S32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_v4u32_s32 i64:$t, i64:$s, i32:$x, i32:$y),
- (TEX_2D_U32_S32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TEX_2D_U32_F32_RR $t, $s, $x, $y)>;
-
-def : Pat<(int_nvvm_tex_2d_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$lod),
- (TEX_2D_F32_F32_LEVEL_RR $t, $s, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_2d_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$lod),
- (TEX_2D_S32_F32_LEVEL_RR $t, $s, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_2d_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$lod),
- (TEX_2D_U32_F32_LEVEL_RR $t, $s, $x, $y, $lod)>;
-
-def : Pat<(int_nvvm_tex_2d_grad_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_2D_F32_F32_GRAD_RR $t, $s, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_2d_grad_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_2D_S32_F32_GRAD_RR $t, $s, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_2d_grad_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_2D_U32_F32_GRAD_RR $t, $s, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-
-def : Pat<(int_nvvm_tex_2d_array_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y),
- (TEX_2D_ARRAY_F32_F32_RR $t, $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_array_v4f32_s32 i64:$t, i64:$s, i32:$l, i32:$x, i32:$y),
- (TEX_2D_ARRAY_F32_S32_RR $t, $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_array_v4s32_s32 i64:$t, i64:$s, i32:$l, i32:$x, i32:$y),
- (TEX_2D_ARRAY_S32_S32_RR $t, $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_array_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y),
- (TEX_2D_ARRAY_S32_F32_RR $t, $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_array_v4u32_s32 i64:$t, i64:$s, i32:$l, i32:$x, i32:$y),
- (TEX_2D_ARRAY_U32_S32_RR $t, $s, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_2d_array_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y),
- (TEX_2D_ARRAY_U32_F32_RR $t, $s, $l, $x, $y)>;
-
-def : Pat<(int_nvvm_tex_2d_array_level_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$lod),
- (TEX_2D_ARRAY_F32_F32_LEVEL_RR $t, $s, $l, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_2d_array_level_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$lod),
- (TEX_2D_ARRAY_S32_F32_LEVEL_RR $t, $s, $l, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_2d_array_level_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$lod),
- (TEX_2D_ARRAY_U32_F32_LEVEL_RR $t, $s, $l, $x, $y, $lod)>;
-
-def : Pat<(int_nvvm_tex_2d_array_grad_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_2D_ARRAY_F32_F32_GRAD_RR $t, $s, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_2d_array_grad_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_2D_ARRAY_S32_F32_GRAD_RR $t, $s, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_2d_array_grad_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_2D_ARRAY_U32_F32_GRAD_RR $t, $s, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-
-def : Pat<(int_nvvm_tex_3d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
- (TEX_3D_F32_F32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_3d_v4f32_s32 i64:$t, i64:$s, i32:$x, i32:$y, i32:$z),
- (TEX_3D_F32_S32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_3d_v4s32_s32 i64:$t, i64:$s, i32:$x, i32:$y, i32:$z),
- (TEX_3D_S32_S32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_3d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
- (TEX_3D_S32_F32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_3d_v4u32_s32 i64:$t, i64:$s, i32:$x, i32:$y, i32:$z),
- (TEX_3D_U32_S32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_3d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
- (TEX_3D_U32_F32_RR $t, $s, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_tex_3d_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_3D_F32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_3d_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_3D_S32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_3d_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_3D_U32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
-
-def : Pat<(int_nvvm_tex_3d_grad_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_3D_F32_F32_GRAD_RR $t, $s, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_3d_grad_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_3D_S32_F32_GRAD_RR $t, $s, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_3d_grad_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_3D_U32_F32_GRAD_RR $t, $s, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-
-def : Pat<(int_nvvm_tex_cube_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
- (TEX_CUBE_F32_F32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_cube_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
- (TEX_CUBE_S32_F32_RR $t, $s, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_cube_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z),
- (TEX_CUBE_U32_F32_RR $t, $s, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_tex_cube_level_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_CUBE_F32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_cube_level_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_CUBE_S32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_cube_level_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_CUBE_U32_F32_LEVEL_RR $t, $s, $x, $y, $z, $lod)>;
-
-def : Pat<(int_nvvm_tex_cube_array_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z),
- (TEX_CUBE_ARRAY_F32_F32_RR $t, $s, $l, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_cube_array_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z),
- (TEX_CUBE_ARRAY_S32_F32_RR $t, $s, $l, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_cube_array_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z),
- (TEX_CUBE_ARRAY_U32_F32_RR $t, $s, $l, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_tex_cube_array_level_v4f32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_CUBE_ARRAY_F32_F32_LEVEL_RR $t, $s, $l, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_cube_array_level_v4s32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_CUBE_ARRAY_S32_F32_LEVEL_RR $t, $s, $l, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_cube_array_level_v4u32_f32 i64:$t, i64:$s, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_CUBE_ARRAY_U32_F32_LEVEL_RR $t, $s, $l, $x, $y, $z, $lod)>;
-
-def : Pat<(int_nvvm_tld4_r_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_R_2D_F32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_g_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_G_2D_F32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_b_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_B_2D_F32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_a_2d_v4f32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_A_2D_F32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_r_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_R_2D_S32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_g_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_G_2D_S32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_b_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_B_2D_S32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_a_2d_v4s32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_A_2D_S32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_r_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_R_2D_U32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_g_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_G_2D_U32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_b_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_B_2D_U32_F32_RR $t, $s, $x, $y)>;
-def : Pat<(int_nvvm_tld4_a_2d_v4u32_f32 i64:$t, i64:$s, f32:$x, f32:$y),
- (TLD4_A_2D_U32_F32_RR $t, $s, $x, $y)>;
-
-def : Pat<(int_nvvm_tex_unified_1d_v4f32_s32 i64:$t, i32:$x),
- (TEX_UNIFIED_1D_F32_S32_R $t, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_v4f32_f32 i64:$t, f32:$x),
- (TEX_UNIFIED_1D_F32_F32_R $t, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_v4s32_s32 i64:$t, i32:$x),
- (TEX_UNIFIED_1D_S32_S32_R $t, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_v4s32_f32 i64:$t, f32:$x),
- (TEX_UNIFIED_1D_S32_F32_R $t, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_v4u32_s32 i64:$t, i32:$x),
- (TEX_UNIFIED_1D_U32_S32_R $t, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_v4u32_f32 i64:$t, f32:$x),
- (TEX_UNIFIED_1D_U32_F32_R $t, $x)>;
-
-def : Pat<(int_nvvm_tex_unified_1d_level_v4f32_f32 i64:$t, f32:$x, f32:$lod),
- (TEX_UNIFIED_1D_F32_F32_LEVEL_R $t, $x, $lod)>;
-def : Pat<(int_nvvm_tex_unified_1d_level_v4s32_f32 i64:$t, f32:$x, f32:$lod),
- (TEX_UNIFIED_1D_S32_F32_LEVEL_R $t, $x, $lod)>;
-def : Pat<(int_nvvm_tex_unified_1d_level_v4u32_f32 i64:$t, f32:$x, f32:$lod),
- (TEX_UNIFIED_1D_U32_F32_LEVEL_R $t, $x, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_1d_grad_v4f32_f32 i64:$t, f32:$x, f32:$gradx, f32:$grady),
- (TEX_UNIFIED_1D_F32_F32_GRAD_R $t, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_unified_1d_grad_v4s32_f32 i64:$t, f32:$x, f32:$gradx, f32:$grady),
- (TEX_UNIFIED_1D_S32_F32_GRAD_R $t, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_unified_1d_grad_v4u32_f32 i64:$t, f32:$x, f32:$gradx, f32:$grady),
- (TEX_UNIFIED_1D_U32_F32_GRAD_R $t, $x, $gradx, $grady)>;
-
-def : Pat<(int_nvvm_tex_unified_1d_array_v4f32_s32 i64:$t, i32:$l, i32:$x),
- (TEX_UNIFIED_1D_ARRAY_F32_S32_R $t, $l, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_v4f32_f32 i64:$t, i32:$l, f32:$x),
- (TEX_UNIFIED_1D_ARRAY_F32_F32_R $t, $l, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_v4s32_s32 i64:$t, i32:$l, i32:$x),
- (TEX_UNIFIED_1D_ARRAY_S32_S32_R $t, $l, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_v4s32_f32 i64:$t, i32:$l, f32:$x),
- (TEX_UNIFIED_1D_ARRAY_S32_F32_R $t, $l, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_v4u32_s32 i64:$t, i32:$l, i32:$x),
- (TEX_UNIFIED_1D_ARRAY_U32_S32_R $t, $l, $x)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_v4u32_f32 i64:$t, i32:$l, f32:$x),
- (TEX_UNIFIED_1D_ARRAY_U32_F32_R $t, $l, $x)>;
-
-def : Pat<(int_nvvm_tex_unified_1d_array_level_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$lod),
- (TEX_UNIFIED_1D_ARRAY_F32_F32_LEVEL_R $t, $l, $x, $lod)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_level_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$lod),
- (TEX_UNIFIED_1D_ARRAY_S32_F32_LEVEL_R $t, $l, $x, $lod)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_level_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$lod),
- (TEX_UNIFIED_1D_ARRAY_U32_F32_LEVEL_R $t, $l, $x, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_1d_array_grad_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$gradx, f32:$grady),
- (TEX_UNIFIED_1D_ARRAY_F32_F32_GRAD_R $t, $l, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_grad_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$gradx, f32:$grady),
- (TEX_UNIFIED_1D_ARRAY_S32_F32_GRAD_R $t, $l, $x, $gradx, $grady)>;
-def : Pat<(int_nvvm_tex_unified_1d_array_grad_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$gradx, f32:$grady),
- (TEX_UNIFIED_1D_ARRAY_U32_F32_GRAD_R $t, $l, $x, $gradx, $grady)>;
-
-def : Pat<(int_nvvm_tex_unified_2d_v4f32_s32 i64:$t, i32:$x, i32:$y),
- (TEX_UNIFIED_2D_F32_S32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
- (TEX_UNIFIED_2D_F32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_v4s32_s32 i64:$t, i32:$x, i32:$y),
- (TEX_UNIFIED_2D_S32_S32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
- (TEX_UNIFIED_2D_S32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_v4u32_s32 i64:$t, i32:$x, i32:$y),
- (TEX_UNIFIED_2D_U32_S32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
- (TEX_UNIFIED_2D_U32_F32_R $t, $x, $y)>;
-
-def : Pat<(int_nvvm_tex_unified_2d_level_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$lod),
- (TEX_UNIFIED_2D_F32_F32_LEVEL_R $t, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_unified_2d_level_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$lod),
- (TEX_UNIFIED_2D_S32_F32_LEVEL_R $t, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_unified_2d_level_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$lod),
- (TEX_UNIFIED_2D_U32_F32_LEVEL_R $t, $x, $y, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_2d_grad_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_UNIFIED_2D_F32_F32_GRAD_R $t, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_unified_2d_grad_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_UNIFIED_2D_S32_F32_GRAD_R $t, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_unified_2d_grad_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_UNIFIED_2D_U32_F32_GRAD_R $t, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-
-def : Pat<(int_nvvm_tex_unified_2d_array_v4f32_s32 i64:$t, i32:$l, i32:$x, i32:$y),
- (TEX_UNIFIED_2D_ARRAY_F32_S32_R $t, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y),
- (TEX_UNIFIED_2D_ARRAY_F32_F32_R $t, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_v4s32_s32 i64:$t, i32:$l, i32:$x, i32:$y),
- (TEX_UNIFIED_2D_ARRAY_S32_S32_R $t, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y),
- (TEX_UNIFIED_2D_ARRAY_S32_F32_R $t, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_v4u32_s32 i64:$t, i32:$l, i32:$x, i32:$y),
- (TEX_UNIFIED_2D_ARRAY_U32_S32_R $t, $l, $x, $y)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y),
- (TEX_UNIFIED_2D_ARRAY_U32_F32_R $t, $l, $x, $y)>;
-
-def : Pat<(int_nvvm_tex_unified_2d_array_level_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$lod),
- (TEX_UNIFIED_2D_ARRAY_F32_F32_LEVEL_R $t, $l, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_level_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$lod),
- (TEX_UNIFIED_2D_ARRAY_S32_F32_LEVEL_R $t, $l, $x, $y, $lod)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_level_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$lod),
- (TEX_UNIFIED_2D_ARRAY_U32_F32_LEVEL_R $t, $l, $x, $y, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_2d_array_grad_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_UNIFIED_2D_ARRAY_F32_F32_GRAD_R $t, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_grad_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_UNIFIED_2D_ARRAY_S32_F32_GRAD_R $t, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-def : Pat<(int_nvvm_tex_unified_2d_array_grad_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$gradx0, f32:$gradx1, f32:$grady0, f32:$grady1),
- (TEX_UNIFIED_2D_ARRAY_U32_F32_GRAD_R $t, $l, $x, $y, $gradx0, $gradx1, $grady0, $grady1)>;
-
-def : Pat<(int_nvvm_tex_unified_3d_v4f32_s32 i64:$t, i32:$x, i32:$y, i32:$z),
- (TEX_UNIFIED_3D_F32_S32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_3d_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_3D_F32_F32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_3d_v4s32_s32 i64:$t, i32:$x, i32:$y, i32:$z),
- (TEX_UNIFIED_3D_S32_S32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_3d_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_3D_S32_F32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_3d_v4u32_s32 i64:$t, i32:$x, i32:$y, i32:$z),
- (TEX_UNIFIED_3D_U32_S32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_3d_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_3D_U32_F32_R $t, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_tex_unified_3d_level_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_3D_F32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_unified_3d_level_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_3D_S32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_unified_3d_level_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_3D_U32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_3d_grad_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_3D_F32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_unified_3d_grad_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_3D_S32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_unified_3d_grad_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_3D_U32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-
-def : Pat<(int_nvvm_tex_unified_cube_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_CUBE_F32_F32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_cube_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_CUBE_S32_F32_R $t, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_cube_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_CUBE_U32_F32_R $t, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_tex_unified_cube_level_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_CUBE_F32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_unified_cube_level_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_CUBE_S32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_unified_cube_level_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_CUBE_U32_F32_LEVEL_R $t, $x, $y, $z, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_cube_array_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_CUBE_ARRAY_F32_F32_R $t, $l, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_cube_array_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_CUBE_ARRAY_S32_F32_R $t, $l, $x, $y, $z)>;
-def : Pat<(int_nvvm_tex_unified_cube_array_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z),
- (TEX_UNIFIED_CUBE_ARRAY_U32_F32_R $t, $l, $x, $y, $z)>;
-
-def : Pat<(int_nvvm_tex_unified_cube_array_level_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_CUBE_ARRAY_F32_F32_LEVEL_R $t, $l, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_unified_cube_array_level_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_CUBE_ARRAY_S32_F32_LEVEL_R $t, $l, $x, $y, $z, $lod)>;
-def : Pat<(int_nvvm_tex_unified_cube_array_level_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$lod),
- (TEX_UNIFIED_CUBE_ARRAY_U32_F32_LEVEL_R $t, $l, $x, $y, $z, $lod)>;
-
-def : Pat<(int_nvvm_tex_unified_cube_grad_v4f32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_CUBE_F32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_unified_cube_grad_v4s32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_CUBE_S32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_unified_cube_grad_v4u32_f32 i64:$t, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_CUBE_U32_F32_GRAD_R $t, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-
-def : Pat<(int_nvvm_tex_unified_cube_array_grad_v4f32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_CUBE_ARRAY_F32_F32_GRAD_R $t, $l, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_unified_cube_array_grad_v4s32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_CUBE_ARRAY_S32_F32_GRAD_R $t, $l, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-def : Pat<(int_nvvm_tex_unified_cube_array_grad_v4u32_f32 i64:$t, i32:$l, f32:$x, f32:$y, f32:$z, f32:$gradx0, f32:$gradx1, f32:$gradx2, f32:$grady0, f32:$grady1, f32:$grady2),
- (TEX_UNIFIED_CUBE_ARRAY_U32_F32_GRAD_R $t, $l, $x, $y, $z, $gradx0, $gradx1, $gradx2, $grady0, $grady1, $grady2)>;
-
-def : Pat<(int_nvvm_tld4_unified_r_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_R_2D_F32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_g_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_G_2D_F32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_b_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_B_2D_F32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_a_2d_v4f32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_A_2D_F32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_r_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_R_2D_S32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_g_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_G_2D_S32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_b_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_B_2D_S32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_a_2d_v4s32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_A_2D_S32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_r_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_R_2D_U32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_g_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_G_2D_U32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_b_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_B_2D_U32_F32_R $t, $x, $y)>;
-def : Pat<(int_nvvm_tld4_unified_a_2d_v4u32_f32 i64:$t, f32:$x, f32:$y),
- (TLD4_UNIFIED_A_2D_U32_F32_R $t, $x, $y)>;
>From 8f0578bae21235f39461eb1c158087c2695c8840 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 15 Dec 2024 16:10:19 +0300
Subject: [PATCH 4/4] Try to make the formatting neater
---
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td | 154 ++++++++++++-----------
1 file changed, 84 insertions(+), 70 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 83a67ea3e52805..8364b658495c75 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -2957,8 +2957,8 @@ class TEX_1D_base<string inst, NVPTXRegClass outtype,
multiclass TEX_1D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
Intrinsic intr> {
- def _RR : TEX_1D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_1D_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x))]>;
def _RI : TEX_1D_base<inst, outtype, intype,
@@ -2993,8 +2993,8 @@ class TEX_1D_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_1D_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_1D_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_1D_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$lod))]>;
def _RI : TEX_1D_LEVEL_base<inst, outtype, intype,
@@ -3027,8 +3027,8 @@ class TEX_1D_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_1D_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_1D_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_1D_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$gradx, intype:$grady))]>;
def _RI : TEX_1D_GRAD_base<inst, outtype, intype,
@@ -3060,8 +3060,8 @@ class TEX_1D_ARRAY_base<string inst, NVPTXRegClass outtype,
multiclass TEX_1D_ARRAY<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_1D_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_1D_ARRAY_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x))]>;
def _RI : TEX_1D_ARRAY_base<inst, outtype, intype,
@@ -3103,8 +3103,8 @@ class TEX_1D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_1D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_1D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_1D_ARRAY_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$lod))]>;
def _RI : TEX_1D_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -3138,8 +3138,8 @@ class TEX_1D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_1D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_1D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_1D_ARRAY_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x,
intype:$gradx, intype:$grady))]>;
@@ -3171,8 +3171,8 @@ class TEX_2D_base<string inst, NVPTXRegClass outtype,
multiclass TEX_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
Intrinsic intr> {
- def _RR : TEX_2D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_2D_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y))]>;
def _RI : TEX_2D_base<inst, outtype, intype, (ins Int64Regs:$t, i64imm:$s)>;
@@ -3205,8 +3205,8 @@ class TEX_2D_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_2D_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_2D_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_2D_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$lod))]>;
def _RI : TEX_2D_LEVEL_base<inst, outtype, intype,
@@ -3241,8 +3241,8 @@ class TEX_2D_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_2D_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_2D_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_2D_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y,
intype:$gradx0, intype:$gradx1,
@@ -3277,8 +3277,8 @@ class TEX_2D_ARRAY_base<string inst, NVPTXRegClass outtype,
multiclass TEX_2D_ARRAY<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_2D_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_2D_ARRAY_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y))]>;
def _RI : TEX_2D_ARRAY_base<inst, outtype, intype,
@@ -3321,8 +3321,8 @@ class TEX_2D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_2D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_2D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_2D_ARRAY_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y, intype:$lod))]>;
def _RI : TEX_2D_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -3358,8 +3358,8 @@ class TEX_2D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_2D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_2D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_2D_ARRAY_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y,
intype:$gradx0, intype:$gradx1,
@@ -3393,8 +3393,8 @@ class TEX_3D_base<string inst, NVPTXRegClass outtype,
multiclass TEX_3D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
Intrinsic intr> {
- def _RR : TEX_3D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_3D_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z))]>;
def _RI : TEX_3D_base<inst, outtype, intype,
@@ -3431,8 +3431,8 @@ class TEX_3D_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_3D_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_3D_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_3D_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z,
intype:$lod))]>;
@@ -3471,8 +3471,8 @@ class TEX_3D_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_3D_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_3D_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_3D_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z,
intype:$gradx0, intype:$gradx1, intype:$gradx2,
@@ -3506,8 +3506,8 @@ class TEX_CUBE_base<string inst, NVPTXRegClass outtype,
multiclass TEX_CUBE<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
Intrinsic intr> {
- def _RR : TEX_CUBE_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_CUBE_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z))]>;
def _RI : TEX_CUBE_base<inst, outtype, intype,
@@ -3541,8 +3541,8 @@ class TEX_CUBE_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_CUBE_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_CUBE_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_CUBE_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, intype:$x, intype:$y, intype:$z,
intype:$lod))]>;
@@ -3577,8 +3577,8 @@ class TEX_CUBE_ARRAY_base<string inst, NVPTXRegClass outtype,
multiclass TEX_CUBE_ARRAY<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_CUBE_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_CUBE_ARRAY_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y, intype:$z))]>;
def _RI : TEX_CUBE_ARRAY_base<inst, outtype, intype,
@@ -3612,8 +3612,8 @@ class TEX_CUBE_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_CUBE_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _RR : TEX_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TEX_CUBE_ARRAY_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i64:$s, i32:$l, intype:$x, intype:$y, intype:$z,
intype:$lod))]>;
@@ -3648,8 +3648,8 @@ class TLD4_2D_base<string inst, NVPTXRegClass outtype,
multiclass TLD4_2D<string inst, NVPTXRegClass outtype, NVPTXRegClass intype,
Intrinsic intr> {
- def _RR : TLD4_2D_base<inst, outtype, intype,
- (ins Int64Regs:$t, Int64Regs:$s),
+ def _RR : TLD4_2D_base<
+ inst, outtype, intype, (ins Int64Regs:$t, Int64Regs:$s),
[(set outtype:$v0, outtype:$v1, outtype:$v2, outtype:$v3,
(intr i64:$t, i64:$s, intype:$x, intype:$y))]>;
def _RI : TLD4_2D_base<inst, outtype, intype,
@@ -3716,7 +3716,8 @@ class TEX_UNIFIED_1D_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_1D<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_1D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_1D_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x))]>;
def _I : TEX_UNIFIED_1D_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -3752,7 +3753,8 @@ class TEX_UNIFIED_1D_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_1D_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_1D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_1D_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$lod))]>;
def _I : TEX_UNIFIED_1D_LEVEL_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -3780,7 +3782,8 @@ class TEX_UNIFIED_1D_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_1D_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_1D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_1D_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$gradx, intype:$grady))]>;
def _I : TEX_UNIFIED_1D_GRAD_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -3807,7 +3810,8 @@ class TEX_UNIFIED_1D_ARRAY_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_1D_ARRAY<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_1D_ARRAY_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_1D_ARRAY_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x))]>;
def _I : TEX_UNIFIED_1D_ARRAY_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -3843,8 +3847,8 @@ class TEX_UNIFIED_1D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_1D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_1D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_1D_ARRAY_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$lod))]>;
def _I : TEX_UNIFIED_1D_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -3877,8 +3881,8 @@ class TEX_UNIFIED_1D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_1D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_1D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_1D_ARRAY_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$gradx, intype:$grady))]>;
def _I : TEX_UNIFIED_1D_ARRAY_GRAD_base<inst, outtype, intype,
@@ -3908,7 +3912,8 @@ class TEX_UNIFIED_2D_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_2D<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_2D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_2D_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y))]>;
def _I : TEX_UNIFIED_2D_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -3944,7 +3949,8 @@ class TEX_UNIFIED_2D_LEVEL_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_2D_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_2D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_2D_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$lod))]>;
def _I : TEX_UNIFIED_2D_LEVEL_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -3973,7 +3979,8 @@ class TEX_UNIFIED_2D_GRAD_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_2D_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_2D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_2D_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y,
intype:$gradx0, intype:$gradx1,
@@ -4001,7 +4008,8 @@ class TEX_UNIFIED_2D_ARRAY_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_2D_ARRAY<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_2D_ARRAY_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_2D_ARRAY_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$y))]>;
def _I : TEX_UNIFIED_2D_ARRAY_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -4038,8 +4046,8 @@ class TEX_UNIFIED_2D_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_2D_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_2D_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_2D_ARRAY_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$lod))]>;
def _I : TEX_UNIFIED_2D_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -4072,8 +4080,8 @@ class TEX_UNIFIED_2D_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_2D_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_2D_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_2D_ARRAY_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$y,
intype:$gradx0, intype:$gradx1,
@@ -4104,7 +4112,8 @@ class TEX_UNIFIED_3D_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_3D<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_3D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_3D_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$z))]>;
def _I : TEX_UNIFIED_3D_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -4140,7 +4149,8 @@ class TEX_UNIFIED_3D_LEVEL_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_3D_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_3D_LEVEL_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_3D_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$z, intype:$lod))]>;
def _I : TEX_UNIFIED_3D_LEVEL_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -4171,7 +4181,8 @@ class TEX_UNIFIED_3D_GRAD_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_3D_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_3D_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_3D_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$z,
intype:$gradx0, intype:$gradx1, intype:$gradx2,
@@ -4199,7 +4210,8 @@ class TEX_UNIFIED_CUBE_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_CUBE<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_CUBE_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_CUBE_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$z))]>;
def _I : TEX_UNIFIED_CUBE_base<inst, outtype, intype, (ins i64imm:$t)>;
@@ -4226,8 +4238,8 @@ class TEX_UNIFIED_CUBE_LEVEL_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_CUBE_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_CUBE_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_CUBE_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$z, intype:$lod))]>;
def _I : TEX_UNIFIED_CUBE_LEVEL_base<inst, outtype, intype,
@@ -4257,8 +4269,8 @@ class TEX_UNIFIED_CUBE_ARRAY_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_CUBE_ARRAY<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_CUBE_ARRAY_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_CUBE_ARRAY_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$z))]>;
def _I : TEX_UNIFIED_CUBE_ARRAY_base<inst, outtype, intype,
@@ -4287,8 +4299,8 @@ class TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_CUBE_ARRAY_LEVEL<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$z, intype:$lod))]>;
def _I : TEX_UNIFIED_CUBE_ARRAY_LEVEL_base<inst, outtype, intype,
@@ -4324,7 +4336,8 @@ class TEX_UNIFIED_CUBE_GRAD_base<string inst, NVPTXRegClass outtype,
multiclass TEX_UNIFIED_CUBE_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_CUBE_GRAD_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_CUBE_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, intype:$x, intype:$y, intype:$z,
intype:$gradx0, intype:$gradx1, intype:$gradx2,
@@ -4357,8 +4370,8 @@ class TEX_UNIFIED_CUBE_ARRAY_GRAD_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TEX_UNIFIED_CUBE_ARRAY_GRAD<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TEX_UNIFIED_CUBE_ARRAY_GRAD_base<inst, outtype, intype,
- (ins Int64Regs:$t),
+ def _R : TEX_UNIFIED_CUBE_ARRAY_GRAD_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$r, outtype:$g, outtype:$b, outtype:$a,
(intr i64:$t, i32:$l, intype:$x, intype:$y, intype:$z,
intype:$gradx0, intype:$gradx1,
@@ -4391,7 +4404,8 @@ class TLD4_UNIFIED_2D_base<string inst, NVPTXRegClass outtype,
pattern>;
multiclass TLD4_UNIFIED_2D<string inst, NVPTXRegClass outtype,
NVPTXRegClass intype, Intrinsic intr> {
- def _R : TLD4_UNIFIED_2D_base<inst, outtype, intype, (ins Int64Regs:$t),
+ def _R : TLD4_UNIFIED_2D_base<
+ inst, outtype, intype, (ins Int64Regs:$t),
[(set outtype:$v0, outtype:$v1, outtype:$v2, outtype:$v3,
(intr i64:$t, intype:$x, intype:$y))]>;
def _I : TLD4_UNIFIED_2D_base<inst, outtype, intype, (ins i64imm:$t)>;
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