[llvm] [CodeGen] Add empty implementation of SelectionDAGInfo to some targets (PR #119968)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 14 06:00:18 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sergei Barannikov (s-barannikov)
<details>
<summary>Changes</summary>
#<!-- -->119969 adds a couple of new methods to this class, which will need to be overridden by these targets.
Part of #<!-- -->119709.
---
Patch is 31.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119968.diff
28 Files Affected:
- (added) llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp (+13)
- (added) llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h (+23)
- (modified) llvm/lib/Target/AMDGPU/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.cpp (+8)
- (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (+5-7)
- (modified) llvm/lib/Target/AMDGPU/R600Subtarget.cpp (+8)
- (modified) llvm/lib/Target/AMDGPU/R600Subtarget.h (+4-6)
- (modified) llvm/lib/Target/Mips/CMakeLists.txt (+1)
- (added) llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp (+13)
- (added) llvm/lib/Target/Mips/MipsSelectionDAGInfo.h (+23)
- (modified) llvm/lib/Target/Mips/MipsSubtarget.cpp (+16-6)
- (modified) llvm/lib/Target/Mips/MipsSubtarget.h (+5-5)
- (modified) llvm/lib/Target/NVPTX/CMakeLists.txt (+1)
- (added) llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp (+13)
- (added) llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h (+23)
- (modified) llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp (+10-1)
- (modified) llvm/lib/Target/NVPTX/NVPTXSubtarget.h (+5-5)
- (modified) llvm/lib/Target/PowerPC/CMakeLists.txt (+1)
- (added) llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp (+13)
- (added) llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h (+23)
- (modified) llvm/lib/Target/PowerPC/PPCSubtarget.cpp (+9)
- (modified) llvm/lib/Target/PowerPC/PPCSubtarget.h (+9-5)
- (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+1)
- (added) llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp (+13)
- (added) llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h (+23)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+10-1)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+7-5)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.h (-1)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..7bc651504e36d4
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUSelectionDAGInfo.h"
+
+using namespace llvm;
+
+AMDGPUSelectionDAGInfo::~AMDGPUSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
new file mode 100644
index 00000000000000..bb11a56da52596
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class AMDGPUSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~AMDGPUSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index 68d141e338a882..03038caab521df 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -100,6 +100,7 @@ add_llvm_target(AMDGPUCodeGen
AMDGPUResourceUsageAnalysis.cpp
AMDGPURewriteOutArguments.cpp
AMDGPURewriteUndefForPHI.cpp
+ AMDGPUSelectionDAGInfo.cpp
AMDGPUSetWavePriority.cpp
AMDGPUSplitModule.cpp
AMDGPUSubtarget.cpp
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 51361b75940560..117afc4a8e8c60 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -16,6 +16,7 @@
#include "AMDGPUInstructionSelector.h"
#include "AMDGPULegalizerInfo.h"
#include "AMDGPURegisterBankInfo.h"
+#include "AMDGPUSelectionDAGInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -185,6 +186,9 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
// clang-format on
MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this);
EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(this);
+
+ TSInfo = std::make_unique<AMDGPUSelectionDAGInfo>();
+
CallLoweringInfo = std::make_unique<AMDGPUCallLowering>(*getTargetLowering());
InlineAsmLoweringInfo =
std::make_unique<InlineAsmLowering>(getTargetLowering());
@@ -194,6 +198,10 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
std::make_unique<AMDGPUInstructionSelector>(*this, *RegBankInfo, TM);
}
+const SelectionDAGTargetInfo *GCNSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
+
unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const {
if (getGeneration() < GFX10)
return 1;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 5cecaf6349c883..3388bc3c5a8de1 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -21,7 +21,6 @@
#include "SIISelLowering.h"
#include "SIInstrInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
#define GET_SUBTARGETINFO_HEADER
@@ -49,6 +48,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
};
private:
+ /// SelectionDAGISel related APIs.
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
+
/// GlobalISel related APIs.
std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
@@ -257,7 +259,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// Dummy feature to use for assembler in tablegen.
bool FeatureDisable = false;
- SelectionDAGTargetInfo TSInfo;
private:
SIInstrInfo InstrInfo;
SITargetLowering TLInfo;
@@ -291,6 +292,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return &InstrInfo.getRegisterInfo();
}
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
+
const CallLowering *getCallLowering() const override {
return CallLoweringInfo.get();
}
@@ -315,11 +318,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return TargetID;
}
- // Nothing implemented, just prevent crashes on use.
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
-
const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins;
}
diff --git a/llvm/lib/Target/AMDGPU/R600Subtarget.cpp b/llvm/lib/Target/AMDGPU/R600Subtarget.cpp
index fd5a87999cf81b..77fbd416955c23 100644
--- a/llvm/lib/Target/AMDGPU/R600Subtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/R600Subtarget.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "R600Subtarget.h"
+#include "AMDGPUSelectionDAGInfo.h"
#include "MCTargetDesc/R600MCTargetDesc.h"
using namespace llvm;
@@ -30,6 +31,13 @@ R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
TLInfo(TM, initializeSubtargetDependencies(TT, GPU, FS)),
InstrItins(getInstrItineraryForCPU(GPU)) {
LocalMemorySize = AddressableLocalMemorySize;
+ TSInfo = std::make_unique<AMDGPUSelectionDAGInfo>();
+}
+
+R600Subtarget::~R600Subtarget() = default;
+
+const SelectionDAGTargetInfo *R600Subtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
}
R600Subtarget &R600Subtarget::initializeSubtargetDependencies(const Triple &TT,
diff --git a/llvm/lib/Target/AMDGPU/R600Subtarget.h b/llvm/lib/Target/AMDGPU/R600Subtarget.h
index 7f0f9305e1fa6c..22e56b66e18277 100644
--- a/llvm/lib/Target/AMDGPU/R600Subtarget.h
+++ b/llvm/lib/Target/AMDGPU/R600Subtarget.h
@@ -19,7 +19,6 @@
#include "R600ISelLowering.h"
#include "R600InstrInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "R600GenSubtargetInfo.inc"
@@ -41,12 +40,14 @@ class R600Subtarget final : public R600GenSubtargetInfo,
Generation Gen = R600;
R600TargetLowering TLInfo;
InstrItineraryData InstrItins;
- SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
public:
R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM);
+ ~R600Subtarget() override;
+
const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
const R600FrameLowering *getFrameLowering() const override {
@@ -65,10 +66,7 @@ class R600Subtarget final : public R600GenSubtargetInfo,
return &InstrItins;
}
- // Nothing implemented, just prevent crashes on use.
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt
index 28f66a4ad94826..21d1765107ae6f 100644
--- a/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/CMakeLists.txt
@@ -58,6 +58,7 @@ add_llvm_target(MipsCodeGen
MipsSEISelDAGToDAG.cpp
MipsSEISelLowering.cpp
MipsSERegisterInfo.cpp
+ MipsSelectionDAGInfo.cpp
MipsSubtarget.cpp
MipsTargetMachine.cpp
MipsTargetObjectFile.cpp
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..c24107bf639434
--- /dev/null
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "MipsSelectionDAGInfo.h"
+
+using namespace llvm;
+
+MipsSelectionDAGInfo::~MipsSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
new file mode 100644
index 00000000000000..bccd924a30e711
--- /dev/null
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class MipsSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~MipsSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index cafb20f983f1f5..2210eca9eb1051 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -16,6 +16,7 @@
#include "MipsLegalizerInfo.h"
#include "MipsRegisterBankInfo.h"
#include "MipsRegisterInfo.h"
+#include "MipsSelectionDAGInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -78,13 +79,14 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
- HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 || Mips_Os16),
- Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
- HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
- HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false), StrictAlign(false),
+ HasDSPR2(false), HasDSPR3(false),
+ AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
+ UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
+ HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
+ UseIndirectJumpsHazard(false), StrictAlign(false),
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
- TSInfo(), InstrInfo(MipsInstrInfo::create(
- initializeSubtargetDependencies(CPU, FS, TM))),
+ InstrInfo(
+ MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
FrameLowering(MipsFrameLowering::create(*this)),
TLInfo(MipsTargetLowering::create(TM, *this)) {
@@ -211,6 +213,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
GINVWarningPrinted = true;
}
+ TSInfo = std::make_unique<MipsSelectionDAGInfo>();
+
CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
Legalizer.reset(new MipsLegalizerInfo(*this));
@@ -219,6 +223,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
InstSelector.reset(createMipsInstructionSelector(TM, *this, *RBI));
}
+MipsSubtarget::~MipsSubtarget() = default;
+
bool MipsSubtarget::isPositionIndependent() const {
return TM.isPositionIndependent();
}
@@ -280,6 +286,10 @@ bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
+const SelectionDAGTargetInfo *MipsSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
+
const CallLowering *MipsSubtarget::getCallLowering() const {
return CallLoweringInfo.get();
}
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index fea7f11fd07054..c048ab29d5f9b2 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -21,7 +21,6 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/RegisterBankInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCInstrItineraries.h"
@@ -220,7 +219,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Triple TargetTriple;
- const SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
std::unique_ptr<const MipsInstrInfo> InstrInfo;
std::unique_ptr<const MipsFrameLowering> FrameLowering;
std::unique_ptr<const MipsTargetLowering> TLInfo;
@@ -243,6 +242,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
+ ~MipsSubtarget() override;
+
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
@@ -383,9 +384,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
void setHelperClassesMips16();
void setHelperClassesMipsSE();
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
+
const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
const TargetFrameLowering *getFrameLowering() const override {
return FrameLowering.get();
diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt
index 693365161330f5..dfbda845347322 100644
--- a/llvm/lib/Target/NVPTX/CMakeLists.txt
+++ b/llvm/lib/Target/NVPTX/CMakeLists.txt
@@ -31,6 +31,7 @@ set(NVPTXCodeGen_sources
NVPTXPrologEpilogPass.cpp
NVPTXRegisterInfo.cpp
NVPTXReplaceImageHandles.cpp
+ NVPTXSelectionDAGInfo.cpp
NVPTXSubtarget.cpp
NVPTXTargetMachine.cpp
NVPTXTargetTransformInfo.cpp
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..9c26f310bbf653
--- /dev/null
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "NVPTXSelectionDAGInfo.h"
+
+using namespace llvm;
+
+NVPTXSelectionDAGInfo::~NVPTXSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
new file mode 100644
index 00000000000000..6b04d78ca96878
--- /dev/null
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class NVPTXSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~NVPTXSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index 0e6b75e622c6ad..34571465aea6f0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "NVPTXSubtarget.h"
+#include "NVPTXSelectionDAGInfo.h"
#include "NVPTXTargetMachine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormatVariadic.h"
@@ -56,7 +57,15 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
FullSmVersion(200), SmVersion(getSmVersion()), TM(TM),
- TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}
+ TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {
+ TSInfo = std::make_unique<NVPTXSelectionDAGInfo>();
+}
+
+NVPTXSubtarget::~NVPTXSubtarget() = default;
+
+const SelectionDAGTargetInfo *NVPTXSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
bool NVPTXSubtarget::hasImageHandles() const {
// Enable handles for Kepler+, where CUDA supports indirect surfaces and
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index e785bbf830da62..2a2b98dd4fb6af 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -18,7 +18,6 @@
#include "NVPTXISelLowering.h"
#include "NVPTXInstrInfo.h"
#include "NVPTXRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include <string>
@@ -46,7 +45,7 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
const NVPTXTargetMachine &TM;
NVPTXInstrInfo InstrInfo;
NVPTXTargetLowering TLInfo;
- SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
// NVPTX does not have any call stack frame, but need a NVPTX specific
// FrameLowering class because TargetFrameLowering is abstract.
@@ -59,6 +58,8 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const NVPTXTargetMachine &TM);
+ ~NVPTXSubtarget() override;
+
const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
@@ -69,9 +70,8 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
const NVPTXTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
bool hasAtomAddF64() const { return SmVersion >= 60; }
bool hasAtomScope() const { return SmVersion >= 60; }
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index 8f7b53b622065d..3808a26a0b92a0 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -43,6 +43,7 @@ add_llvm_target(PowerPCCodeGen
PPCMacroFusion.cpp
PPCMIPeephole.cpp
PPCRegisterInfo.cpp
+ PPCSelectionDAGInfo.cpp
PPCSubtarget.cpp
PPCTargetMachine.cpp
PPCTargetObjectFile.cpp
diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp b/llvm/lib/T...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/119968
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