[llvm] [CodeGen] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (PR #119969)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sat Dec 14 05:54:08 PST 2024
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/119969
None
>From af6d99c654cc25e2b373cef05fed27a800a15dbc Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Wed, 13 Nov 2024 20:29:24 +0300
Subject: [PATCH 1/2] [CodeGen] Implement SelectionDAGInfo for some targets
A future patch adds a couple of new methods to this class,
which will need to be overridden by these targets.
Part of #119709.
---
.../Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp | 13 +++++++++++
.../Target/AMDGPU/AMDGPUSelectionDAGInfo.h | 23 +++++++++++++++++++
llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 +
llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 8 +++++++
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 12 ++++------
llvm/lib/Target/AMDGPU/R600Subtarget.cpp | 8 +++++++
llvm/lib/Target/AMDGPU/R600Subtarget.h | 10 ++++----
llvm/lib/Target/Mips/CMakeLists.txt | 1 +
llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp | 13 +++++++++++
llvm/lib/Target/Mips/MipsSelectionDAGInfo.h | 23 +++++++++++++++++++
llvm/lib/Target/Mips/MipsSubtarget.cpp | 22 +++++++++++++-----
llvm/lib/Target/Mips/MipsSubtarget.h | 10 ++++----
llvm/lib/Target/NVPTX/CMakeLists.txt | 1 +
.../Target/NVPTX/NVPTXSelectionDAGInfo.cpp | 13 +++++++++++
llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h | 23 +++++++++++++++++++
llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp | 11 ++++++++-
llvm/lib/Target/NVPTX/NVPTXSubtarget.h | 10 ++++----
llvm/lib/Target/PowerPC/CMakeLists.txt | 1 +
.../Target/PowerPC/PPCSelectionDAGInfo.cpp | 13 +++++++++++
llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h | 23 +++++++++++++++++++
llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 9 ++++++++
llvm/lib/Target/PowerPC/PPCSubtarget.h | 14 +++++++----
llvm/lib/Target/RISCV/CMakeLists.txt | 1 +
.../Target/RISCV/RISCVSelectionDAGInfo.cpp | 13 +++++++++++
llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h | 23 +++++++++++++++++++
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 11 ++++++++-
llvm/lib/Target/RISCV/RISCVSubtarget.h | 12 ++++++----
llvm/lib/Target/RISCV/RISCVTargetMachine.h | 1 -
28 files changed, 281 insertions(+), 42 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
create mode 100644 llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
create mode 100644 llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
create mode 100644 llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
create mode 100644 llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
create mode 100644 llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
create mode 100644 llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
create mode 100644 llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
create mode 100644 llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
create mode 100644 llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..7bc651504e36d4
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUSelectionDAGInfo.h"
+
+using namespace llvm;
+
+AMDGPUSelectionDAGInfo::~AMDGPUSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
new file mode 100644
index 00000000000000..bb11a56da52596
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class AMDGPUSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~AMDGPUSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index 68d141e338a882..03038caab521df 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -100,6 +100,7 @@ add_llvm_target(AMDGPUCodeGen
AMDGPUResourceUsageAnalysis.cpp
AMDGPURewriteOutArguments.cpp
AMDGPURewriteUndefForPHI.cpp
+ AMDGPUSelectionDAGInfo.cpp
AMDGPUSetWavePriority.cpp
AMDGPUSplitModule.cpp
AMDGPUSubtarget.cpp
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
index 51361b75940560..117afc4a8e8c60 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
@@ -16,6 +16,7 @@
#include "AMDGPUInstructionSelector.h"
#include "AMDGPULegalizerInfo.h"
#include "AMDGPURegisterBankInfo.h"
+#include "AMDGPUSelectionDAGInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
@@ -185,6 +186,9 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
// clang-format on
MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this);
EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(this);
+
+ TSInfo = std::make_unique<AMDGPUSelectionDAGInfo>();
+
CallLoweringInfo = std::make_unique<AMDGPUCallLowering>(*getTargetLowering());
InlineAsmLoweringInfo =
std::make_unique<InlineAsmLowering>(getTargetLowering());
@@ -194,6 +198,10 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
std::make_unique<AMDGPUInstructionSelector>(*this, *RegBankInfo, TM);
}
+const SelectionDAGTargetInfo *GCNSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
+
unsigned GCNSubtarget::getConstantBusLimit(unsigned Opcode) const {
if (getGeneration() < GFX10)
return 1;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 5cecaf6349c883..3388bc3c5a8de1 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -21,7 +21,6 @@
#include "SIISelLowering.h"
#include "SIInstrInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/Support/ErrorHandling.h"
#define GET_SUBTARGETINFO_HEADER
@@ -49,6 +48,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
};
private:
+ /// SelectionDAGISel related APIs.
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
+
/// GlobalISel related APIs.
std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
@@ -257,7 +259,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// Dummy feature to use for assembler in tablegen.
bool FeatureDisable = false;
- SelectionDAGTargetInfo TSInfo;
private:
SIInstrInfo InstrInfo;
SITargetLowering TLInfo;
@@ -291,6 +292,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return &InstrInfo.getRegisterInfo();
}
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
+
const CallLowering *getCallLowering() const override {
return CallLoweringInfo.get();
}
@@ -315,11 +318,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return TargetID;
}
- // Nothing implemented, just prevent crashes on use.
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
-
const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins;
}
diff --git a/llvm/lib/Target/AMDGPU/R600Subtarget.cpp b/llvm/lib/Target/AMDGPU/R600Subtarget.cpp
index fd5a87999cf81b..77fbd416955c23 100644
--- a/llvm/lib/Target/AMDGPU/R600Subtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/R600Subtarget.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "R600Subtarget.h"
+#include "AMDGPUSelectionDAGInfo.h"
#include "MCTargetDesc/R600MCTargetDesc.h"
using namespace llvm;
@@ -30,6 +31,13 @@ R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
TLInfo(TM, initializeSubtargetDependencies(TT, GPU, FS)),
InstrItins(getInstrItineraryForCPU(GPU)) {
LocalMemorySize = AddressableLocalMemorySize;
+ TSInfo = std::make_unique<AMDGPUSelectionDAGInfo>();
+}
+
+R600Subtarget::~R600Subtarget() = default;
+
+const SelectionDAGTargetInfo *R600Subtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
}
R600Subtarget &R600Subtarget::initializeSubtargetDependencies(const Triple &TT,
diff --git a/llvm/lib/Target/AMDGPU/R600Subtarget.h b/llvm/lib/Target/AMDGPU/R600Subtarget.h
index 7f0f9305e1fa6c..22e56b66e18277 100644
--- a/llvm/lib/Target/AMDGPU/R600Subtarget.h
+++ b/llvm/lib/Target/AMDGPU/R600Subtarget.h
@@ -19,7 +19,6 @@
#include "R600ISelLowering.h"
#include "R600InstrInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#define GET_SUBTARGETINFO_HEADER
#include "R600GenSubtargetInfo.inc"
@@ -41,12 +40,14 @@ class R600Subtarget final : public R600GenSubtargetInfo,
Generation Gen = R600;
R600TargetLowering TLInfo;
InstrItineraryData InstrItins;
- SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
public:
R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM);
+ ~R600Subtarget() override;
+
const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
const R600FrameLowering *getFrameLowering() const override {
@@ -65,10 +66,7 @@ class R600Subtarget final : public R600GenSubtargetInfo,
return &InstrItins;
}
- // Nothing implemented, just prevent crashes on use.
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt
index 28f66a4ad94826..21d1765107ae6f 100644
--- a/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/CMakeLists.txt
@@ -58,6 +58,7 @@ add_llvm_target(MipsCodeGen
MipsSEISelDAGToDAG.cpp
MipsSEISelLowering.cpp
MipsSERegisterInfo.cpp
+ MipsSelectionDAGInfo.cpp
MipsSubtarget.cpp
MipsTargetMachine.cpp
MipsTargetObjectFile.cpp
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..c24107bf639434
--- /dev/null
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "MipsSelectionDAGInfo.h"
+
+using namespace llvm;
+
+MipsSelectionDAGInfo::~MipsSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
new file mode 100644
index 00000000000000..bccd924a30e711
--- /dev/null
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class MipsSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~MipsSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index cafb20f983f1f5..2210eca9eb1051 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -16,6 +16,7 @@
#include "MipsLegalizerInfo.h"
#include "MipsRegisterBankInfo.h"
#include "MipsRegisterInfo.h"
+#include "MipsSelectionDAGInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
@@ -78,13 +79,14 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
- HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 || Mips_Os16),
- Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
- HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
- HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false), StrictAlign(false),
+ HasDSPR2(false), HasDSPR3(false),
+ AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
+ UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
+ HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
+ UseIndirectJumpsHazard(false), StrictAlign(false),
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
- TSInfo(), InstrInfo(MipsInstrInfo::create(
- initializeSubtargetDependencies(CPU, FS, TM))),
+ InstrInfo(
+ MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
FrameLowering(MipsFrameLowering::create(*this)),
TLInfo(MipsTargetLowering::create(TM, *this)) {
@@ -211,6 +213,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
GINVWarningPrinted = true;
}
+ TSInfo = std::make_unique<MipsSelectionDAGInfo>();
+
CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
Legalizer.reset(new MipsLegalizerInfo(*this));
@@ -219,6 +223,8 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
InstSelector.reset(createMipsInstructionSelector(TM, *this, *RBI));
}
+MipsSubtarget::~MipsSubtarget() = default;
+
bool MipsSubtarget::isPositionIndependent() const {
return TM.isPositionIndependent();
}
@@ -280,6 +286,10 @@ bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
+const SelectionDAGTargetInfo *MipsSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
+
const CallLowering *MipsSubtarget::getCallLowering() const {
return CallLoweringInfo.get();
}
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index fea7f11fd07054..c048ab29d5f9b2 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -21,7 +21,6 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/RegisterBankInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCInstrItineraries.h"
@@ -220,7 +219,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Triple TargetTriple;
- const SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
std::unique_ptr<const MipsInstrInfo> InstrInfo;
std::unique_ptr<const MipsFrameLowering> FrameLowering;
std::unique_ptr<const MipsTargetLowering> TLInfo;
@@ -243,6 +242,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
+ ~MipsSubtarget() override;
+
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
@@ -383,9 +384,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
void setHelperClassesMips16();
void setHelperClassesMipsSE();
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
+
const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
const TargetFrameLowering *getFrameLowering() const override {
return FrameLowering.get();
diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt
index 693365161330f5..dfbda845347322 100644
--- a/llvm/lib/Target/NVPTX/CMakeLists.txt
+++ b/llvm/lib/Target/NVPTX/CMakeLists.txt
@@ -31,6 +31,7 @@ set(NVPTXCodeGen_sources
NVPTXPrologEpilogPass.cpp
NVPTXRegisterInfo.cpp
NVPTXReplaceImageHandles.cpp
+ NVPTXSelectionDAGInfo.cpp
NVPTXSubtarget.cpp
NVPTXTargetMachine.cpp
NVPTXTargetTransformInfo.cpp
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..9c26f310bbf653
--- /dev/null
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "NVPTXSelectionDAGInfo.h"
+
+using namespace llvm;
+
+NVPTXSelectionDAGInfo::~NVPTXSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
new file mode 100644
index 00000000000000..6b04d78ca96878
--- /dev/null
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class NVPTXSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~NVPTXSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_NVPTX_NVPTXSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index 0e6b75e622c6ad..34571465aea6f0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "NVPTXSubtarget.h"
+#include "NVPTXSelectionDAGInfo.h"
#include "NVPTXTargetMachine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormatVariadic.h"
@@ -56,7 +57,15 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
FullSmVersion(200), SmVersion(getSmVersion()), TM(TM),
- TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}
+ TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {
+ TSInfo = std::make_unique<NVPTXSelectionDAGInfo>();
+}
+
+NVPTXSubtarget::~NVPTXSubtarget() = default;
+
+const SelectionDAGTargetInfo *NVPTXSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
bool NVPTXSubtarget::hasImageHandles() const {
// Enable handles for Kepler+, where CUDA supports indirect surfaces and
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index e785bbf830da62..2a2b98dd4fb6af 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -18,7 +18,6 @@
#include "NVPTXISelLowering.h"
#include "NVPTXInstrInfo.h"
#include "NVPTXRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include <string>
@@ -46,7 +45,7 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
const NVPTXTargetMachine &TM;
NVPTXInstrInfo InstrInfo;
NVPTXTargetLowering TLInfo;
- SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
// NVPTX does not have any call stack frame, but need a NVPTX specific
// FrameLowering class because TargetFrameLowering is abstract.
@@ -59,6 +58,8 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const NVPTXTargetMachine &TM);
+ ~NVPTXSubtarget() override;
+
const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
@@ -69,9 +70,8 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
const NVPTXTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
bool hasAtomAddF64() const { return SmVersion >= 60; }
bool hasAtomScope() const { return SmVersion >= 60; }
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index 8f7b53b622065d..3808a26a0b92a0 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -43,6 +43,7 @@ add_llvm_target(PowerPCCodeGen
PPCMacroFusion.cpp
PPCMIPeephole.cpp
PPCRegisterInfo.cpp
+ PPCSelectionDAGInfo.cpp
PPCSubtarget.cpp
PPCTargetMachine.cpp
PPCTargetObjectFile.cpp
diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..211aaff3cfa0ea
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPCSelectionDAGInfo.h"
+
+using namespace llvm;
+
+PPCSelectionDAGInfo::~PPCSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
new file mode 100644
index 00000000000000..cc14e9b0a69043
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_POWERPC_PPCSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_POWERPC_PPCSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class PPCSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~PPCSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_POWERPC_PPCSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 57b650575a8984..75a0272af7c312 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -16,6 +16,7 @@
#include "GISel/PPCRegisterBankInfo.h"
#include "PPC.h"
#include "PPCRegisterInfo.h"
+#include "PPCSelectionDAGInfo.h"
#include "PPCTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
@@ -59,6 +60,8 @@ PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
TargetTriple.getArch() == Triple::ppc64le),
TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
InstrInfo(*this), TLInfo(TM, *this) {
+ TSInfo = std::make_unique<PPCSelectionDAGInfo>();
+
CallLoweringInfo.reset(new PPCCallLowering(*getTargetLowering()));
Legalizer.reset(new PPCLegalizerInfo(*this));
auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
@@ -67,6 +70,12 @@ PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI));
}
+PPCSubtarget::~PPCSubtarget() = default;
+
+const SelectionDAGTargetInfo *PPCSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
+
void PPCSubtarget::initializeEnvironment() {
StackAlignment = Align(16);
CPUDirective = PPC::DIR_NONE;
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index f6ace4daa336bf..b8714f8f587e6f 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -19,7 +19,6 @@
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/RegisterBankInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCInstrItineraries.h"
@@ -33,6 +32,7 @@
#undef PPC
namespace llvm {
+class SelectionDAGTargetInfo;
class StringRef;
namespace PPC {
@@ -105,7 +105,9 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
PPCFrameLowering FrameLowering;
PPCInstrInfo InstrInfo;
PPCTargetLowering TLInfo;
- SelectionDAGTargetInfo TSInfo;
+
+ // SelectionDAGISel related APIs.
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
/// GlobalISel related APIs.
std::unique_ptr<CallLowering> CallLoweringInfo;
@@ -121,6 +123,8 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
const std::string &TuneCPU, const std::string &FS,
const PPCTargetMachine &TM);
+ ~PPCSubtarget();
+
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
@@ -147,9 +151,9 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
const PPCTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
+
const PPCRegisterInfo *getRegisterInfo() const override {
return &getInstrInfo()->getRegisterInfo();
}
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index b95ad9dd428cc9..44661647a86310 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -54,6 +54,7 @@ add_llvm_target(RISCVCodeGen
RISCVMoveMerger.cpp
RISCVPushPopOptimizer.cpp
RISCVRegisterInfo.cpp
+ RISCVSelectionDAGInfo.cpp
RISCVSubtarget.cpp
RISCVTargetMachine.cpp
RISCVTargetObjectFile.cpp
diff --git a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
new file mode 100644
index 00000000000000..19d6138609a2ba
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
@@ -0,0 +1,13 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVSelectionDAGInfo.h"
+
+using namespace llvm;
+
+RISCVSelectionDAGInfo::~RISCVSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
new file mode 100644
index 00000000000000..7543d8b493cebf
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
@@ -0,0 +1,23 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+namespace llvm {
+
+class RISCVSelectionDAGInfo : public SelectionDAGTargetInfo {
+public:
+ ~RISCVSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 38443e8646de40..6bd7a1245bf6dd 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -15,6 +15,7 @@
#include "GISel/RISCVLegalizerInfo.h"
#include "RISCV.h"
#include "RISCVFrameLowering.h"
+#include "RISCVSelectionDAGInfo.h"
#include "RISCVTargetMachine.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MacroFusion.h"
@@ -97,7 +98,15 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
FrameLowering(
initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
- InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+ InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
+ TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
+}
+
+RISCVSubtarget::~RISCVSubtarget() = default;
+
+const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
const CallLowering *RISCVSubtarget::getCallLowering() const {
if (!CallLoweringInfo)
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 9a1881c2d39837..c93b06c3e0d5a7 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -21,7 +21,6 @@
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
@@ -102,7 +101,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
RISCVInstrInfo InstrInfo;
RISCVRegisterInfo RegInfo;
RISCVTargetLowering TLInfo;
- SelectionDAGTargetInfo TSInfo;
/// Initializes using the passed in CPU and feature strings so that we can
/// use initializer lists for subtarget initialization.
@@ -118,6 +116,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
unsigned RVVVectorLMULMax, const TargetMachine &TM);
+ ~RISCVSubtarget() override;
+
// Parses features string setting specified subtarget options. The
// definition of this function is auto-generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
@@ -132,9 +132,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
const RISCVTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+
bool enableMachineScheduler() const override { return true; }
bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
@@ -284,6 +282,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
}
protected:
+ // SelectionDAGISel related APIs.
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
+
// GlobalISel related APIs.
mutable std::unique_ptr<CallLowering> CallLoweringInfo;
mutable std::unique_ptr<InstructionSelector> InstSelector;
@@ -298,6 +299,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMinRVVVectorSizeInBits() const;
public:
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
const CallLowering *getCallLowering() const override;
InstructionSelector *getInstructionSelector() const override;
const LegalizerInfo *getLegalizerInfo() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index 5506196c3c7e86..b1610e3f81eba7 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -16,7 +16,6 @@
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include <optional>
>From 7f87dace4c3a70ca9e937fe93f780ad43cbddcd8 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Wed, 13 Nov 2024 21:26:38 +0300
Subject: [PATCH 2/2] [CodeGen] Virtualize isTargetStrictFPOpcode /
isTargetMemoryOpcode
---
llvm/include/llvm/CodeGen/ISDOpcodes.h | 11 ------
llvm/include/llvm/CodeGen/SelectionDAG.h | 4 +-
llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 29 ++-------------
.../llvm/CodeGen/SelectionDAGTargetInfo.h | 13 +++++++
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +++---
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 7 +++-
.../SelectionDAG/SelectionDAGTargetInfo.cpp | 6 +++
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 6 ++-
.../AArch64/AArch64SelectionDAGInfo.cpp | 20 ++++++++++
.../Target/AArch64/AArch64SelectionDAGInfo.h | 4 ++
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 -
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 6 ++-
.../Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp | 8 ++++
.../Target/AMDGPU/AMDGPUSelectionDAGInfo.h | 2 +
llvm/lib/Target/ARM/ARMISelLowering.h | 6 ++-
llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp | 7 ++++
llvm/lib/Target/ARM/ARMSelectionDAGInfo.h | 2 +
llvm/lib/Target/Mips/MipsISelLowering.h | 2 +-
llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp | 18 +++++++++
llvm/lib/Target/Mips/MipsSelectionDAGInfo.h | 2 +
llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 6 ++-
.../Target/NVPTX/NVPTXSelectionDAGInfo.cpp | 8 ++++
llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h | 2 +
llvm/lib/Target/PowerPC/PPCISelLowering.h | 21 +++++------
.../Target/PowerPC/PPCSelectionDAGInfo.cpp | 26 +++++++++++++
llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h | 4 ++
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 37 +++++++++----------
llvm/lib/Target/RISCV/RISCVISelLowering.h | 11 ++----
.../Target/RISCV/RISCVSelectionDAGInfo.cpp | 22 +++++++++++
llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h | 4 ++
llvm/lib/Target/SystemZ/SystemZISelLowering.h | 8 ++--
.../SystemZ/SystemZSelectionDAGInfo.cpp | 26 +++++++++++++
.../Target/SystemZ/SystemZSelectionDAGInfo.h | 4 ++
.../lib/Target/WebAssembly/WebAssemblyISD.def | 8 ++--
.../WebAssembly/WebAssemblyISelLowering.cpp | 3 --
.../WebAssembly/WebAssemblyISelLowering.h | 8 ----
.../WebAssemblySelectionDAGInfo.cpp | 13 +++++++
.../WebAssembly/WebAssemblySelectionDAGInfo.h | 3 ++
llvm/lib/Target/X86/X86ISelLowering.cpp | 8 +++-
llvm/lib/Target/X86/X86ISelLowering.h | 15 +++-----
llvm/lib/Target/X86/X86SelectionDAGInfo.cpp | 14 +++++++
llvm/lib/Target/X86/X86SelectionDAGInfo.h | 4 ++
42 files changed, 299 insertions(+), 122 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 0b6d155b6d161e..69820aed2137b5 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -1490,17 +1490,6 @@ enum NodeType {
BUILTIN_OP_END
};
-/// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations
-/// which cannot raise FP exceptions should be less than this value.
-/// Those that do must not be less than this value.
-static const int FIRST_TARGET_STRICTFP_OPCODE = BUILTIN_OP_END + 400;
-
-/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
-/// which do not reference a specific memory location should be less than
-/// this value. Those that do must not be less than this value, and can
-/// be used with SelectionDAG::getMemIntrinsicNode.
-static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END + 500;
-
/// Whether this is bitwise logic opcode.
inline bool isBitwiseLogicOp(unsigned Opcode) {
return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index e97e01839f73b4..27cc1a2f963519 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1327,8 +1327,8 @@ class SelectionDAG {
/// Creates a MemIntrinsicNode that may produce a
/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
- /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
- /// less than FIRST_TARGET_MEMORY_OPCODE.
+ /// INTRINSIC_W_CHAIN, or a target-specific memory-referencing opcode
+ // (see `SelectionDAGTargetInfo::isTargetMemoryOpcode`).
SDValue getMemIntrinsicNode(
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 61f3c6329efce8..46d8ae442bf2a2 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -210,7 +210,6 @@ class SDValue {
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline const APInt &getConstantOperandAPInt(unsigned i) const;
- inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline bool isUndef() const;
@@ -688,22 +687,6 @@ END_TWO_BYTE_PACK()
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
- /// Test if this node has a target-specific opcode that may raise
- /// FP exceptions (in the \<target\>ISD namespace and greater than
- /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
- /// opcode are currently automatically considered to possibly raise
- /// FP exceptions as well.
- bool isTargetStrictFPOpcode() const {
- return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
- }
-
- /// Test if this node has a target-specific
- /// memory-referencing opcode (in the \<target\>ISD namespace and
- /// greater than FIRST_TARGET_MEMORY_OPCODE).
- bool isTargetMemoryOpcode() const {
- return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
- }
-
/// Return true if the type of the node type undefined.
bool isUndef() const { return NodeType == ISD::UNDEF; }
@@ -1214,10 +1197,6 @@ inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
}
-inline bool SDValue::isTargetMemoryOpcode() const {
- return Node->isTargetMemoryOpcode();
-}
-
inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
}
@@ -1571,10 +1550,10 @@ class AtomicSDNode : public MemSDNode {
}
};
-/// This SDNode is used for target intrinsics that touch
-/// memory and need an associated MachineMemOperand. Its opcode may be
-/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
-/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
+/// This SDNode is used for target intrinsics that touch memory and need
+/// an associated MachineMemOperand. Its opcode may be INTRINSIC_VOID,
+/// INTRINSIC_W_CHAIN, PREFETCH, or a target-specific memory-referencing
+/// opcode (see `SelectionDAGTargetInfo::isTargetMemoryOpcode`).
class MemIntrinsicSDNode : public MemSDNode {
public:
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
index 720c9463867c34..ef5ae5dba58de4 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
@@ -35,6 +35,19 @@ class SelectionDAGTargetInfo {
SelectionDAGTargetInfo &operator=(const SelectionDAGTargetInfo &) = delete;
virtual ~SelectionDAGTargetInfo();
+ /// Returns true if a node with the given target-specific opcode has
+ /// a memory operand. Nodes with such opcodes can only be created with
+ /// `SelectionDAG::getMemIntrinsicNode`.
+ virtual bool isTargetMemoryOpcode(unsigned Opcode) const { return false; }
+
+ /// Returns true if a node with the given target-specific opcode has
+ /// strict floating-point semantics.
+ virtual bool isTargetStrictFPOpcode(unsigned Opcode) const { return false; }
+
+ /// Returns true if a node with the given target-specific opcode
+ /// may raise a floating-point exception.
+ virtual bool mayRaiseFPException(unsigned Opcode) const;
+
/// Emit target-specific code that performs a memcpy.
/// This can be used by targets to provide code sequences for cases
/// that don't fit the target's parameters for simple loads/stores and can be
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 34214550f3a12b..9d6430e697f241 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -8978,12 +8978,12 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
SDVTList VTList,
ArrayRef<SDValue> Ops, EVT MemVT,
MachineMemOperand *MMO) {
- assert((Opcode == ISD::INTRINSIC_VOID ||
- Opcode == ISD::INTRINSIC_W_CHAIN ||
- Opcode == ISD::PREFETCH ||
- (Opcode <= (unsigned)std::numeric_limits<int>::max() &&
- (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
- "Opcode is not a memory-accessing opcode!");
+ assert(
+ (Opcode == ISD::INTRINSIC_VOID || Opcode == ISD::INTRINSIC_W_CHAIN ||
+ Opcode == ISD::PREFETCH ||
+ (Opcode <= (unsigned)std::numeric_limits<int>::max() &&
+ Opcode >= ISD::BUILTIN_OP_END && TSI->isTargetMemoryOpcode(Opcode))) &&
+ "Opcode is not a memory-accessing opcode!");
// Memoize the node unless it returns a glue result.
MemIntrinsicSDNode *N;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 3000dfda1bea03..e897b4fac9af9a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -51,6 +51,7 @@
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/SwiftErrorValueTracking.h"
@@ -4394,8 +4395,10 @@ bool SelectionDAGISel::mayRaiseFPException(SDNode *N) const {
// For ISD opcodes, only StrictFP opcodes may raise an FP
// exception.
- if (N->isTargetOpcode())
- return N->isTargetStrictFPOpcode();
+ if (N->isTargetOpcode()) {
+ const SelectionDAGTargetInfo &TSI = CurDAG->getSelectionDAGInfo();
+ return TSI.mayRaiseFPException(N->getOpcode());
+ }
return N->isStrictFPOpcode();
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
index 3a2df6f60593a9..0f3b36658f10ad 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp
@@ -15,3 +15,9 @@
using namespace llvm;
SelectionDAGTargetInfo::~SelectionDAGTargetInfo() = default;
+
+bool SelectionDAGTargetInfo::mayRaiseFPException(unsigned Opcode) const {
+ // FIXME: All target memory opcodes are currently automatically considered
+ // to possibly raise FP exceptions. See rev. 63336795.
+ return isTargetStrictFPOpcode(Opcode) || isTargetMemoryOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index d51b36f7e49946..835c9381834724 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -477,7 +477,7 @@ enum NodeType : unsigned {
MSRR,
// Strict (exception-raising) floating point comparison
- STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ STRICT_FCMP,
STRICT_FCMPE,
// SME ZA loads and stores
@@ -485,7 +485,8 @@ enum NodeType : unsigned {
SME_ZA_STR,
// NEON Load/Store with post-increment base updates
- LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ LD2post = FIRST_MEMORY_OPCODE,
LD3post,
LD4post,
ST2post,
@@ -520,6 +521,7 @@ enum NodeType : unsigned {
STP,
STILP,
STNP,
+ LAST_MEMORY_OPCODE = STNP,
};
} // end namespace AArch64ISD
diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
index c4d60a0cb4a118..f06c15ccb50755 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
@@ -23,6 +23,26 @@ static cl::opt<bool>
"to lower to librt functions"),
cl::init(true));
+bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= AArch64ISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
+bool AArch64SelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
+ switch (static_cast<AArch64ISD::NodeType>(Opcode)) {
+ default:
+ break;
+ case AArch64ISD::STRICT_FCMP:
+ case AArch64ISD::STRICT_FCMPE:
+ case AArch64ISD::SME_ZA_LDR:
+ case AArch64ISD::SME_ZA_STR:
+ return true;
+ }
+ return SelectionDAGTargetInfo::isTargetStrictFPOpcode(Opcode);
+}
+
SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
const SDLoc &DL, SDValue Chain,
SDValue Dst, SDValue SrcOrValue,
diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
index 9d1f2e9cba846a..7efe49c7206555 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
@@ -19,6 +19,10 @@ namespace llvm {
class AArch64SelectionDAGInfo : public SelectionDAGTargetInfo {
public:
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
+ bool isTargetStrictFPOpcode(unsigned Opcode) const override;
+
SDValue EmitMOPS(unsigned Opcode, SelectionDAG &DAG, const SDLoc &DL,
SDValue Chain, SDValue Dst, SDValue SrcOrValue, SDValue Size,
Align Alignment, bool isVolatile,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 48e9af9fe507fb..f76acfe12e2953 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5555,7 +5555,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(PC_ADD_REL_OFFSET)
NODE_NAME_CASE(LDS)
NODE_NAME_CASE(DUMMY_CHAIN)
- case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
NODE_NAME_CASE(LOAD_D16_HI)
NODE_NAME_CASE(LOAD_D16_LO)
NODE_NAME_CASE(LOAD_D16_HI_I8)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 33991239a41209..c74dc7942f52c0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -546,8 +546,9 @@ enum NodeType : unsigned {
LDS,
DUMMY_CHAIN,
- FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
- LOAD_D16_HI,
+
+ FIRST_MEMORY_OPCODE,
+ LOAD_D16_HI = FIRST_MEMORY_OPCODE,
LOAD_D16_LO,
LOAD_D16_HI_I8,
LOAD_D16_HI_U8,
@@ -603,6 +604,7 @@ enum NodeType : unsigned {
BUFFER_ATOMIC_FMIN,
BUFFER_ATOMIC_FMAX,
BUFFER_ATOMIC_COND_SUB_U32,
+ LAST_MEMORY_OPCODE = BUFFER_ATOMIC_COND_SUB_U32,
};
} // End namespace AMDGPUISD
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
index 7bc651504e36d4..150c5aa33be92e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
@@ -7,7 +7,15 @@
//===----------------------------------------------------------------------===//
#include "AMDGPUSelectionDAGInfo.h"
+#include "AMDGPUISelLowering.h"
using namespace llvm;
AMDGPUSelectionDAGInfo::~AMDGPUSelectionDAGInfo() = default;
+
+bool AMDGPUSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= AMDGPUISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= AMDGPUISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
index bb11a56da52596..3280be73b2fdf1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
@@ -16,6 +16,8 @@ namespace llvm {
class AMDGPUSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~AMDGPUSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 4fa600e0cfcc40..cd663cebeab01f 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -321,7 +321,8 @@ class VectorType;
CSINC, // Conditional select increment.
// Vector load N-element structure to all lanes:
- VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ VLD1DUP = FIRST_MEMORY_OPCODE,
VLD2DUP,
VLD3DUP,
VLD4DUP,
@@ -356,7 +357,8 @@ class VectorType;
// Load/Store of dual registers
LDRD,
- STRD
+ STRD,
+ LAST_MEMORY_OPCODE = STRD,
};
} // end namespace ARMISD
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
index e7ea10ff971a0c..24972636adb960 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
@@ -30,6 +30,13 @@ cl::opt<TPLoop::MemTransfer> EnableMemtransferTPLoop(
"Allow (may be subject to certain conditions) "
"conversion of memcpy to TP loop.")));
+bool ARMSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= ARMISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= ARMISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
// Emit, if possible, a specialized version of the given Libcall. Typically this
// means selecting the appropriately aligned version, but we also convert memset
// of 0 into memclr.
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
index 275b1c0f8dc017..d68150e66567ce 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
@@ -37,6 +37,8 @@ namespace ARM_AM {
class ARMSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment,
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index e245c056de6491..ae56bf7c8a2e72 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -247,7 +247,7 @@ class TargetRegisterClass;
DOUBLE_SELECT_I64,
// Load/Store Left/Right nodes.
- LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ LWL,
LWR,
SWL,
SWR,
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
index c24107bf639434..8120e35570f65b 100644
--- a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp
@@ -7,7 +7,25 @@
//===----------------------------------------------------------------------===//
#include "MipsSelectionDAGInfo.h"
+#include "MipsISelLowering.h"
using namespace llvm;
MipsSelectionDAGInfo::~MipsSelectionDAGInfo() = default;
+
+bool MipsSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ switch (static_cast<MipsISD::NodeType>(Opcode)) {
+ default:
+ break;
+ case MipsISD::LWL:
+ case MipsISD::LWR:
+ case MipsISD::SWL:
+ case MipsISD::SWR:
+ case MipsISD::LDL:
+ case MipsISD::LDR:
+ case MipsISD::SDL:
+ case MipsISD::SDR:
+ return true;
+ }
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
index bccd924a30e711..934cd2e056595d 100644
--- a/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
+++ b/llvm/lib/Target/Mips/MipsSelectionDAGInfo.h
@@ -16,6 +16,8 @@ namespace llvm {
class MipsSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~MipsSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
index c8b589ae39413e..f7c59973f8d1a5 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h
@@ -70,7 +70,8 @@ enum NodeType : unsigned {
BrxEnd,
Dummy,
- LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ LoadV2 = FIRST_MEMORY_OPCODE,
LoadV4,
LDUV2, // LDU.v2
LDUV4, // LDU.v4
@@ -443,7 +444,8 @@ enum NodeType : unsigned {
Suld3DV2I64Zero,
Suld3DV4I8Zero,
Suld3DV4I16Zero,
- Suld3DV4I32Zero
+ Suld3DV4I32Zero,
+ LAST_MEMORY_OPCODE = Suld3DV4I32Zero,
};
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
index 9c26f310bbf653..5470f9e7fd9d47 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp
@@ -7,7 +7,15 @@
//===----------------------------------------------------------------------===//
#include "NVPTXSelectionDAGInfo.h"
+#include "NVPTXISelLowering.h"
using namespace llvm;
NVPTXSelectionDAGInfo::~NVPTXSelectionDAGInfo() = default;
+
+bool NVPTXSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= NVPTXISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= NVPTXISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
index 6b04d78ca96878..9d69f48026c790 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h
@@ -16,6 +16,8 @@ namespace llvm {
class NVPTXSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~NVPTXSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 8f41fc107a6918..7ee1b9bbbce511 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -36,14 +36,11 @@ namespace llvm {
namespace PPCISD {
- // When adding a NEW PPCISD node please add it to the correct position in
- // the enum. The order of elements in this enum matters!
- // Values that are added after this entry:
- // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
- // are considered memory opcodes and are treated differently than entries
- // that come before it. For example, ADD or MUL should be placed before
- // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
- // after it.
+ // When adding a NEW PPCISD node please add it to the correct position in
+ // the enum. The order of elements in this enum matters!
+ // Values that are added between FIRST_MEMORY_OPCODE and LAST_MEMORY_OPCODE
+ // are considered memory opcodes and are treated differently than other
+ // entries.
enum NodeType : unsigned {
// Start the numbering where the builtin ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END,
@@ -487,7 +484,7 @@ namespace llvm {
XXMFACC,
// Constrained conversion from floating point to int
- STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ STRICT_FCTIDZ,
STRICT_FCTIWZ,
STRICT_FCTIDUZ,
STRICT_FCTIWUZ,
@@ -516,7 +513,8 @@ namespace llvm {
/// byte-swapping store instruction. It byte-swaps the low "Type" bits of
/// the GPRC input, then stores it through Ptr. Type can be either i16 or
/// i32.
- STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ STBRX = FIRST_MEMORY_OPCODE,
/// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
/// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
@@ -607,7 +605,8 @@ namespace llvm {
/// GPRC = TOC_ENTRY GA, TOC
/// Loads the entry for GA from the TOC, where the TOC base is given by
/// the last operand.
- TOC_ENTRY
+ TOC_ENTRY,
+ LAST_MEMORY_OPCODE = TOC_ENTRY,
};
} // end namespace PPCISD
diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
index 211aaff3cfa0ea..9fdc0e85f8f041 100644
--- a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp
@@ -7,7 +7,33 @@
//===----------------------------------------------------------------------===//
#include "PPCSelectionDAGInfo.h"
+#include "PPCISelLowering.h"
using namespace llvm;
PPCSelectionDAGInfo::~PPCSelectionDAGInfo() = default;
+
+bool PPCSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= PPCISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= PPCISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
+bool PPCSelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
+ switch (static_cast<PPCISD::NodeType>(Opcode)) {
+ default:
+ break;
+ case PPCISD::STRICT_FCTIDZ:
+ case PPCISD::STRICT_FCTIWZ:
+ case PPCISD::STRICT_FCTIDUZ:
+ case PPCISD::STRICT_FCTIWUZ:
+ case PPCISD::STRICT_FCFID:
+ case PPCISD::STRICT_FCFIDU:
+ case PPCISD::STRICT_FCFIDS:
+ case PPCISD::STRICT_FCFIDUS:
+ case PPCISD::STRICT_FADDRTZ:
+ return true;
+ }
+ return SelectionDAGTargetInfo::isTargetStrictFPOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
index cc14e9b0a69043..08e2ddbf1c4ca7 100644
--- a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h
@@ -16,6 +16,10 @@ namespace llvm {
class PPCSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~PPCSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
+ bool isTargetStrictFPOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 096b9fa79173fe..3b38737a4e48a5 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17,6 +17,7 @@
#include "RISCVConstantPoolValue.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVRegisterInfo.h"
+#include "RISCVSelectionDAGInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
@@ -6392,14 +6393,12 @@ static unsigned getRISCVVLOp(SDValue Op) {
/// Return true if a RISC-V target specified op has a passthru operand.
static bool hasPassthruOp(unsigned Opcode) {
assert(Opcode > RISCVISD::FIRST_NUMBER &&
- Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
+ Opcode <= RISCVISD::LAST_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
- static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP ==
- 127 &&
- RISCVISD::LAST_RISCV_STRICTFP_OPCODE -
- ISD::FIRST_TARGET_STRICTFP_OPCODE ==
- 21 &&
- "adding target specific op should update this function");
+ static_assert(
+ RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 127 &&
+ RISCVISD::LAST_STRICTFP_OPCODE - RISCVISD::FIRST_STRICTFP_OPCODE == 21 &&
+ "adding target specific op should update this function");
if (Opcode >= RISCVISD::ADD_VL && Opcode <= RISCVISD::VFMAX_VL)
return true;
if (Opcode == RISCVISD::FCOPYSIGN_VL)
@@ -6418,14 +6417,12 @@ static bool hasPassthruOp(unsigned Opcode) {
/// Return true if a RISC-V target specified op has a mask operand.
static bool hasMaskOp(unsigned Opcode) {
assert(Opcode > RISCVISD::FIRST_NUMBER &&
- Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
+ Opcode <= RISCVISD::LAST_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
- static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP ==
- 127 &&
- RISCVISD::LAST_RISCV_STRICTFP_OPCODE -
- ISD::FIRST_TARGET_STRICTFP_OPCODE ==
- 21 &&
- "adding target specific op should update this function");
+ static_assert(
+ RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == 127 &&
+ RISCVISD::LAST_STRICTFP_OPCODE - RISCVISD::FIRST_STRICTFP_OPCODE == 21 &&
+ "adding target specific op should update this function");
if (Opcode >= RISCVISD::TRUNCATE_VECTOR_VL && Opcode <= RISCVISD::SETCC_VL)
return true;
if (Opcode >= RISCVISD::VRGATHER_VX_VL && Opcode <= RISCVISD::VFIRST_VL)
@@ -15920,7 +15917,7 @@ static SDValue performFP_TO_INTCombine(SDNode *N,
SDValue Src = N->getOperand(0);
// Don't do this for strict-fp Src.
- if (Src->isStrictFPOpcode() || Src->isTargetStrictFPOpcode())
+ if (Src->isStrictFPOpcode())
return SDValue();
// Ensure the FP type is legal.
@@ -16025,7 +16022,7 @@ static SDValue performFP_TO_INT_SATCombine(SDNode *N,
SDValue Src = N->getOperand(0);
// Don't do this for strict-fp Src.
- if (Src->isStrictFPOpcode() || Src->isTargetStrictFPOpcode())
+ if (Src->isStrictFPOpcode())
return SDValue();
// Ensure the FP type is also legal.
@@ -16133,7 +16130,9 @@ static unsigned negateFMAOpcode(unsigned Opcode, bool NegMul, bool NegAcc) {
static SDValue combineVFMADD_VLWithVFNEG_VL(SDNode *N, SelectionDAG &DAG) {
// Fold FNEG_VL into FMA opcodes.
// The first operand of strict-fp is chain.
- unsigned Offset = N->isTargetStrictFPOpcode();
+ bool IsStrict =
+ DAG.getSelectionDAGInfo().isTargetStrictFPOpcode(N->getOpcode());
+ unsigned Offset = IsStrict ? 1 : 0;
SDValue A = N->getOperand(0 + Offset);
SDValue B = N->getOperand(1 + Offset);
SDValue C = N->getOperand(2 + Offset);
@@ -16160,7 +16159,7 @@ static SDValue combineVFMADD_VLWithVFNEG_VL(SDNode *N, SelectionDAG &DAG) {
return SDValue();
unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), NegA != NegB, NegC);
- if (N->isTargetStrictFPOpcode())
+ if (IsStrict)
return DAG.getNode(NewOpcode, SDLoc(N), N->getVTList(),
{N->getOperand(0), A, B, C, Mask, VL});
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
@@ -16176,7 +16175,7 @@ static SDValue performVFMADD_VLCombine(SDNode *N,
return V;
// FIXME: Ignore strict opcodes for now.
- if (N->isTargetStrictFPOpcode())
+ if (DAG.getSelectionDAGInfo().isTargetStrictFPOpcode(N->getOpcode()))
return SDValue();
return combineOp_VLToVWOp_VL(N, DCI, Subtarget);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 778e38a1a834ee..3e9e2ca67f645b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -467,7 +467,8 @@ enum NodeType : unsigned {
// FP to 32 bit int conversions for RV64. These are used to keep track of the
// result being sign extended to 64 bit. These saturate out of range inputs.
- STRICT_FCVT_W_RV64 = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ FIRST_STRICTFP_OPCODE,
+ STRICT_FCVT_W_RV64 = FIRST_STRICTFP_OPCODE,
STRICT_FCVT_WU_RV64,
STRICT_FADD_VL,
STRICT_FSUB_VL,
@@ -489,13 +490,9 @@ enum NodeType : unsigned {
STRICT_FSETCC_VL,
STRICT_FSETCCS_VL,
STRICT_VFROUND_NOEXCEPT_VL,
- LAST_RISCV_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
+ LAST_STRICTFP_OPCODE = STRICT_VFROUND_NOEXCEPT_VL,
- // WARNING: Do not add anything in the end unless you want the node to
- // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
- // opcodes will be thought as target memory ops!
-
- TH_LWD = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ TH_LWD,
TH_LWUD,
TH_LDD,
TH_SWD,
diff --git a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
index 19d6138609a2ba..f1518ce880efc9 100644
--- a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp
@@ -7,7 +7,29 @@
//===----------------------------------------------------------------------===//
#include "RISCVSelectionDAGInfo.h"
+#include "RISCVISelLowering.h"
using namespace llvm;
RISCVSelectionDAGInfo::~RISCVSelectionDAGInfo() = default;
+
+bool RISCVSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ switch (static_cast<RISCVISD::NodeType>(Opcode)) {
+ default:
+ break;
+ case RISCVISD::TH_LWD:
+ case RISCVISD::TH_LWUD:
+ case RISCVISD::TH_LDD:
+ case RISCVISD::TH_SWD:
+ case RISCVISD::TH_SDD:
+ return true;
+ }
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
+bool RISCVSelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
+ if (Opcode >= RISCVISD::FIRST_STRICTFP_OPCODE &&
+ Opcode <= RISCVISD::LAST_STRICTFP_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetStrictFPOpcode(Opcode);
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
index 7543d8b493cebf..6977d8507a9605 100644
--- a/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h
@@ -16,6 +16,10 @@ namespace llvm {
class RISCVSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
~RISCVSelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
+ bool isTargetStrictFPOpcode(unsigned Opcode) const override;
};
} // namespace llvm
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 0a899e861c73bf..4f418eceef8bbe 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -307,7 +307,7 @@ enum NodeType : unsigned {
// Strict variants of scalar floating-point comparisons.
// Quiet and signaling versions.
- STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ STRICT_FCMP,
STRICT_FCMPS,
// Strict variants of vector floating-point comparisons.
@@ -333,7 +333,8 @@ enum NodeType : unsigned {
// operand into the high bits
// Operand 3: the negative of operand 2, for rotating the other way
// Operand 4: the width of the field in bits (8 or 16)
- ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ ATOMIC_SWAPW = FIRST_MEMORY_OPCODE,
ATOMIC_LOADW_ADD,
ATOMIC_LOADW_SUB,
ATOMIC_LOADW_AND,
@@ -384,7 +385,8 @@ enum NodeType : unsigned {
// Prefetch from the second operand using the 4-bit control code in
// the first operand. The code is 1 for a load prefetch and 2 for
// a store prefetch.
- PREFETCH
+ PREFETCH,
+ LAST_MEMORY_OPCODE = PREFETCH,
};
// Return true if OPCODE is some kind of PC-relative address.
diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
index c182c9890509fb..552bf1a24a74c6 100644
--- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
@@ -17,6 +17,32 @@ using namespace llvm;
#define DEBUG_TYPE "systemz-selectiondag-info"
+bool SystemZSelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= SystemZISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= SystemZISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
+bool SystemZSelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
+ switch (static_cast<SystemZISD::NodeType>(Opcode)) {
+ default:
+ break;
+ case SystemZISD::STRICT_FCMP:
+ case SystemZISD::STRICT_FCMPS:
+ case SystemZISD::STRICT_VFCMPE:
+ case SystemZISD::STRICT_VFCMPH:
+ case SystemZISD::STRICT_VFCMPHE:
+ case SystemZISD::STRICT_VFCMPES:
+ case SystemZISD::STRICT_VFCMPHS:
+ case SystemZISD::STRICT_VFCMPHES:
+ case SystemZISD::STRICT_VEXTEND:
+ case SystemZISD::STRICT_VROUND:
+ return true;
+ }
+ return SelectionDAGTargetInfo::isTargetStrictFPOpcode(Opcode);
+}
+
static unsigned getMemMemLenAdj(unsigned Op) {
return Op == SystemZISD::MEMSET_MVC ? 2 : 1;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
index 6ac5bf8c6c1a37..c928f343e57103 100644
--- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
@@ -21,6 +21,10 @@ class SystemZSelectionDAGInfo : public SelectionDAGTargetInfo {
public:
explicit SystemZSelectionDAGInfo() = default;
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
+ bool isTargetStrictFPOpcode(unsigned Opcode) const override;
+
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &DL,
SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
index 3502c47016c6b6..1cf0d13df1ff6b 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISD.def
@@ -48,10 +48,10 @@ HANDLE_NODETYPE(I64_MUL_WIDE_S)
HANDLE_NODETYPE(I64_MUL_WIDE_U)
// Memory intrinsics
-HANDLE_MEM_NODETYPE(GLOBAL_GET)
-HANDLE_MEM_NODETYPE(GLOBAL_SET)
-HANDLE_MEM_NODETYPE(TABLE_GET)
-HANDLE_MEM_NODETYPE(TABLE_SET)
+HANDLE_NODETYPE(GLOBAL_GET)
+HANDLE_NODETYPE(GLOBAL_SET)
+HANDLE_NODETYPE(TABLE_GET)
+HANDLE_NODETYPE(TABLE_SET)
// Bulk memory instructions. These follow LLVM's expected semantics of
// supporting out-of-bounds pointers if the length is zero, by inserting
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 7712570869ff6c..084aed6eed46d3 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -871,14 +871,11 @@ const char *
WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
case WebAssemblyISD::FIRST_NUMBER:
- case WebAssemblyISD::FIRST_MEM_OPCODE:
break;
#define HANDLE_NODETYPE(NODE) \
case WebAssemblyISD::NODE: \
return "WebAssemblyISD::" #NODE;
-#define HANDLE_MEM_NODETYPE(NODE) HANDLE_NODETYPE(NODE)
#include "WebAssemblyISD.def"
-#undef HANDLE_MEM_NODETYPE
#undef HANDLE_NODETYPE
}
return nullptr;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
index 82b33b6d1933d2..454432728ca871 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
@@ -24,16 +24,8 @@ namespace WebAssemblyISD {
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
#define HANDLE_NODETYPE(NODE) NODE,
-#define HANDLE_MEM_NODETYPE(NODE)
#include "WebAssemblyISD.def"
- FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE,
#undef HANDLE_NODETYPE
-#undef HANDLE_MEM_NODETYPE
-#define HANDLE_NODETYPE(NODE)
-#define HANDLE_MEM_NODETYPE(NODE) NODE,
-#include "WebAssemblyISD.def"
-#undef HANDLE_NODETYPE
-#undef HANDLE_MEM_NODETYPE
};
} // end namespace WebAssemblyISD
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
index 6f37dab4095349..b94cd46c9c141e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp
@@ -18,6 +18,19 @@ using namespace llvm;
WebAssemblySelectionDAGInfo::~WebAssemblySelectionDAGInfo() = default; // anchor
+bool WebAssemblySelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
+ default:
+ break;
+ case WebAssemblyISD::GLOBAL_GET:
+ case WebAssemblyISD::GLOBAL_SET:
+ case WebAssemblyISD::TABLE_GET:
+ case WebAssemblyISD::TABLE_SET:
+ return true;
+ }
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
SDValue WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(
SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
index fd517b238715b5..69c9af09663081 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h
@@ -22,6 +22,9 @@ namespace llvm {
class WebAssemblySelectionDAGInfo final : public SelectionDAGTargetInfo {
public:
~WebAssemblySelectionDAGInfo() override;
+
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Op1, SDValue Op2,
SDValue Op3, Align Alignment, bool isVolatile,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7d23176c493a23..4003241e8a525a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -54494,7 +54494,8 @@ static SDValue combineX86INT_TO_FP(SDNode *N, SelectionDAG &DAG,
static SDValue combineCVTP2I_CVTTP2I(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI) {
- bool IsStrict = N->isTargetStrictFPOpcode();
+ const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
+ bool IsStrict = TSI.isTargetStrictFPOpcode(N->getOpcode());
EVT VT = N->getValueType(0);
// Convert a full vector load into vzload when not all bits are needed.
@@ -55114,7 +55115,10 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
SDLoc dl(N);
EVT VT = N->getValueType(0);
- bool IsStrict = N->isStrictFPOpcode() || N->isTargetStrictFPOpcode();
+ const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo();
+ bool IsStrict = N->isTargetOpcode()
+ ? TSI.isTargetStrictFPOpcode(N->getOpcode())
+ : N->isStrictFPOpcode();
// Let legalize expand this if it isn't a legal type yet.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index d154ee9745b978..2b7a8eaf249d83 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -809,7 +809,8 @@ namespace llvm {
CTEST,
/// X86 strict FP compare instructions.
- STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
+ FIRST_STRICTFP_OPCODE,
+ STRICT_FCMP = FIRST_STRICTFP_OPCODE,
STRICT_FCMPS,
// Vector packed double/float comparison.
@@ -853,12 +854,11 @@ namespace llvm {
/// Floating point max and min.
STRICT_FMAX,
STRICT_FMIN,
-
- // WARNING: Only add nodes here if they are strict FP nodes. Non-memory and
- // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE.
+ LAST_STRICTFP_OPCODE = STRICT_FMIN,
// Compare and swap.
- LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
+ FIRST_MEMORY_OPCODE,
+ LCMPXCHG_DAG = FIRST_MEMORY_OPCODE,
LCMPXCHG8_DAG,
LCMPXCHG16_DAG,
LCMPXCHG16_SAVE_RBX_DAG,
@@ -979,10 +979,7 @@ namespace llvm {
// Conditional load/store instructions
CLOAD,
CSTORE,
-
- // WARNING: Do not add anything in the end unless you want the node to
- // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
- // opcodes will be thought as target memory ops!
+ LAST_MEMORY_OPCODE = CSTORE,
};
} // end namespace X86ISD
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
index 3f88bcf9ce5ec5..a21c4d714311e4 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -27,6 +27,20 @@ static cl::opt<bool>
UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false),
cl::desc("Use fast short rep mov in memcpy lowering"));
+bool X86SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
+ if (Opcode >= X86ISD::FIRST_MEMORY_OPCODE &&
+ Opcode <= X86ISD::LAST_MEMORY_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetMemoryOpcode(Opcode);
+}
+
+bool X86SelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
+ if (Opcode >= X86ISD::FIRST_STRICTFP_OPCODE &&
+ Opcode <= X86ISD::LAST_STRICTFP_OPCODE)
+ return true;
+ return SelectionDAGTargetInfo::isTargetStrictFPOpcode(Opcode);
+}
+
/// Returns the best type to use with repmovs/repstos depending on alignment.
static MVT getOptimalRepType(const X86Subtarget &Subtarget, Align Alignment) {
uint64_t Align = Alignment.value();
diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.h b/llvm/lib/Target/X86/X86SelectionDAGInfo.h
index 19136ca4f6f586..e77e16bab830d5 100644
--- a/llvm/lib/Target/X86/X86SelectionDAGInfo.h
+++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.h
@@ -26,6 +26,10 @@ class X86SelectionDAGInfo : public SelectionDAGTargetInfo {
public:
explicit X86SelectionDAGInfo() = default;
+ bool isTargetMemoryOpcode(unsigned Opcode) const override;
+
+ bool isTargetStrictFPOpcode(unsigned Opcode) const override;
+
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, Align Alignment,
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