[llvm] [NVPTX] Constant-folding for f2i, d2ui, f2ll etc. (PR #118965)

[Artem Belevich via llvm-commits]

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@@ -0,0 +1,173 @@
+//===--- NVVMIntrinsicUtils.h -----------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// This file contains the definitions of the enumerations and flags
+/// associated with NVVM Intrinsics, along with some helper functions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_IR_NVVMINTRINSICUTILS_H
+#define LLVM_IR_NVVMINTRINSICUTILS_H
+
+#include "llvm/ADT/APFloat.h"
+#include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/IntrinsicsNVPTX.h"
+
+namespace llvm {
+namespace nvvm {
+
+// Reduction Ops supported with TMA Copy from Shared
+// to Global Memory for the "cp.reduce.async.bulk.tensor.*"
+// family of PTX instructions.
+enum class TMAReductionOp : uint8_t {
+  ADD = 0,
+  MIN = 1,
+  MAX = 2,
+  INC = 3,
+  DEC = 4,
+  AND = 5,
+  OR = 6,
+  XOR = 7,
+};
+
+bool IntrinsicShouldFTZ(Intrinsic::ID IntrinsicID) {
+  switch (IntrinsicID) {
+  // Float to i32 / i64 conversion intrinsics:
----------------
Artem-B wrote:

Makes me wonder if we can add these FTZ, signedness, and rounding mode, properties as some sort of flag on the intrinsic in tablegen, where we define them, so we don't have to play a whack-a-mole updating these switches every time we add/change a NVPTX intrinsic.

If that's too cumbersome, we could construct a static table/map of intrinsic->flags, populate it once, and then just lookup individual intrinsic flag where we need it. That may be less cumbersome to update in the future.


https://github.com/llvm/llvm-project/pull/118965