[llvm] [LoongArch] Adds support for vectors in OptWInstrs (PR #118935)

[via llvm-commits]

https://github.com/heiher updated https://github.com/llvm/llvm-project/pull/118935

>From fe6638a65cf910c970e9674190c8a9b0afb6d58f Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Thu, 5 Dec 2024 20:59:04 +0800
Subject: [PATCH 1/2] [LoongArch] Adds support for vectors in OptWInstrs

---
 .../Target/LoongArch/LoongArchOptWInstrs.cpp  | 31 +++++++++++++++++--
 llvm/test/CodeGen/LoongArch/sextw-removal.ll  |  1 -
 2 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
index ab90409fdf47d0..73e8be0f9522af 100644
--- a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
@@ -126,7 +126,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
 
       switch (UserMI->getOpcode()) {
       default:
-        // TODO: Add vector
         return false;
 
       case LoongArch::ADD_W:
@@ -167,18 +166,45 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
       case LoongArch::MOVGR2FCSR:
       case LoongArch::MOVGR2FRH_W:
       case LoongArch::MOVGR2FR_W_64:
+      case LoongArch::VINSGR2VR_W:
+      case LoongArch::XVINSGR2VR_W:
+      case LoongArch::VREPLGR2VR_W:
+      case LoongArch::XVREPLGR2VR_W:
         if (Bits >= 32)
           break;
         return false;
       case LoongArch::MOVGR2CF:
+      case LoongArch::VREPLVE_D:
+      case LoongArch::XVREPLVE_D:
         if (Bits >= 1)
           break;
         return false;
+      case LoongArch::VREPLVE_W:
+      case LoongArch::XVREPLVE_W:
+        if (Bits >= 2)
+          break;
+        return false;
+      case LoongArch::VREPLVE_H:
+      case LoongArch::XVREPLVE_H:
+        if (Bits >= 3)
+          break;
+        return false;
+      case LoongArch::VREPLVE_B:
+      case LoongArch::XVREPLVE_B:
+        if (Bits >= 4)
+          break;
+        return false;
       case LoongArch::EXT_W_B:
+      case LoongArch::VINSGR2VR_B:
+      case LoongArch::VREPLGR2VR_B:
+      case LoongArch::XVREPLGR2VR_B:
         if (Bits >= 8)
           break;
         return false;
       case LoongArch::EXT_W_H:
+      case LoongArch::VINSGR2VR_H:
+      case LoongArch::VREPLGR2VR_H:
+      case LoongArch::XVREPLGR2VR_H:
         if (Bits >= 16)
           break;
         return false;
@@ -431,7 +457,8 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
   case LoongArch::MOVCF2GR:
   case LoongArch::MOVFRH2GR_S:
   case LoongArch::MOVFR2GR_S_64:
-    // TODO: Add vector
+  case LoongArch::VPICKVE2GR_W:
+  case LoongArch::XVPICKVE2GR_W:
     return true;
   // Special cases that require checking operands.
   // shifting right sufficiently makes the value 32-bit sign-extended
diff --git a/llvm/test/CodeGen/LoongArch/sextw-removal.ll b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
index 0aeafadb9325b8..c625f2db4d2e89 100644
--- a/llvm/test/CodeGen/LoongArch/sextw-removal.ll
+++ b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
@@ -1322,7 +1322,6 @@ define signext i32 @test20(<4 x i32> %v) {
 ; CHECK-LABEL: test20:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vpickve2gr.w $a0, $vr0, 3
-; CHECK-NEXT:    addi.w $a0, $a0, 0
 ; CHECK-NEXT:    ret
 ;
 ; NORMV-LABEL: test20:

>From 3ad015acc79d858508830873ead46b68801886ff Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Fri, 13 Dec 2024 23:16:40 +0800
Subject: [PATCH 2/2] Update test case

---
 llvm/test/CodeGen/LoongArch/sextw-removal.ll | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/LoongArch/sextw-removal.ll b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
index 5a6eb5209847a2..fff749fb13e950 100644
--- a/llvm/test/CodeGen/LoongArch/sextw-removal.ll
+++ b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
@@ -1357,7 +1357,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
 ; CHECK-NEXT:    .cfi_offset 27, -56
 ; CHECK-NEXT:    .cfi_offset 28, -64
 ; CHECK-NEXT:    .cfi_offset 29, -72
-; CHECK-NEXT:    ld.d $s6, $sp, 80
+; CHECK-NEXT:    ld.w $s6, $sp, 80
 ; CHECK-NEXT:    move $s2, $a7
 ; CHECK-NEXT:    move $s4, $a5
 ; CHECK-NEXT:    move $s0, $a4
@@ -1378,8 +1378,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
 ; CHECK-NEXT:  .LBB24_3: # %for.cond32.preheader.preheader
 ; CHECK-NEXT:    ld.d $a0, $sp, 96
 ; CHECK-NEXT:    ld.d $a1, $sp, 88
-; CHECK-NEXT:    addi.w $a2, $s6, 0
-; CHECK-NEXT:    sltui $a2, $a2, 1
+; CHECK-NEXT:    sltui $a2, $s6, 1
 ; CHECK-NEXT:    masknez $a0, $a0, $a2
 ; CHECK-NEXT:    vreplgr2vr.w $vr0, $s6
 ; CHECK-NEXT:    andi $a1, $a1, 1
@@ -1451,7 +1450,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
 ; NORMV-NEXT:    beqz $s4, .LBB24_2
 ; NORMV-NEXT:  # %bb.1: # %if.then26
 ; NORMV-NEXT:    addi.d $a0, $s6, 1
-; NORMV-NEXT:    addi.w $s6, $a0, 0
+; NORMV-NEXT:    addi.d $s6, $a0, 0
 ; NORMV-NEXT:    beqz $s4, .LBB24_3
 ; NORMV-NEXT:    b .LBB24_6
 ; NORMV-NEXT:  .LBB24_2: