[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

Perhaps a left field suggestion but looking at the use cases you want to handle I'm wondering if my initial suggestion was too limiting and instead we'd be better of with something more powerful like `PARTIAL_REDUCE_SMLA/PARTIAL_REDUCE_UMLA`.  That way you'll have an easier time representing the expected use cases of the intrinsic whilst still being able to represent the most general form by using a unit vector for one of the multiplicands.

This will re-raise an earlier question of yours as to whether we need `PARTIAL_REDUCE_USMLA`. To that I would personally hold off and maintain the current DAG combine because it feels somewhat target specific, but at the same time I wouldn't object to it if the consensus is in favour of it.

https://github.com/llvm/llvm-project/pull/117185