[llvm] [RISCV] Split OPERAND_SEW operand type for mask only instructions. (PR #119776)

[Craig Topper via llvm-commits]

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@@ -430,7 +430,9 @@ void RISCVInstrInfo::copyPhysRegVector(
     if (UseVMV) {
       const MCInstrDesc &Desc = DefMBBI->getDesc();
       MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc)));  // AVL
-      MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW
+      unsigned Log2SEW =
+          DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc)).getImm();
+      MIB.addImm(Log2SEW ? Log2SEW : 3);                        // SEW
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topperc wrote:

> Actually never mind it's an immediate. We could maybe set SEW to something illegal to prevent anything from depending on it

That would complicate the verifier.

https://github.com/llvm/llvm-project/pull/119776