[llvm] [M68k] implement -mxgot (PR #119803)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 12 19:00:19 PST 2024
https://github.com/knickish created https://github.com/llvm/llvm-project/pull/119803
None
>From 09fb9ae469d16c9dead563a5b49d6237d36eb793 Mon Sep 17 00:00:00 2001
From: kirk <knickish at gmail.com>
Date: Wed, 11 Dec 2024 19:42:43 +0000
Subject: [PATCH] [M68k] implement -mxgot
---
llvm/lib/Target/M68k/M68k.td | 3 +
llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp | 14 ++--
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 23 ++++++-
llvm/lib/Target/M68k/M68kSubtarget.cpp | 4 +-
llvm/lib/Target/M68k/M68kSubtarget.h | 5 ++
llvm/lib/Target/M68k/M68kTargetMachine.cpp | 1 +
llvm/lib/Target/M68k/M68kTargetMachine.h | 1 +
.../M68k/MCTargetDesc/M68kAsmBackend.cpp | 65 ++++++++++++++++---
.../M68k/MCTargetDesc/M68kMCCodeEmitter.cpp | 5 +-
llvm/test/CodeGen/M68k/xgot.ll | 51 +++++++++++++++
.../MC/M68k/Relocations/PIC/data-gotoff.s | 37 ++++++++++-
11 files changed, 188 insertions(+), 21 deletions(-)
create mode 100644 llvm/test/CodeGen/M68k/xgot.ll
diff --git a/llvm/lib/Target/M68k/M68k.td b/llvm/lib/Target/M68k/M68k.td
index dab66d10229559..7fd48d6a7c46d4 100644
--- a/llvm/lib/Target/M68k/M68k.td
+++ b/llvm/lib/Target/M68k/M68k.td
@@ -65,6 +65,9 @@ foreach i = {0-7} in
SubtargetFeature<"reserve-d"#i, "UserReservedRegister[M68k::D"#i#"]",
"true", "Reserve D"#i#" register">;
+def FeatureXGOT
+ : SubtargetFeature<"xgot", "UseXGOT", "true", "Assume 32-bit GOT">;
+
//===----------------------------------------------------------------------===//
// M68k processors supported.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
index 53c144c8fa79a1..d6636e38837c0f 100644
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -680,11 +680,15 @@ void M68kDAGToDAGISel::Select(SDNode *Node) {
break;
case ISD::GLOBAL_OFFSET_TABLE: {
- SDValue GOT = CurDAG->getTargetExternalSymbol(
- "_GLOBAL_OFFSET_TABLE_", MVT::i32, M68kII::MO_GOTPCREL);
- MachineSDNode *Res =
- CurDAG->getMachineNode(M68k::LEA32q, DL, MVT::i32, GOT);
- ReplaceNode(Node, Res);
+ if (Subtarget->useXGOT()) {
+
+ } else {
+ SDValue GOT = CurDAG->getTargetExternalSymbol(
+ "_GLOBAL_OFFSET_TABLE_", MVT::i32, M68kII::MO_GOTPCREL);
+ MachineSDNode *Res =
+ CurDAG->getMachineNode(M68k::LEA32q, DL, MVT::i32, GOT);
+ ReplaceNode(Node, Res);
+ }
return;
}
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 63404645209508..da5ce0bd606a9c 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -17,6 +17,7 @@
#include "M68kMachineFunction.h"
#include "M68kTargetMachine.h"
#include "MCTargetDesc/M68kMCCodeEmitter.h"
+#include "MCTargetDesc/M68kMCTargetDesc.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/ScopeExit.h"
@@ -936,6 +937,7 @@ struct M68kGlobalBaseReg : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override {
const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
M68kMachineFunctionInfo *MxFI = MF.getInfo<M68kMachineFunctionInfo>();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();
@@ -949,9 +951,24 @@ struct M68kGlobalBaseReg : public MachineFunctionPass {
DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
const M68kInstrInfo *TII = STI.getInstrInfo();
- // Generate lea (__GLOBAL_OFFSET_TABLE_,%PC), %A5
- BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)
- .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", M68kII::MO_GOTPCREL);
+ if (STI.useXGOT()) {
+ Register LoadPC = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);
+ Register LoadGOT =
+ RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);
+ BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), LoadPC).addImm(0);
+ BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32b), LoadGOT)
+ .addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
+ ;
+ BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::SUB32ar), GlobalBaseReg)
+ .addReg(LoadPC)
+ .addReg(LoadGOT);
+
+ // continue here
+ } else {
+ // Generate lea (__GLOBAL_OFFSET_TABLE_,%PC), %A5
+ BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)
+ .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", M68kII::MO_GOTPCREL);
+ }
return true;
}
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.cpp b/llvm/lib/Target/M68k/M68kSubtarget.cpp
index 53ec574ae5596c..44927d37bd2c00 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.cpp
+++ b/llvm/lib/Target/M68k/M68kSubtarget.cpp
@@ -25,6 +25,7 @@
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
@@ -50,7 +51,8 @@ void M68kSubtarget::anchor() {}
M68kSubtarget::M68kSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const M68kTargetMachine &TM)
- : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TM(TM), TSInfo(),
+ : M68kGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
+ UseXGOT(this->useXGOT()), TM(TM), TSInfo(),
InstrInfo(initializeSubtargetDependencies(CPU, TT, FS, TM)),
FrameLowering(*this, this->getStackAlignment()), TLInfo(TM, *this),
TargetTriple(TT) {
diff --git a/llvm/lib/Target/M68k/M68kSubtarget.h b/llvm/lib/Target/M68k/M68kSubtarget.h
index c08a9786fb27ba..19128856d30649 100644
--- a/llvm/lib/Target/M68k/M68kSubtarget.h
+++ b/llvm/lib/Target/M68k/M68kSubtarget.h
@@ -51,6 +51,9 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
enum SubtargetEnum { M00, M10, M20, M30, M40, M60 };
SubtargetEnum SubtargetKind = M00;
+ // Assume 32-bit GOT.
+ bool UseXGOT = false;
+
enum FPKindEnum { M881, M882 };
std::optional<FPKindEnum> FPUKind;
@@ -98,6 +101,8 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
bool useSmallSection() const { return UseSmallSection; }
+ bool useXGOT() const { return UseXGOT; }
+
const Triple &getTargetTriple() const { return TargetTriple; }
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
index 2f5a2e8288a261..839db3a6da5fe5 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp
@@ -105,6 +105,7 @@ M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT,
::getEffectiveCodeModel(CM, JIT), OL),
TLOF(std::make_unique<M68kELFTargetObjectFile>()),
Subtarget(TT, CPU, FS, *this) {
+ setCodeModel(::getEffectiveCodeModel(CM, JIT));
initAsmInfo();
}
diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.h b/llvm/lib/Target/M68k/M68kTargetMachine.h
index c2648f5d38c5ea..25a721aba3c8ec 100644
--- a/llvm/lib/Target/M68k/M68kTargetMachine.h
+++ b/llvm/lib/Target/M68k/M68kTargetMachine.h
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/Support/CodeGen.h"
#include <optional>
diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
index 04777677cbf218..432915e972538a 100644
--- a/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
+++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
@@ -93,8 +93,11 @@ class M68kAsmBackend : public MCAsmBackend {
bool mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const override;
- bool fixupNeedsRelaxation(const MCFixup &Fixup,
- uint64_t Value) const override;
+ bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,
+ const MCFixup &Fixup, bool Resolved,
+ uint64_t Value,
+ const MCRelaxableFragment *DF,
+ const bool WasForced) const override;
void relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const override;
@@ -191,6 +194,31 @@ static unsigned getRelaxedOpcodeBranch(const MCInst &Inst) {
}
}
+static bool RelaxesTo32Bit(const MCInst &Inst) {
+ unsigned Op = Inst.getOpcode();
+ switch (Op) {
+ default:
+ return false;
+
+ case M68k::BRA16:
+ case M68k::Bcc16:
+ case M68k::Bls16:
+ case M68k::Blt16:
+ case M68k::Beq16:
+ case M68k::Bmi16:
+ case M68k::Bne16:
+ case M68k::Bge16:
+ case M68k::Bcs16:
+ case M68k::Bpl16:
+ case M68k::Bgt16:
+ case M68k::Bhi16:
+ case M68k::Bvc16:
+ case M68k::Ble16:
+ case M68k::Bvs16:
+ return true;
+ }
+}
+
static unsigned getRelaxedOpcodeArith(const MCInst &Inst) {
unsigned Op = Inst.getOpcode();
// NOTE there will be some relaxations for PCD and ARD mem for x20
@@ -224,22 +252,42 @@ bool M68kAsmBackend::mayNeedRelaxation(const MCInst &Inst,
return false;
}
-bool M68kAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
- uint64_t UnsignedValue) const {
+bool M68kAsmBackend::fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,
+ const MCFixup &Fixup,
+ bool Resolved,
+ uint64_t UnsignedValue,
+ const MCRelaxableFragment *DF,
+ const bool WasForced) const {
int64_t Value = static_cast<int64_t>(UnsignedValue);
- if (!isInt<32>(Value) || (!Allows32BitBranch && !isInt<16>(Value)))
+ if (!isInt<32>(Value) || (!Allows32BitBranch && !isInt<16>(Value))) {
llvm_unreachable("Cannot relax the instruction, value does not fit");
+ }
+
+ bool InstrCanRelax = false;
+ if (Allows32BitBranch) {
+ // mayNeedRelaxation checks that there's actually an instr to relax to
+ // before reaching this point, and all instrs are available for this CPU
+ InstrCanRelax = true;
+ } else {
+ // We're using a CPU that can only handle 16 bit branches, we can't relax
+ // unless it's an 8->16 bit relaxation
+ InstrCanRelax = !RelaxesTo32Bit(DF->getInst());
+ }
+ // For unresolved fixups, make sure we relax them as much as is possible
+ // for the CPU type.
+ bool RelaxBecauseUnresolved = !Resolved && InstrCanRelax;
// Relax if the value is too big for a (signed) i8
// (or signed i16 if 32 bit branches can be used). This means
// that byte-wide instructions have to matched by default
unsigned KindLog2Size = getFixupKindLog2Size(Fixup.getKind());
bool FixupFieldTooSmall = false;
- if (!isInt<8>(Value) && KindLog2Size == 0)
+ if (!isInt<8>(Value) && KindLog2Size == 0) {
FixupFieldTooSmall = true;
- else if (!isInt<16>(Value) && KindLog2Size <= 1)
+ } else if (!isInt<16>(Value) && KindLog2Size <= 1) {
FixupFieldTooSmall = true;
+ }
// NOTE
// A branch to the immediately following instruction automatically
@@ -247,7 +295,8 @@ bool M68kAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
// displacement field contains $00 (zero offset).
bool ZeroDisplacementNeedsFixup = Value == 0 && KindLog2Size == 0;
- return ZeroDisplacementNeedsFixup || FixupFieldTooSmall;
+ return ZeroDisplacementNeedsFixup || FixupFieldTooSmall ||
+ RelaxBecauseUnresolved;
}
// NOTE Can tblgen help at all here to verify there aren't other instructions
diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
index 78783084ee59a0..236e2104b4c346 100644
--- a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
+++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp
@@ -214,9 +214,12 @@ void M68kMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &Op,
} else if (Op.isExpr()) {
// Absolute address
int64_t Addr;
- if (!Op.getExpr()->evaluateAsAbsolute(Addr))
+ if (!Op.getExpr()->evaluateAsAbsolute(Addr)) {
+ LLVM_DEBUG(MI.dump_pretty(dbgs()));
+ LLVM_DEBUG(dbgs() << '\n');
report_fatal_error("Unsupported asm expression. Only absolute address "
"can be placed here.");
+ }
Value |= static_cast<uint64_t>(Addr);
} else {
llvm_unreachable("Unsupported operand type");
diff --git a/llvm/test/CodeGen/M68k/xgot.ll b/llvm/test/CodeGen/M68k/xgot.ll
new file mode 100644
index 00000000000000..ad7ebc2fb38d1b
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/xgot.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=m68k --show-mc-encoding -mattr=+xgot -relocation-model=pic -code-model=large < %s | FileCheck %s
+
+ at VBRTag = external global [2147483647 x i8]
+
+define i1 @folded_offset(i32 %conv29) {
+; CHECK-LABEL: folded_offset:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %entry
+; CHECK-NEXT: lea (0,%pc), %a0 ; encoding: [0x41,0xfa,0x00,0x00]
+; CHECK-NEXT: lea _GLOBAL_OFFSET_TABLE_, %a1 ; encoding: [0x43,0xf9,A,A,A,A]
+; CHECK-NEXT: ; fixup A - offset: 2, value: _GLOBAL_OFFSET_TABLE_, kind: FK_Data_4
+; CHECK-NEXT: suba.l %a1, %a0 ; encoding: [0x91,0xc9]
+; CHECK-NEXT: move.l #VBRTag at GOTOFF, %d0 ; encoding: [0x20,0x3c,A,A,A,A]
+; CHECK-NEXT: ; fixup A - offset: 2, value: VBRTag at GOTOFF, kind: FK_Data_4
+; CHECK-NEXT: move.b (1,%a0,%d0), %d0 ; encoding: [0x10,0x30,0x08,0x01]
+; CHECK-NEXT: ext.w %d0 ; encoding: [0x48,0x80]
+; CHECK-NEXT: ext.l %d0 ; encoding: [0x48,0xc0]
+; CHECK-NEXT: sub.l (4,%sp), %d0 ; encoding: [0x90,0xaf,0x00,0x04]
+; CHECK-NEXT: seq %d0 ; encoding: [0x57,0xc0]
+; CHECK-NEXT: rts ; encoding: [0x4e,0x75]
+entry:
+ %0 = load i8, ptr getelementptr inbounds ([2147483647 x i8], ptr @VBRTag, i32 0, i32 1), align 1
+ %conv30 = sext i8 %0 to i32
+ %cmp31.not = icmp eq i32 %conv30, %conv29
+ ret i1 %cmp31.not
+}
+
+define i1 @non_folded_offset(i32 %conv29) {
+; CHECK-LABEL: non_folded_offset:
+; CHECK: .cfi_startproc
+; CHECK-NEXT: ; %bb.0: ; %entry
+; CHECK-NEXT: lea (0,%pc), %a0 ; encoding: [0x41,0xfa,0x00,0x00]
+; CHECK-NEXT: lea _GLOBAL_OFFSET_TABLE_, %a1 ; encoding: [0x43,0xf9,A,A,A,A]
+; CHECK-NEXT: ; fixup A - offset: 2, value: _GLOBAL_OFFSET_TABLE_, kind: FK_Data_4
+; CHECK-NEXT: suba.l %a1, %a0 ; encoding: [0x91,0xc9]
+; CHECK-NEXT: move.l #2147483645, %d0 ; encoding: [0x20,0x3c,0x7f,0xff,0xff,0xfd]
+; CHECK-NEXT: adda.l #VBRTag at GOTOFF, %a0 ; encoding: [0xd1,0xfc,A,A,A,A]
+; CHECK-NEXT: ; fixup A - offset: 2, value: VBRTag at GOTOFF, kind: FK_Data_4
+; CHECK-NEXT: move.b (0,%a0,%d0), %d0 ; encoding: [0x10,0x30,0x08,0x00]
+; CHECK-NEXT: ext.w %d0 ; encoding: [0x48,0x80]
+; CHECK-NEXT: ext.l %d0 ; encoding: [0x48,0xc0]
+; CHECK-NEXT: sub.l (4,%sp), %d0 ; encoding: [0x90,0xaf,0x00,0x04]
+; CHECK-NEXT: seq %d0 ; encoding: [0x57,0xc0]
+; CHECK-NEXT: rts ; encoding: [0x4e,0x75]
+entry:
+ %0 = load i8, ptr getelementptr inbounds ([2147483647 x i8], ptr @VBRTag, i32 0, i32 2147483645), align 1
+ %conv30 = sext i8 %0 to i32
+ %cmp31.not = icmp eq i32 %conv30, %conv29
+ ret i1 %cmp31.not
+}
diff --git a/llvm/test/MC/M68k/Relocations/PIC/data-gotoff.s b/llvm/test/MC/M68k/Relocations/PIC/data-gotoff.s
index ca1ce52de1ca75..0de930b6fd6582 100644
--- a/llvm/test/MC/M68k/Relocations/PIC/data-gotoff.s
+++ b/llvm/test/MC/M68k/Relocations/PIC/data-gotoff.s
@@ -2,18 +2,49 @@
; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s
; RUN: llvm-mc -triple m68k -show-encoding --position-independent %s -o - \
; RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
+; RUN: llvm-mc -triple m68k -filetype=obj -mattr=+xgot --position-independent %s -o - \
+; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC-XGOT %s
+; RUN: llvm-mc -triple m68k -show-encoding -mattr=+xgot --position-independent %s -o - \
+; RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP-XGOT %s
+
+; RUN: llvm-mc -triple m68k --mcpu=M68020 -filetype=obj --position-independent %s -o - \
+; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC32 %s
+; RUN: llvm-mc -triple m68k --mcpu=M68020 -show-encoding --position-independent %s -o - \
+; RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP32 %s
+; RUN: llvm-mc -triple m68k --mcpu=M68020 -filetype=obj -mattr=+xgot --position-independent %s -o - \
+; RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC-XGOT32 %s
+; RUN: llvm-mc -triple m68k --mcpu=M68020 -show-encoding -mattr=+xgot --position-independent %s -o - \
+; RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP-XGOT32 %s
-; RELOC: R_68K_GOTOFF8 dst1 0x0
; INSTR: move.l (dst1 at GOTOFF,%a5,%d0), %d0
+; RELOC: R_68K_GOTOFF8 dst1 0x0
+; RELOC32: R_68K_GOTOFF8 dst1 0x0
+; RELOC-XGOT: R_68K_GOTOFF8 dst1 0x0
+; RELOC-XGO32T: R_68K_GOTOFF8 dst1 0x0
; FIXUP: fixup A - offset: 3, value: dst1 at GOTOFF, kind: FK_Data_1
+; FIXUP32: fixup A - offset: 3, value: dst1 at GOTOFF, kind: FK_Data_1
+; FIXUP-XGOT: fixup A - offset: 3, value: dst1 at GOTOFF, kind: FK_Data_1
+; FIXUP-XGOT32: fixup A - offset: 3, value: dst1 at GOTOFF, kind: FK_Data_1
move.l (dst1 at GOTOFF,%a5,%d0), %d0
-; RELOC: R_68K_GOTOFF16 dst2 0x0
; INSTR: move.l (dst2 at GOTOFF,%a5), %d0
+; RELOC: R_68K_GOTOFF16 dst2 0x0
+; RELOC32: R_68K_GOTOFF16 dst2 0x0
+; RELOC-XGOT: R_68K_GOTOFF16 dst2 0x0
+; RELOC-XGOT32: R_68K_GOTOFF16 dst2 0x0
; FIXUP: fixup A - offset: 2, value: dst2 at GOTOFF, kind: FK_Data_2
+; FIXUP32: fixup A - offset: 2, value: dst2 at GOTOFF, kind: FK_Data_2
+; FIXUP-XGOT: fixup A - offset: 2, value: dst2 at GOTOFF, kind: FK_Data_2
+; FIXUP-XGOT32: fixup A - offset: 2, value: dst2 at GOTOFF, kind: FK_Data_2
move.l (dst2 at GOTOFF,%a5), %d0
-; RELOC: R_68K_GOTPCREL16 dst3 0x0
; INSTR: lea (dst3 at GOTPCREL,%pc), %a5
+; RELOC: R_68K_GOTPCREL16 dst3 0x0
+; RELOC32: R_68K_GOTPCREL16 dst3 0x0
+; RELOC-XGOT: R_68K_GOTPCREL16 dst3 0x0
+; RELOC-XGOT32: R_68K_GOTPCREL16 dst3 0x0
; FIXUP: fixup A - offset: 2, value: dst3 at GOTPCREL, kind: FK_PCRel_2
+; FIXUP32: fixup A - offset: 2, value: dst3 at GOTPCREL, kind: FK_PCRel_2
+; FIXUP-XGOT: fixup A - offset: 2, value: dst3 at GOTPCREL, kind: FK_PCRel_2
+; FIXUP-XGOT32: fixup A - offset: 2, value: dst3 at GOTPCREL, kind: FK_PCRel_2
lea (dst3 at GOTPCREL,%pc), %a5
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