[llvm] [RISCV][VLOPT] Add vector mask producing integer instructions to isSupportedInstr and getOperandInfo (PR #119733)

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 12 11:38:03 PST 2024


================
@@ -602,4 +602,83 @@ body: |
     %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
     %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
 ...
-
+---
+name: vmop_vv
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: vmop_vv
+    ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1, 0 /* e8 */
+    ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 0 /* e8 */
+    %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 0
----------------
michaelmaitland wrote:

Thanks. Updated. Is that something we could enforce in the MachineVerifier?

https://github.com/llvm/llvm-project/pull/119733


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