[llvm] 67eb05b - [PowerPC] Add special handling for arguments that are smaller than pointer size. (#119003)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 12 06:43:59 PST 2024
Author: Stefan Pintilie
Date: 2024-12-12T09:43:53-05:00
New Revision: 67eb05b2928ea707761bb040e6eb824f4ca9ef3a
URL: https://github.com/llvm/llvm-project/commit/67eb05b2928ea707761bb040e6eb824f4ca9ef3a
DIFF: https://github.com/llvm/llvm-project/commit/67eb05b2928ea707761bb040e6eb824f4ca9ef3a.diff
LOG: [PowerPC] Add special handling for arguments that are smaller than pointer size. (#119003)
When arguments are passed in memory instead of registers we currently
load the entire pointer size even though the argument may be smaller.
For exmaple if the pointer size if i32 then we use a load word even if
the argument is only an i8. This patch zeros / extends the bits that are
not required to ensure that we are getting the correct value even if the
load is larger.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 2af983fc7b04e8..69bc2cce6c2c7d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -7244,6 +7244,9 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
MVT LocVT = VA.getLocVT();
MVT ValVT = VA.getValVT();
ISD::ArgFlagsTy Flags = Ins[VA.getValNo()].Flags;
+
+ EVT ArgVT = Ins[VA.getValNo()].ArgVT;
+ bool ArgSignExt = Ins[VA.getValNo()].Flags.isSExt();
// For compatibility with the AIX XL compiler, the float args in the
// parameter save area are initialized even if the argument is available
// in register. The caller is required to initialize both the register
@@ -7291,7 +7294,24 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue ArgValue =
DAG.getLoad(ValVT, dl, Chain, FIN, MachinePointerInfo());
- InVals.push_back(ArgValue);
+
+ // While the ABI specifies the argument type is (sign or zero) extended
+ // out to register width, not all code is compliant. We truncate and
+ // re-extend to be more forgiving of these callers when the argument type
+ // is smaller than register width.
+ if (!ArgVT.isVector() && !ValVT.isVector() && ArgVT.isInteger() &&
+ ValVT.isInteger() &&
+ ArgVT.getScalarSizeInBits() < ValVT.getScalarSizeInBits()) {
+ SDValue ArgValueTrunc = DAG.getNode(
+ ISD::TRUNCATE, dl, ArgVT.getSimpleVT() == MVT::i1 ? MVT::i8 : ArgVT,
+ ArgValue);
+ SDValue ArgValueExt =
+ ArgSignExt ? DAG.getSExtOrTrunc(ArgValueTrunc, dl, ValVT)
+ : DAG.getZExtOrTrunc(ArgValueTrunc, dl, ValVT);
+ InVals.push_back(ArgValueExt);
+ } else {
+ InVals.push_back(ArgValue);
+ }
};
// Vector arguments to VaArg functions are passed both on the stack, and
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index 00d1c471c2fa7c..501227c9072c45 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -1102,12 +1102,12 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 32BIT-NEXT: {{ $}}
; 32BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0)
; 32BIT-NEXT: renamable $r12 = LWZ 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4)
- ; 32BIT-NEXT: renamable $r0 = LWZ 0, %fixed-stack.1 :: (load (s32) from %fixed-stack.1, align 8)
+ ; 32BIT-NEXT: renamable $r0 = LBZ 3, %fixed-stack.1 :: (load (s8) from %fixed-stack.1 + 3, basealign 4)
; 32BIT-NEXT: renamable $r31 = LWZ 4, %fixed-stack.3 :: (load (s32) from %fixed-stack.3 + 4, basealign 16)
; 32BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3, align 16)
; 32BIT-NEXT: renamable $r29 = LWZ 0, %fixed-stack.5 :: (load (s32) from %fixed-stack.5, align 8)
- ; 32BIT-NEXT: renamable $r28 = LWZ 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6)
- ; 32BIT-NEXT: renamable $r27 = LWZ 0, %fixed-stack.7 :: (load (s32) from %fixed-stack.7, align 16)
+ ; 32BIT-NEXT: renamable $r28 = LBZ 3, %fixed-stack.6 :: (load (s8) from %fixed-stack.6 + 3, basealign 4)
+ ; 32BIT-NEXT: renamable $r27 = LHA 2, %fixed-stack.7 :: (load (s16) from %fixed-stack.7 + 2, basealign 4)
; 32BIT-NEXT: renamable $r26 = LWZ 4, %fixed-stack.9 :: (load (s32) from %fixed-stack.9 + 4, basealign 8)
; 32BIT-NEXT: renamable $r25 = LWZ 0, %fixed-stack.9 :: (load (s32) from %fixed-stack.9, align 8)
; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4
@@ -1143,13 +1143,13 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 64BIT: bb.0.entry:
; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
; 64BIT-NEXT: {{ $}}
- ; 64BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.1, implicit-def $x11 :: (load (s32) from %fixed-stack.1)
+ ; 64BIT-NEXT: renamable $r11 = LBZ 3, %fixed-stack.1, implicit-def $x11 :: (load (s8) from %fixed-stack.1 + 3, basealign 4)
; 64BIT-NEXT: renamable $x12 = LWZ8 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4)
- ; 64BIT-NEXT: renamable $x0 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0)
- ; 64BIT-NEXT: renamable $x2 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
- ; 64BIT-NEXT: renamable $x31 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
- ; 64BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.5, implicit-def $x30 :: (load (s32) from %fixed-stack.5)
- ; 64BIT-NEXT: renamable $x29 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6)
+ ; 64BIT-NEXT: renamable $r0 = LBZ 3, %fixed-stack.5, implicit-def $x0 :: (load (s8) from %fixed-stack.5 + 3, basealign 4)
+ ; 64BIT-NEXT: renamable $x2 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0)
+ ; 64BIT-NEXT: renamable $x31 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
+ ; 64BIT-NEXT: renamable $x30 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
+ ; 64BIT-NEXT: renamable $x29 = LHA8 2, %fixed-stack.6
; 64BIT-NEXT: renamable $x28 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16)
; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
@@ -1161,12 +1161,12 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x28
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x29
- ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30
+ ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12
+ ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x31
- ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x2
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x11
- ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0
+ ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x2
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
entry:
%add = add nsw i32 %i1, %i2
@@ -1611,8 +1611,8 @@ define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroex
; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4
; 32BIT-NEXT: {{ $}}
; 32BIT-NEXT: renamable $r3 = LWZ 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
- ; 32BIT-NEXT: renamable $r4 = LWZ 0, %fixed-stack.5 :: (load (s32) from %fixed-stack.5)
- ; 32BIT-NEXT: renamable $r5 = LWZ 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6, align 8)
+ ; 32BIT-NEXT: renamable $r4 = LHA 2, %fixed-stack.5 :: (load (s16) from %fixed-stack.5 + 2, basealign 4)
+ ; 32BIT-NEXT: renamable $r5 = LBZ 3, %fixed-stack.6 :: (load (s8) from %fixed-stack.6 + 3, basealign 4)
; 32BIT-NEXT: renamable $r6 = LWZ 0, %fixed-stack.2 :: (load (s32) from %fixed-stack.2, align 8)
; 32BIT-NEXT: renamable $r7 = LIS 17200
; 32BIT-NEXT: STW killed renamable $r7, 0, %stack.1 :: (store (s32) into %stack.1, align 8)
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
index 433d4273444660..79c59e925302af 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1181,78 +1181,95 @@ entry:
declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...)
-define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) {
+define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16, i8 signext %si8, i1 zeroext %zi1) {
; ASM32PWR4-LABEL: test_ints_stack:
; ASM32PWR4: # %bb.0: # %entry
; ASM32PWR4-NEXT: add 3, 3, 4
-; ASM32PWR4-NEXT: lwz 11, 92(1)
+; ASM32PWR4-NEXT: stw 31, -4(1) # 4-byte Folded Spill
; ASM32PWR4-NEXT: add 3, 3, 5
; ASM32PWR4-NEXT: add 3, 3, 6
; ASM32PWR4-NEXT: add 3, 3, 7
-; ASM32PWR4-NEXT: lwz 12, 76(1)
+; ASM32PWR4-NEXT: lbz 12, 99(1)
; ASM32PWR4-NEXT: add 3, 3, 8
; ASM32PWR4-NEXT: add 3, 3, 9
-; ASM32PWR4-NEXT: lwz 6, 60(1)
+; ASM32PWR4-NEXT: lwz 0, 92(1)
; ASM32PWR4-NEXT: add 3, 3, 10
-; ASM32PWR4-NEXT: srawi 5, 11, 31
+; ASM32PWR4-NEXT: extsb 4, 12
; ASM32PWR4-NEXT: srawi 8, 3, 31
-; ASM32PWR4-NEXT: lwz 4, 64(1)
+; ASM32PWR4-NEXT: lwz 31, 76(1)
+; ASM32PWR4-NEXT: srawi 12, 0, 31
+; ASM32PWR4-NEXT: lwz 6, 60(1)
+; ASM32PWR4-NEXT: lha 11, 66(1)
; ASM32PWR4-NEXT: lwz 7, 56(1)
-; ASM32PWR4-NEXT: stw 31, -4(1) # 4-byte Folded Spill
-; ASM32PWR4-NEXT: srawi 31, 12, 31
+; ASM32PWR4-NEXT: stw 30, -8(1) # 4-byte Folded Spill
+; ASM32PWR4-NEXT: srawi 30, 31, 31
; ASM32PWR4-NEXT: addc 3, 3, 6
; ASM32PWR4-NEXT: adde 7, 8, 7
-; ASM32PWR4-NEXT: lwz 6, 68(1)
-; ASM32PWR4-NEXT: srawi 8, 4, 31
-; ASM32PWR4-NEXT: addc 3, 3, 4
+; ASM32PWR4-NEXT: lbz 6, 71(1)
+; ASM32PWR4-NEXT: srawi 8, 11, 31
+; ASM32PWR4-NEXT: addc 3, 3, 11
; ASM32PWR4-NEXT: adde 7, 7, 8
-; ASM32PWR4-NEXT: lwz 4, 72(1)
+; ASM32PWR4-NEXT: lwz 9, 72(1)
; ASM32PWR4-NEXT: addc 3, 3, 6
; ASM32PWR4-NEXT: addze 6, 7
-; ASM32PWR4-NEXT: addc 3, 3, 4
-; ASM32PWR4-NEXT: lwz 0, 84(1)
-; ASM32PWR4-NEXT: addze 4, 6
-; ASM32PWR4-NEXT: addc 3, 3, 12
+; ASM32PWR4-NEXT: addc 3, 3, 9
+; ASM32PWR4-NEXT: lwz 5, 84(1)
+; ASM32PWR4-NEXT: addze 6, 6
+; ASM32PWR4-NEXT: addc 3, 3, 31
; ASM32PWR4-NEXT: lwz 7, 80(1)
-; ASM32PWR4-NEXT: adde 4, 4, 31
+; ASM32PWR4-NEXT: adde 6, 6, 30
+; ASM32PWR4-NEXT: addc 3, 3, 5
+; ASM32PWR4-NEXT: lbz 8, 91(1)
+; ASM32PWR4-NEXT: adde 5, 6, 7
+; ASM32PWR4-NEXT: addc 3, 3, 8
+; ASM32PWR4-NEXT: lbz 6, 103(1)
+; ASM32PWR4-NEXT: addze 5, 5
; ASM32PWR4-NEXT: addc 3, 3, 0
-; ASM32PWR4-NEXT: lwz 6, 88(1)
-; ASM32PWR4-NEXT: adde 4, 4, 7
-; ASM32PWR4-NEXT: addc 3, 3, 6
+; ASM32PWR4-NEXT: adde 5, 5, 12
; ASM32PWR4-NEXT: lwz 31, -4(1) # 4-byte Folded Reload
-; ASM32PWR4-NEXT: addze 6, 4
-; ASM32PWR4-NEXT: addc 4, 3, 11
-; ASM32PWR4-NEXT: adde 3, 6, 5
+; ASM32PWR4-NEXT: srawi 7, 4, 31
+; ASM32PWR4-NEXT: addc 3, 3, 4
+; ASM32PWR4-NEXT: adde 5, 5, 7
+; ASM32PWR4-NEXT: lwz 30, -8(1) # 4-byte Folded Reload
+; ASM32PWR4-NEXT: addc 4, 3, 6
+; ASM32PWR4-NEXT: addze 3, 5
; ASM32PWR4-NEXT: blr
;
; ASM64PWR4-LABEL: test_ints_stack:
; ASM64PWR4: # %bb.0: # %entry
; ASM64PWR4-NEXT: add 3, 3, 4
-; ASM64PWR4-NEXT: ld 4, 112(1)
+; ASM64PWR4-NEXT: std 31, -8(1) # 8-byte Folded Spill
; ASM64PWR4-NEXT: add 3, 3, 5
; ASM64PWR4-NEXT: add 3, 3, 6
; ASM64PWR4-NEXT: add 3, 3, 7
-; ASM64PWR4-NEXT: lwa 12, 124(1)
+; ASM64PWR4-NEXT: std 2, -16(1) # 8-byte Folded Spill
; ASM64PWR4-NEXT: add 3, 3, 8
; ASM64PWR4-NEXT: add 3, 3, 9
+; ASM64PWR4-NEXT: ld 6, 112(1)
; ASM64PWR4-NEXT: add 3, 3, 10
; ASM64PWR4-NEXT: extsw 3, 3
-; ASM64PWR4-NEXT: lwz 5, 132(1)
-; ASM64PWR4-NEXT: add 3, 3, 4
+; ASM64PWR4-NEXT: lha 0, 126(1)
+; ASM64PWR4-NEXT: add 3, 3, 6
+; ASM64PWR4-NEXT: add 3, 3, 0
+; ASM64PWR4-NEXT: lbz 5, 135(1)
+; ASM64PWR4-NEXT: lwz 7, 140(1)
+; ASM64PWR4-NEXT: add 3, 3, 5
+; ASM64PWR4-NEXT: lwa 12, 148(1)
+; ASM64PWR4-NEXT: add 3, 3, 7
; ASM64PWR4-NEXT: add 3, 3, 12
-; ASM64PWR4-NEXT: std 2, -8(1) # 8-byte Folded Spill
+; ASM64PWR4-NEXT: ld 31, 152(1)
+; ASM64PWR4-NEXT: lbz 5, 167(1)
+; ASM64PWR4-NEXT: add 3, 3, 31
+; ASM64PWR4-NEXT: lwa 11, 172(1)
; ASM64PWR4-NEXT: add 3, 3, 5
-; ASM64PWR4-NEXT: lwz 2, 140(1)
-; ASM64PWR4-NEXT: lwa 11, 148(1)
-; ASM64PWR4-NEXT: add 3, 3, 2
; ASM64PWR4-NEXT: add 3, 3, 11
-; ASM64PWR4-NEXT: ld 4, 152(1)
-; ASM64PWR4-NEXT: lwz 0, 164(1)
+; ASM64PWR4-NEXT: lbz 2, 183(1)
+; ASM64PWR4-NEXT: lbz 6, 191(1)
+; ASM64PWR4-NEXT: extsb 4, 2
; ASM64PWR4-NEXT: add 3, 3, 4
-; ASM64PWR4-NEXT: lwa 5, 172(1)
-; ASM64PWR4-NEXT: add 3, 3, 0
-; ASM64PWR4-NEXT: add 3, 3, 5
-; ASM64PWR4-NEXT: ld 2, -8(1) # 8-byte Folded Reload
+; ASM64PWR4-NEXT: add 3, 3, 6
+; ASM64PWR4-NEXT: ld 2, -16(1) # 8-byte Folded Reload
+; ASM64PWR4-NEXT: ld 31, -8(1) # 8-byte Folded Reload
; ASM64PWR4-NEXT: blr
entry:
%add = add nsw i32 %i1, %i2
@@ -1277,7 +1294,11 @@ entry:
%add18 = add nsw i64 %add16, %conv17
%conv19 = sext i32 %i16 to i64
%add20 = add nsw i64 %add18, %conv19
- ret i64 %add20
+ %conv21 = sext i8 %si8 to i64
+ %add22 = add nsw i64 %add20, %conv21
+ %conv23 = zext i1 %zi1 to i64
+ %add24 = add nsw i64 %add22, %conv23
+ ret i64 %add24
}
@ll1 = common global i64 0, align 8
@@ -1720,17 +1741,17 @@ entry:
define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroext %c1, i16 signext %s1, i64 %ll1, i32 %i1, i32 %i2, i32 %i3) {
; ASM32PWR4-LABEL: mix_callee:
; ASM32PWR4: # %bb.0: # %entry
-; ASM32PWR4-NEXT: lwz 4, 60(1)
+; ASM32PWR4-NEXT: lha 3, 62(1)
; ASM32PWR4-NEXT: lis 8, 17200
; ASM32PWR4-NEXT: fadd 1, 1, 2
; ASM32PWR4-NEXT: fadd 1, 1, 3
-; ASM32PWR4-NEXT: lwz 5, 56(1)
-; ASM32PWR4-NEXT: lwz 3, 68(1)
-; ASM32PWR4-NEXT: add 4, 5, 4
-; ASM32PWR4-NEXT: lwz 5, L..C34(2) # %const.0
+; ASM32PWR4-NEXT: lbz 5, 59(1)
; ASM32PWR4-NEXT: fadd 1, 1, 4
+; ASM32PWR4-NEXT: lwz 4, 68(1)
+; ASM32PWR4-NEXT: add 3, 5, 3
+; ASM32PWR4-NEXT: lwz 5, L..C34(2) # %const.0
; ASM32PWR4-NEXT: lwz 6, 72(1)
-; ASM32PWR4-NEXT: add 3, 4, 3
+; ASM32PWR4-NEXT: add 3, 3, 4
; ASM32PWR4-NEXT: lwz 7, 76(1)
; ASM32PWR4-NEXT: add 3, 3, 6
; ASM32PWR4-NEXT: stw 8, -16(1)
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