[llvm] [RFC] TableGen-erate SDNode descriptions (PR #119709)
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Thu Dec 12 06:29:41 PST 2024
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git-clang-format --diff 625ec7ec8983e040c440928bc1b35143a6362eab 2a57488fae8ca00e6f65c462bbf162938445d031 --extensions h,cpp -- llvm/include/llvm/CodeGen/SDNodeInfo.h llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h llvm/lib/Target/ARC/ARCSelectionDAGInfo.cpp llvm/lib/Target/ARC/ARCSelectionDAGInfo.h llvm/lib/Target/AVR/AVRSelectionDAGInfo.cpp llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.cpp llvm/lib/Target/CSKY/CSKYSelectionDAGInfo.h llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.cpp llvm/lib/Target/LoongArch/LoongArchSelectionDAGInfo.h llvm/lib/Target/M68k/M68kSelectionDAGInfo.cpp llvm/lib/Target/M68k/M68kSelectionDAGInfo.h llvm/lib/Target/MSP430/MSP430SelectionDAGInfo.cpp llvm/lib/Target/MSP430/MSP430SelectionDAGInfo.h llvm/lib/Target/Mips/MipsSelectionDAGInfo.cpp llvm/lib/Target/Mips/MipsSelectionDAGInfo.h llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.cpp llvm/lib/Target/NVPTX/NVPTXSelectionDAGInfo.h llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.h llvm/lib/Target/Sparc/SparcSelectionDAGInfo.cpp llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h llvm/lib/Target/VE/VESelectionDAGInfo.cpp llvm/lib/Target/VE/VESelectionDAGInfo.h llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h llvm/utils/TableGen/SDNodeInfoEmitter.cpp llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/include/llvm/CodeGen/SelectionDAG.h llvm/include/llvm/CodeGen/SelectionDAGNodes.h llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGTargetInfo.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h llvm/lib/Target/AMDGPU/GCNSubtarget.cpp llvm/lib/Target/AMDGPU/GCNSubtarget.h llvm/lib/Target/AMDGPU/R600ISelLowering.cpp llvm/lib/Target/AMDGPU/R600Subtarget.cpp llvm/lib/Target/AMDGPU/R600Subtarget.h llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/ARC/ARCISelDAGToDAG.cpp llvm/lib/Target/ARC/ARCISelLowering.cpp llvm/lib/Target/ARC/ARCISelLowering.h llvm/lib/Target/ARC/ARCSubtarget.cpp llvm/lib/Target/ARC/ARCSubtarget.h llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.h llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp llvm/lib/Target/ARM/ARMSelectionDAGInfo.h llvm/lib/Target/AVR/AVRISelLowering.cpp llvm/lib/Target/AVR/AVRISelLowering.h llvm/lib/Target/AVR/AVRSelectionDAGInfo.h llvm/lib/Target/BPF/BPFISelLowering.cpp llvm/lib/Target/BPF/BPFISelLowering.h llvm/lib/Target/BPF/BPFSelectionDAGInfo.cpp llvm/lib/Target/BPF/BPFSelectionDAGInfo.h llvm/lib/Target/CSKY/CSKYISelLowering.cpp llvm/lib/Target/CSKY/CSKYISelLowering.h llvm/lib/Target/CSKY/CSKYSubtarget.cpp llvm/lib/Target/CSKY/CSKYSubtarget.h llvm/lib/Target/Hexagon/HexagonISelLowering.cpp llvm/lib/Target/Hexagon/HexagonISelLowering.h llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h llvm/lib/Target/Lanai/LanaiISelLowering.cpp llvm/lib/Target/Lanai/LanaiISelLowering.h llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp llvm/lib/Target/LoongArch/LoongArchISelLowering.h llvm/lib/Target/LoongArch/LoongArchSubtarget.cpp llvm/lib/Target/LoongArch/LoongArchSubtarget.h llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp llvm/lib/Target/M68k/M68kISelLowering.cpp llvm/lib/Target/M68k/M68kISelLowering.h llvm/lib/Target/M68k/M68kSubtarget.cpp llvm/lib/Target/M68k/M68kSubtarget.h llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp llvm/lib/Target/MSP430/MSP430ISelLowering.cpp llvm/lib/Target/MSP430/MSP430ISelLowering.h llvm/lib/Target/MSP430/MSP430Subtarget.cpp llvm/lib/Target/MSP430/MSP430Subtarget.h llvm/lib/Target/Mips/MipsISelLowering.cpp llvm/lib/Target/Mips/MipsISelLowering.h llvm/lib/Target/Mips/MipsSubtarget.cpp llvm/lib/Target/Mips/MipsSubtarget.h llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.h llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp llvm/lib/Target/NVPTX/NVPTXSubtarget.h llvm/lib/Target/PowerPC/PPCFastISel.cpp llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/lib/Target/PowerPC/PPCISelLowering.h llvm/lib/Target/PowerPC/PPCSubtarget.cpp llvm/lib/Target/PowerPC/PPCSubtarget.h llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h llvm/lib/Target/RISCV/RISCVTargetMachine.h llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp llvm/lib/Target/Sparc/SparcISelLowering.cpp llvm/lib/Target/Sparc/SparcISelLowering.h llvm/lib/Target/Sparc/SparcSubtarget.cpp llvm/lib/Target/Sparc/SparcSubtarget.h llvm/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.h llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h llvm/lib/Target/VE/VECustomDAG.cpp llvm/lib/Target/VE/VEISelDAGToDAG.cpp llvm/lib/Target/VE/VEISelLowering.cpp llvm/lib/Target/VE/VEISelLowering.h llvm/lib/Target/VE/VESubtarget.cpp llvm/lib/Target/VE/VESubtarget.h llvm/lib/Target/VE/VVPISelLowering.cpp llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.h llvm/lib/Target/X86/X86ISelLoweringCall.cpp llvm/lib/Target/X86/X86SelectionDAGInfo.cpp llvm/lib/Target/X86/X86SelectionDAGInfo.h llvm/lib/Target/XCore/XCoreISelLowering.cpp llvm/lib/Target/XCore/XCoreISelLowering.h llvm/lib/Target/XCore/XCoreSelectionDAGInfo.cpp llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp llvm/lib/Target/Xtensa/XtensaISelLowering.cpp llvm/lib/Target/Xtensa/XtensaISelLowering.h llvm/lib/Target/Xtensa/XtensaSubtarget.cpp llvm/lib/Target/Xtensa/XtensaSubtarget.h llvm/utils/TableGen/Basic/SequenceToOffsetTable.h llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp llvm/utils/TableGen/Common/CodeGenDAGPatterns.h llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
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diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1bfd26b4cc..2c0f39de5b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -8978,9 +8978,10 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
SDVTList VTList,
ArrayRef<SDValue> Ops, EVT MemVT,
MachineMemOperand *MMO) {
- assert((Opcode == ISD::INTRINSIC_VOID || Opcode == ISD::INTRINSIC_W_CHAIN ||
- Opcode == ISD::PREFETCH ||
- (Opcode <= (unsigned)std::numeric_limits<int>::max() &&
+ assert(
+ (Opcode == ISD::INTRINSIC_VOID || Opcode == ISD::INTRINSIC_W_CHAIN ||
+ Opcode == ISD::PREFETCH ||
+ (Opcode <= (unsigned)std::numeric_limits<int>::max() &&
Opcode >= ISD::BUILTIN_OP_END && TSI->isTargetMemoryOpcode(Opcode))) &&
"Opcode is not a memory-accessing opcode!");
diff --git a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
index 3bc3ea999e..ff426019c3 100644
--- a/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
+++ b/llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
@@ -134,7 +134,6 @@ public:
SDValue Size, unsigned Align,
RTLIB::Libcall LC) const;
};
-
}
#endif
diff --git a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
index ab36f60005..1faf18843e 100644
--- a/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
+++ b/llvm/lib/Target/BPF/BPFSelectionDAGInfo.h
@@ -35,9 +35,7 @@ public:
MachinePointerInfo SrcPtrInfo) const override;
unsigned getCommonMaxStoresPerMemFunc() const { return 128; }
-
};
-
}
#endif
diff --git a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
index c62be58901..9ffb6f6893 100644
--- a/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
@@ -85,7 +85,6 @@ public:
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
};
-
}
#endif
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.h b/llvm/lib/Target/MSP430/MSP430ISelLowering.h
index 6d89538f6b..6c08bee6bc 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.h
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.h
@@ -19,117 +19,113 @@
#include "llvm/CodeGen/TargetLowering.h"
namespace llvm {
- class MSP430Subtarget;
- class MSP430TargetLowering : public TargetLowering {
- public:
- explicit MSP430TargetLowering(const TargetMachine &TM,
- const MSP430Subtarget &STI);
-
- MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
- return MVT::i8;
- }
-
- MVT::SimpleValueType getCmpLibcallReturnType() const override {
- return MVT::i16;
- }
-
- /// LowerOperation - Provide custom lowering hooks for some operations.
- SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
-
- SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
- SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
-
- TargetLowering::ConstraintType
- getConstraintType(StringRef Constraint) const override;
- std::pair<unsigned, const TargetRegisterClass *>
- getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
- StringRef Constraint, MVT VT) const override;
-
- /// isTruncateFree - Return true if it's free to truncate a value of type
- /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
- /// register R15W to i8 by referencing its sub-register R15B.
- bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
- bool isTruncateFree(EVT VT1, EVT VT2) const override;
-
- /// isZExtFree - Return true if any actual instruction that defines a value
- /// of type Ty1 implicit zero-extends the value to Ty2 in the result
- /// register. This does not necessarily include registers defined in unknown
- /// ways, such as incoming arguments, or copies from unknown virtual
- /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
- /// necessarily apply to truncate instructions. e.g. on msp430, all
- /// instructions that define 8-bit values implicit zero-extend the result
- /// out to 16 bits.
- bool isZExtFree(Type *Ty1, Type *Ty2) const override;
- bool isZExtFree(EVT VT1, EVT VT2) const override;
-
- bool isLegalICmpImmediate(int64_t) const override;
- bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
-
- MachineBasicBlock *
- EmitInstrWithCustomInserter(MachineInstr &MI,
- MachineBasicBlock *BB) const override;
- MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
- MachineBasicBlock *BB) const;
-
- private:
- SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
- CallingConv::ID CallConv, bool isVarArg,
- bool isTailCall,
- const SmallVectorImpl<ISD::OutputArg> &Outs,
- const SmallVectorImpl<SDValue> &OutVals,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- const SDLoc &dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const;
-
- SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
- bool isVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- const SDLoc &dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const;
-
- SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
- CallingConv::ID CallConv, bool isVarArg,
+class MSP430Subtarget;
+class MSP430TargetLowering : public TargetLowering {
+public:
+ explicit MSP430TargetLowering(const TargetMachine &TM,
+ const MSP430Subtarget &STI);
+
+ MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
+ return MVT::i8;
+ }
+
+ MVT::SimpleValueType getCmpLibcallReturnType() const override {
+ return MVT::i16;
+ }
+
+ /// LowerOperation - Provide custom lowering hooks for some operations.
+ SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+
+ SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
+ SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
+
+ TargetLowering::ConstraintType
+ getConstraintType(StringRef Constraint) const override;
+ std::pair<unsigned, const TargetRegisterClass *>
+ getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+ StringRef Constraint, MVT VT) const override;
+
+ /// isTruncateFree - Return true if it's free to truncate a value of type
+ /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
+ /// register R15W to i8 by referencing its sub-register R15B.
+ bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
+ bool isTruncateFree(EVT VT1, EVT VT2) const override;
+
+ /// isZExtFree - Return true if any actual instruction that defines a value
+ /// of type Ty1 implicit zero-extends the value to Ty2 in the result
+ /// register. This does not necessarily include registers defined in unknown
+ /// ways, such as incoming arguments, or copies from unknown virtual
+ /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
+ /// necessarily apply to truncate instructions. e.g. on msp430, all
+ /// instructions that define 8-bit values implicit zero-extend the result
+ /// out to 16 bits.
+ bool isZExtFree(Type *Ty1, Type *Ty2) const override;
+ bool isZExtFree(EVT VT1, EVT VT2) const override;
+
+ bool isLegalICmpImmediate(int64_t) const override;
+ bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
+
+ MachineBasicBlock *
+ EmitInstrWithCustomInserter(MachineInstr &MI,
+ MachineBasicBlock *BB) const override;
+ MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
+ MachineBasicBlock *BB) const;
+
+private:
+ SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
+ CallingConv::ID CallConv, bool isVarArg,
+ bool isTailCall,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ const SDLoc &dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const;
+
+ SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
+ bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
- SDValue
- LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- const SDLoc &dl, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &InVals) const override;
- SDValue
- LowerCall(TargetLowering::CallLoweringInfo &CLI,
- SmallVectorImpl<SDValue> &InVals) const override;
-
- bool CanLowerReturn(CallingConv::ID CallConv,
- MachineFunction &MF,
- bool IsVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs,
- LLVMContext &Context) const override;
-
- SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs,
- const SmallVectorImpl<SDValue> &OutVals,
- const SDLoc &dl, SelectionDAG &DAG) const override;
-
- bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
- SDValue &Base,
- SDValue &Offset,
- ISD::MemIndexedMode &AM,
- SelectionDAG &DAG) const override;
+ SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ const SDLoc &dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const;
+
+ SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
+ bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ const SDLoc &dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const override;
+ SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
+ SmallVectorImpl<SDValue> &InVals) const override;
+
+ bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+ bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext &Context) const override;
+
+ SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
+ SelectionDAG &DAG) const override;
+
+ bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
+ SDValue &Offset, ISD::MemIndexedMode &AM,
+ SelectionDAG &DAG) const override;
};
-} // namespace llvm
+ } // namespace llvm
#endif
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 9f1a106f80..2ef658e6f7 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1712,7 +1712,7 @@ SDValue WebAssemblyTargetLowering::LowerLoad(SDValue Op,
SDValue Idx = DAG.getTargetConstant(*Local, Base, MVT::i32);
EVT LocalVT = LN->getValueType(0);
SDValue LocalGet = DAG.getNode(WebAssemblyISD::LOCAL_GET, DL, LocalVT,
- {LN->getChain(), Idx});
+ {LN->getChain(), Idx});
SDValue Result = DAG.getMergeValues({LocalGet, LN->getChain()}, DL);
assert(Result->getNumValues() == 2 && "Loads must carry a chain!");
return Result;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 94c80133b5..66d6988d6f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -26858,8 +26858,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SDVTList VTs = DAG.getVTList(MVT::Untyped, MVT::Other);
SDLoc DL(Op);
- SDValue Operation =
- DAG.getNode(X86ISD::VP2INTERSECT, DL, VTs,
+ SDValue Operation = DAG.getNode(X86ISD::VP2INTERSECT, DL, VTs,
Op->getOperand(1), Op->getOperand(2));
SDValue Result0 = DAG.getTargetExtractSubreg(X86::sub_mask_0, DL,
diff --git a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
index 04734699a0..6c285e1650 100644
--- a/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
+++ b/llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h
@@ -31,7 +31,6 @@ public:
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const override;
};
-
}
#endif
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index 9b35a8fa8c..c15915ae19 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -1,4 +1,5 @@
-//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===//
+//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp
+//-------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -138,7 +139,8 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) {
EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 15u);
}
-TEST_F(AArch64SelectionDAGTest, ComputeNumSignBitsSVE_SIGN_EXTEND_VECTOR_INREG) {
+TEST_F(AArch64SelectionDAGTest,
+ ComputeNumSignBitsSVE_SIGN_EXTEND_VECTOR_INREG) {
SDLoc Loc;
auto Int8VT = EVT::getIntegerVT(Context, 8);
auto Int16VT = EVT::getIntegerVT(Context, 16);
@@ -447,7 +449,7 @@ TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_SPLAT_VECTOR) {
EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
APInt UndefElts;
- APInt DemandedElts(1,1);
+ APInt DemandedElts(1, 1);
EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
}
@@ -486,7 +488,8 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_BUILD_VECTOR) {
EXPECT_EQ(SplatIdx, 0);
}
-TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_ADD_of_BUILD_VECTOR) {
+TEST_F(AArch64SelectionDAGTest,
+ getSplatSourceVector_Fixed_ADD_of_BUILD_VECTOR) {
TargetLowering TL(*TM);
SDLoc Loc;
@@ -519,7 +522,8 @@ TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_SPLAT_VECTOR) {
EXPECT_EQ(SplatIdx, 0);
}
-TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTOR) {
+TEST_F(AArch64SelectionDAGTest,
+ getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTOR) {
TargetLowering TL(*TM);
SDLoc Loc;
@@ -554,7 +558,7 @@ TEST_F(AArch64SelectionDAGTest, getRepeatedSequence_Patterns) {
// Build some repeating sequences.
SmallVector<SDValue, 16> Pattern1111, Pattern1133, Pattern0123;
- for(int I = 0; I != 4; ++I) {
+ for (int I = 0; I != 4; ++I) {
Pattern1111.append(4, Val1);
Pattern1133.append(2, Val1);
Pattern1133.append(2, Val3);
@@ -591,7 +595,7 @@ TEST_F(AArch64SelectionDAGTest, getRepeatedSequence_Patterns) {
cast<BuildVectorSDNode>(DAG->getBuildVector(VecVT, Loc, Pattern1111));
auto *BV1133 =
cast<BuildVectorSDNode>(DAG->getBuildVector(VecVT, Loc, Pattern1133));
- auto *BV0123=
+ auto *BV0123 =
cast<BuildVectorSDNode>(DAG->getBuildVector(VecVT, Loc, Pattern0123));
auto *BV022 =
cast<BuildVectorSDNode>(DAG->getBuildVector(VecVT, Loc, Pattern022));
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index ebd4d22123..86071cf358 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -1708,7 +1708,8 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode &N,
llvm_unreachable("Invalid ConstraintType!");
}
-bool llvm::operator==(const SDTypeConstraint &LHS, const SDTypeConstraint &RHS) {
+bool llvm::operator==(const SDTypeConstraint &LHS,
+ const SDTypeConstraint &RHS) {
if (std::tie(LHS.OperandNo, LHS.ConstraintType) !=
std::tie(RHS.OperandNo, RHS.ConstraintType))
return false;
@@ -1729,7 +1730,7 @@ bool llvm::operator==(const SDTypeConstraint &LHS, const SDTypeConstraint &RHS)
case SDTypeConstraint::SDTCisSameNumEltsAs:
case SDTypeConstraint::SDTCisSameSizeAs:
return LHS.x.SDTCisSameSizeAs_Info.OtherOperandNum ==
- RHS.x.SDTCisSameSizeAs_Info.OtherOperandNum;
+ RHS.x.SDTCisSameSizeAs_Info.OtherOperandNum;
}
return true;
}
@@ -1738,7 +1739,7 @@ bool llvm::operator<(const SDTypeConstraint &LHS, const SDTypeConstraint &RHS) {
if (std::tie(LHS.OperandNo, LHS.ConstraintType) !=
std::tie(RHS.OperandNo, RHS.ConstraintType))
return std::tie(LHS.OperandNo, LHS.ConstraintType) <
- std::tie(RHS.OperandNo, RHS.ConstraintType);
+ std::tie(RHS.OperandNo, RHS.ConstraintType);
switch (LHS.ConstraintType) {
case SDTypeConstraint::SDTCisVT:
case SDTypeConstraint::SDTCVecEltisVT:
@@ -1756,7 +1757,7 @@ bool llvm::operator<(const SDTypeConstraint &LHS, const SDTypeConstraint &RHS) {
case SDTypeConstraint::SDTCisSameNumEltsAs:
case SDTypeConstraint::SDTCisSameSizeAs:
return LHS.x.SDTCisSameSizeAs_Info.OtherOperandNum <
- RHS.x.SDTCisSameSizeAs_Info.OtherOperandNum;
+ RHS.x.SDTCisSameSizeAs_Info.OtherOperandNum;
}
return false;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/119709
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