[llvm] 625ec7e - [VectorCombine] Move concat-boolmasks.ll tests to be VectorCombine only

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-12-12T11:02:01Z
New Revision: 625ec7ec8983e040c440928bc1b35143a6362eab

URL: https://github.com/llvm/llvm-project/commit/625ec7ec8983e040c440928bc1b35143a6362eab
DIFF: https://github.com/llvm/llvm-project/commit/625ec7ec8983e040c440928bc1b35143a6362eab.diff

LOG: [VectorCombine] Move concat-boolmasks.ll tests to be VectorCombine only

Suggested on #119559

Added: 
    llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll

Modified: 
    

Removed: 
    llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll b/llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
similarity index 90%
rename from llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
rename to llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
index 07bfbffa9518fa..1aa03eedc5eb03 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/concat-boolmasks.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/concat-boolmasks.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s
-; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
-; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
-; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
+; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s
+; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
+; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
+; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
 
 define i32 @movmsk_i32_v32i8_v16i8(<16 x i8> %v0, <16 x i8> %v1) {
 ; CHECK-LABEL: @movmsk_i32_v32i8_v16i8(
@@ -35,7 +35,7 @@ define i32 @movmsk_i32_v8i32_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
 ; CHECK-NEXT:    [[B1:%.*]] = bitcast <4 x i1> [[C1]] to i4
 ; CHECK-NEXT:    [[Z0:%.*]] = zext i4 [[B0]] to i32
 ; CHECK-NEXT:    [[Z1:%.*]] = zext i4 [[B1]] to i32
-; CHECK-NEXT:    [[S0:%.*]] = shl nuw nsw i32 [[Z0]], 4
+; CHECK-NEXT:    [[S0:%.*]] = shl nuw i32 [[Z0]], 4
 ; CHECK-NEXT:    [[OR:%.*]] = or disjoint i32 [[S0]], [[Z1]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
@@ -58,7 +58,7 @@ define i64 @movmsk_i64_v32i8_v16i8(<16 x i8> %v0, <16 x i8> %v1) {
 ; CHECK-NEXT:    [[B1:%.*]] = bitcast <16 x i1> [[C1]] to i16
 ; CHECK-NEXT:    [[Z0:%.*]] = zext i16 [[B0]] to i64
 ; CHECK-NEXT:    [[Z1:%.*]] = zext i16 [[B1]] to i64
-; CHECK-NEXT:    [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 16
+; CHECK-NEXT:    [[S0:%.*]] = shl nuw i64 [[Z0]], 16
 ; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[S0]], [[Z1]]
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
@@ -81,7 +81,7 @@ define i64 @movmsk_i64_v8i32_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
 ; CHECK-NEXT:    [[B1:%.*]] = bitcast <4 x i1> [[C1]] to i4
 ; CHECK-NEXT:    [[Z0:%.*]] = zext i4 [[B0]] to i64
 ; CHECK-NEXT:    [[Z1:%.*]] = zext i4 [[B1]] to i64
-; CHECK-NEXT:    [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 4
+; CHECK-NEXT:    [[S0:%.*]] = shl nuw i64 [[Z0]], 4
 ; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[S0]], [[Z1]]
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
@@ -111,11 +111,11 @@ define i64 @movmsk_i64_v64i8_v16i8(<16 x i8> %v0, <16 x i8> %v1, <16 x i8> %v2,
 ; CHECK-NEXT:    [[Z2:%.*]] = zext i16 [[B2]] to i64
 ; CHECK-NEXT:    [[Z3:%.*]] = zext i16 [[B3]] to i64
 ; CHECK-NEXT:    [[S0:%.*]] = shl nuw i64 [[Z0]], 48
-; CHECK-NEXT:    [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 32
-; CHECK-NEXT:    [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16
-; CHECK-NEXT:    [[OR0:%.*]] = or disjoint i64 [[S1]], [[S0]]
+; CHECK-NEXT:    [[S1:%.*]] = shl nuw i64 [[Z1]], 32
+; CHECK-NEXT:    [[S2:%.*]] = shl nuw i64 [[Z2]], 16
+; CHECK-NEXT:    [[OR0:%.*]] = or disjoint i64 [[S0]], [[S1]]
 ; CHECK-NEXT:    [[OR1:%.*]] = or disjoint i64 [[S2]], [[Z3]]
-; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[OR1]], [[OR0]]
+; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[OR0]], [[OR1]]
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
   %c0 = icmp slt <16 x i8> %v0, zeroinitializer
@@ -153,12 +153,12 @@ define i64 @movmsk_i64_v32i32_v4i32(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2,
 ; CHECK-NEXT:    [[Z1:%.*]] = zext i4 [[B1]] to i64
 ; CHECK-NEXT:    [[Z2:%.*]] = zext i4 [[B2]] to i64
 ; CHECK-NEXT:    [[Z3:%.*]] = zext i4 [[B3]] to i64
-; CHECK-NEXT:    [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 12
-; CHECK-NEXT:    [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8
-; CHECK-NEXT:    [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 4
+; CHECK-NEXT:    [[S1:%.*]] = shl nuw i64 [[Z0]], 12
+; CHECK-NEXT:    [[S0:%.*]] = shl nuw i64 [[Z1]], 8
+; CHECK-NEXT:    [[S2:%.*]] = shl nuw i64 [[Z2]], 4
 ; CHECK-NEXT:    [[OR0:%.*]] = or disjoint i64 [[S1]], [[S0]]
 ; CHECK-NEXT:    [[OR1:%.*]] = or disjoint i64 [[S2]], [[Z3]]
-; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[OR1]], [[OR0]]
+; CHECK-NEXT:    [[OR:%.*]] = or disjoint i64 [[OR0]], [[OR1]]
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
   %c0 = icmp slt <4 x i32> %v0, zeroinitializer
@@ -213,7 +213,7 @@ define i32 @movmsk_i32_v16i32_v8i32(<8 x i32> %v0, <8 x i32> %v1) {
 ; CHECK-NEXT:    [[B1:%.*]] = bitcast <8 x i1> [[C1]] to i8
 ; CHECK-NEXT:    [[Z0:%.*]] = zext i8 [[B0]] to i32
 ; CHECK-NEXT:    [[Z1:%.*]] = zext i8 [[B1]] to i32
-; CHECK-NEXT:    [[S0:%.*]] = shl nuw nsw i32 [[Z0]], 8
+; CHECK-NEXT:    [[S0:%.*]] = shl nuw i32 [[Z0]], 8
 ; CHECK-NEXT:    [[OR:%.*]] = or disjoint i32 [[S0]], [[Z1]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;