[clang] [llvm] [RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (PR #119504)

[via llvm-commits]

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@@ -57,6 +57,86 @@ class QCIRVInstRR<bits<5> func5, DAGOperand InTyRs1, string opcodestr>
     : RVInstR<{0b00, func5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd),
               (ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class QCISELECTIICC<bits<3> func3, string opcodestr>
+    : RVInst<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1,
+                            simm5:$simm5, simm5:$simm), opcodestr,
+                            "$rd, $rs1, $simm5, $simm", [], InstFormatR4> {
+  let Constraints = "$rd = $rd_wb";
+  bits<5> simm;
+  bits<5> simm5;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = simm;
+  let Inst{26-25} = 0b00;
+  let Inst{24-20} = simm5;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = func3;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = 0b1011011;
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hchandel wrote:

Done

https://github.com/llvm/llvm-project/pull/119504