[llvm] da71203 - [MISched] Unify the way to specify scheduling direction (#119518)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 19:24:12 PST 2024
Author: Pengcheng Wang
Date: 2024-12-12T11:24:07+08:00
New Revision: da71203e6fc6b8e08c9979204506d385e9cb07b8
URL: https://github.com/llvm/llvm-project/commit/da71203e6fc6b8e08c9979204506d385e9cb07b8
DIFF: https://github.com/llvm/llvm-project/commit/da71203e6fc6b8e08c9979204506d385e9cb07b8.diff
LOG: [MISched] Unify the way to specify scheduling direction (#119518)
For pre-ra scheduling, we use two options `-misched-topdown` and
`-misched-bottomup` to force the direction.
While for post-ra scheduling, we use `-misched-postra-direction`
with enumerated values (`topdown`, `bottomup` and `bidirectional`).
This is not unified and adds some mental burdens. Here we replace
these two options `-misched-topdown` and `-misched-bottomup` with
`-misched-prera-direction` with the same enumerated values.
To avoid the condition of `getNumOccurrences() > 0`, we add a new
enum value `Unspecified` and make it the default initial value.
These options are hidden, so we needn't keep the compatibility.
Added:
Modified:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/VLIWMachineScheduler.cpp
llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
llvm/test/CodeGen/AArch64/force-enable-intervals.mir
llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
llvm/test/CodeGen/ARM/single-issue-r52.mir
llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
llvm/test/CodeGen/X86/handle-move.ll
llvm/test/CodeGen/X86/misched-aa-colored.ll
llvm/test/CodeGen/X86/misched-matrix.ll
llvm/test/CodeGen/X86/misched-new.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 42d132efec2e7c..3dd62b2ba333c3 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -99,8 +99,16 @@
namespace llvm {
-extern cl::opt<bool> ForceTopDown;
-extern cl::opt<bool> ForceBottomUp;
+namespace MISched {
+enum Direction {
+ Unspecified,
+ TopDown,
+ BottomUp,
+ Bidirectional,
+};
+} // namespace MISched
+
+extern cl::opt<MISched::Direction> PreRADirection;
extern cl::opt<bool> VerifyScheduling;
#ifndef NDEBUG
extern cl::opt<bool> ViewMISchedDAGs;
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 1722bdda99e4af..91aaeea156c4a1 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -77,30 +77,30 @@ STATISTIC(NumClustered, "Number of load/store pairs clustered");
namespace llvm {
-cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
- cl::desc("Force top-down list scheduling"));
-cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
- cl::desc("Force bottom-up list scheduling"));
-namespace MISchedPostRASched {
-enum Direction {
- TopDown,
- BottomUp,
- Bidirectional,
-};
-} // end namespace MISchedPostRASched
-cl::opt<MISchedPostRASched::Direction> PostRADirection(
+cl::opt<MISched::Direction> PreRADirection(
+ "misched-prera-direction", cl::Hidden,
+ cl::desc("Pre reg-alloc list scheduling direction"),
+ cl::init(MISched::Unspecified),
+ cl::values(
+ clEnumValN(MISched::TopDown, "topdown",
+ "Force top-down pre reg-alloc list scheduling"),
+ clEnumValN(MISched::BottomUp, "bottomup",
+ "Force bottom-up pre reg-alloc list scheduling"),
+ clEnumValN(MISched::Bidirectional, "bidirectional",
+ "Force bidirectional pre reg-alloc list scheduling")));
+
+cl::opt<MISched::Direction> PostRADirection(
"misched-postra-direction", cl::Hidden,
cl::desc("Post reg-alloc list scheduling direction"),
- // Default to top-down because it was implemented first and existing targets
- // expect that behavior by default.
- cl::init(MISchedPostRASched::TopDown),
+ cl::init(MISched::Unspecified),
cl::values(
- clEnumValN(MISchedPostRASched::TopDown, "topdown",
+ clEnumValN(MISched::TopDown, "topdown",
"Force top-down post reg-alloc list scheduling"),
- clEnumValN(MISchedPostRASched::BottomUp, "bottomup",
+ clEnumValN(MISched::BottomUp, "bottomup",
"Force bottom-up post reg-alloc list scheduling"),
- clEnumValN(MISchedPostRASched::Bidirectional, "bidirectional",
+ clEnumValN(MISched::Bidirectional, "bidirectional",
"Force bidirectional post reg-alloc list scheduling")));
+
cl::opt<bool>
DumpCriticalPathLength("misched-dcpl", cl::Hidden,
cl::desc("Print critical path length to stdout"));
@@ -3307,19 +3307,15 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
RegionPolicy.ShouldTrackLaneMasks = false;
}
- // Check -misched-topdown/bottomup can force or unforce scheduling direction.
- // e.g. -misched-bottomup=false allows scheduling in both directions.
- assert((!ForceTopDown || !ForceBottomUp) &&
- "-misched-topdown incompatible with -misched-bottomup");
- if (ForceBottomUp.getNumOccurrences() > 0) {
- RegionPolicy.OnlyBottomUp = ForceBottomUp;
- if (RegionPolicy.OnlyBottomUp)
- RegionPolicy.OnlyTopDown = false;
- }
- if (ForceTopDown.getNumOccurrences() > 0) {
- RegionPolicy.OnlyTopDown = ForceTopDown;
- if (RegionPolicy.OnlyTopDown)
- RegionPolicy.OnlyBottomUp = false;
+ if (PreRADirection == MISched::TopDown) {
+ RegionPolicy.OnlyTopDown = true;
+ RegionPolicy.OnlyBottomUp = false;
+ } else if (PreRADirection == MISched::BottomUp) {
+ RegionPolicy.OnlyTopDown = false;
+ RegionPolicy.OnlyBottomUp = true;
+ } else if (PreRADirection == MISched::Bidirectional) {
+ RegionPolicy.OnlyBottomUp = false;
+ RegionPolicy.OnlyTopDown = false;
}
}
@@ -3911,17 +3907,15 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, NumRegionInstrs);
// After subtarget overrides, apply command line options.
- if (PostRADirection.getNumOccurrences() > 0) {
- if (PostRADirection == MISchedPostRASched::TopDown) {
- RegionPolicy.OnlyTopDown = true;
- RegionPolicy.OnlyBottomUp = false;
- } else if (PostRADirection == MISchedPostRASched::BottomUp) {
- RegionPolicy.OnlyTopDown = false;
- RegionPolicy.OnlyBottomUp = true;
- } else if (PostRADirection == MISchedPostRASched::Bidirectional) {
- RegionPolicy.OnlyBottomUp = false;
- RegionPolicy.OnlyTopDown = false;
- }
+ if (PostRADirection == MISched::TopDown) {
+ RegionPolicy.OnlyTopDown = true;
+ RegionPolicy.OnlyBottomUp = false;
+ } else if (PostRADirection == MISched::BottomUp) {
+ RegionPolicy.OnlyTopDown = false;
+ RegionPolicy.OnlyBottomUp = true;
+ } else if (PostRADirection == MISched::Bidirectional) {
+ RegionPolicy.OnlyBottomUp = false;
+ RegionPolicy.OnlyTopDown = false;
}
}
@@ -4368,10 +4362,9 @@ class InstructionShuffler : public MachineSchedStrategy {
} // end anonymous namespace
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
- bool Alternate = !ForceTopDown && !ForceBottomUp;
- bool TopDown = !ForceBottomUp;
- assert((TopDown || !ForceTopDown) &&
- "-misched-topdown incompatible with -misched-bottomup");
+ bool Alternate =
+ PreRADirection != MISched::TopDown && PreRADirection != MISched::BottomUp;
+ bool TopDown = PreRADirection != MISched::BottomUp;
return new ScheduleDAGMILive(
C, std::make_unique<InstructionShuffler>(Alternate, TopDown));
}
diff --git a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
index 0cddf59d0ca2ac..2fd1dd5f84a91e 100644
--- a/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
+++ b/llvm/lib/CodeGen/VLIWMachineScheduler.cpp
@@ -297,9 +297,6 @@ void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
HighPressureSets[i] =
((float)MaxPressure[i] > ((float)Limit * RPThreshold));
}
-
- assert((!ForceTopDown || !ForceBottomUp) &&
- "-misched-topdown incompatible with -misched-bottomup");
}
VLIWResourceModel *ConvergingVLIWScheduler::createVLIWResourceModel(
@@ -954,7 +951,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
return nullptr;
}
SUnit *SU;
- if (ForceTopDown) {
+ if (PreRADirection == MISched::TopDown) {
SU = Top.pickOnlyChoice();
if (!SU) {
SchedCandidate TopCand;
@@ -965,7 +962,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
SU = TopCand.SU;
}
IsTopNode = true;
- } else if (ForceBottomUp) {
+ } else if (PreRADirection == MISched::BottomUp) {
SU = Bot.pickOnlyChoice();
if (!SU) {
SchedCandidate BotCand;
diff --git a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
index 2a8961649b26cd..bff6d1d71b7c44 100644
--- a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
+++ b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
@@ -1,12 +1,12 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-topdown=true -sched-print-cycles=true \
+# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
# RUN: 2>&1 | FileCheck %s --check-prefix=TOP --strict-whitespace
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-bottomup=true -sched-print-cycles=true \
+# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
# RUN: 2>&1 | FileCheck %s --check-prefix=BOTTOM --strict-whitespace
diff --git a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
index 98bee7a579c05a..a53d4e7480307d 100644
--- a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
+++ b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
@@ -1,12 +1,12 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -misched-dump-reserved-cycles=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -o - %s 2>&1 -misched-topdown| FileCheck %s
+# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -o - %s 2>&1 -misched-topdown| FileCheck %s --check-prefix=FORCE
+# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE
# REQUIRES: asserts, aarch64-registered-target
---
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
index 6fb8ba2dfc839e..ea40f9e52dcd68 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
@@ -1,7 +1,7 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -mcpu=cortex-a55 %s -o - 2>&1 \
# RUN: -misched-dump-reserved-cycles=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -misched-bottomup=true -sched-print-cycles=true \
+# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
# RUN: -misched-detail-resource-booking=true \
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
# RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
index 9c9b6e281b15da..9be91b8a01e86b 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
@@ -1,6 +1,6 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-bottomup=true -sched-print-cycles=true \
+# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
# RUN: -misched-dump-reserved-cycles=true -misched-detail-resource-booking=true\
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
# RUN: 2>&1 | FileCheck %s
diff --git a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
index 4b77444ec60d28..b04fd89b796ba7 100644
--- a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
+++ b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
@@ -1,11 +1,11 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-topdown=true -sched-print-cycles=true \
+# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-topdown=true -sched-print-cycles=true \
+# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s
# REQUIRES: asserts, aarch64-registered-target
diff --git a/llvm/test/CodeGen/ARM/single-issue-r52.mir b/llvm/test/CodeGen/ARM/single-issue-r52.mir
index 084afb6f666c1c..d01ef82617f230 100644
--- a/llvm/test/CodeGen/ARM/single-issue-r52.mir
+++ b/llvm/test/CodeGen/ARM/single-issue-r52.mir
@@ -1,7 +1,7 @@
-# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
-# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
-# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
-# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
+# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
+# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
+# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN
+# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-prera-direction=bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP
# REQUIRES: asserts
--- |
; ModuleID = 'foo.ll'
diff --git a/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir b/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
index e179e7f08752a8..ec8a57d14e8f2d 100644
--- a/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
+++ b/llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
@@ -1,6 +1,6 @@
# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler \
# RUN: -debug-only=machine-scheduler -misched-dump-schedule-trace \
-# RUN: -misched-topdown -o - %s 2>&1 | FileCheck %s
+# RUN: -misched-prera-direction=topdown -o - %s 2>&1 | FileCheck %s
# REQUIRES: asserts
# The purpose of this test is to show that the VADD instructions are issued so
diff --git a/llvm/test/CodeGen/X86/handle-move.ll b/llvm/test/CodeGen/X86/handle-move.ll
index 0a43ef3fc22d4a..c6da9589ff4652 100644
--- a/llvm/test/CodeGen/X86/handle-move.ll
+++ b/llvm/test/CodeGen/X86/handle-move.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=x86_64-- -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-bottomup -verify-machineinstrs < %s
-; RUN: llc -mtriple=x86_64-- -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-topdown -verify-machineinstrs < %s
+; RUN: llc -mtriple=x86_64-- -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-prera-direction=bottomup -verify-machineinstrs < %s
+; RUN: llc -mtriple=x86_64-- -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-prera-direction=topdown -verify-machineinstrs < %s
; REQUIRES: asserts
;
; Test the LiveIntervals::handleMove() function.
diff --git a/llvm/test/CodeGen/X86/misched-aa-colored.ll b/llvm/test/CodeGen/X86/misched-aa-colored.ll
index 73626de163d007..3504e555cd9ca0 100644
--- a/llvm/test/CodeGen/X86/misched-aa-colored.ll
+++ b/llvm/test/CodeGen/X86/misched-aa-colored.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=x86-64 -enable-misched -misched-bottomup=0 -misched-topdown=0 -misched=shuffle -enable-aa-sched-mi | FileCheck %s
+; RUN: llc < %s -mcpu=x86-64 -enable-misched -misched-prera-direction=bidirectional -misched=shuffle -enable-aa-sched-mi | FileCheck %s
; REQUIRES: asserts
; -misched=shuffle is NDEBUG only!
diff --git a/llvm/test/CodeGen/X86/misched-matrix.ll b/llvm/test/CodeGen/X86/misched-matrix.ll
index e909348eaa3883..f44bf39e76f6f6 100644
--- a/llvm/test/CodeGen/X86/misched-matrix.ll
+++ b/llvm/test/CodeGen/X86/misched-matrix.ll
@@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=generic -pre-RA-sched=source -enable-misched \
-; RUN: -misched-topdown -verify-machineinstrs \
+; RUN: -misched-prera-direction=topdown -verify-machineinstrs \
; RUN: | FileCheck %s -check-prefix=TOPDOWN
; RUN: llc < %s -mtriple=x86_64-- -mcpu=generic -pre-RA-sched=source -enable-misched \
; RUN: -misched=ilpmin -verify-machineinstrs \
diff --git a/llvm/test/CodeGen/X86/misched-new.ll b/llvm/test/CodeGen/X86/misched-new.ll
index 06ae8ff43d5af7..d7b3604ceefc4a 100644
--- a/llvm/test/CodeGen/X86/misched-new.ll
+++ b/llvm/test/CodeGen/X86/misched-new.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -x86-early-ifcvt -enable-misched \
-; RUN: -misched=shuffle -misched-bottomup -verify-machineinstrs \
+; RUN: -misched=shuffle -misched-prera-direction=bottomup -verify-machineinstrs \
; RUN: | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -x86-early-ifcvt -enable-misched \
-; RUN: -misched=shuffle -misched-topdown -verify-machineinstrs \
+; RUN: -misched=shuffle -misched-prera-direction=topdown -verify-machineinstrs \
; RUN: | FileCheck %s --check-prefix TOPDOWN
; REQUIRES: asserts
;
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