[llvm] [NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (PR #119622)

[Artem Belevich via llvm-commits]

================
@@ -3206,14 +3219,40 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
     EVT EltVT = ValVT.getVectorElementType();
     unsigned NumElts = ValVT.getVectorNumElements();
 
+    if (UpsizeElementTypes) {
+      switch (ValVT.getSimpleVT().SimpleTy) {
+      default:
+        llvm_unreachable("Unexpected Vector Type");
+      case MVT::v8i8: // <2 x i8x4>
+        NumElts = 2;
+        EltVT = MVT::v4i8;
+        break;
+      case MVT::v8f16: // <4 x f16x2>
+        NumElts = 4;
+        EltVT = MVT::v2f16;
+        break;
+      case MVT::v8bf16: // <4 x bf16x2>
+        NumElts = 4;
+        EltVT = MVT::v2bf16;
+        break;
+      case MVT::v8i16: // <4 x i16x2>
+        NumElts = 4;
+        EltVT = MVT::v2i16;
+        break;
+      case MVT::v16i8: // <4 x i8x4>
+        NumElts = 4;
+        EltVT = MVT::v4i8;
+        break;
+      }
----------------
Artem-B wrote:

This can be generalized to 
```
NPerWord = 32/EltVT.getSizeInBits(); // elements to pack in one word.
EltVT = getVectorVT(EltVT, NPerWord); // word-sized vector.
NumElts = NumElts/NPerWord; // number of word-sized vectors.
```

https://github.com/llvm/llvm-project/pull/119622