[llvm] [RISCV][VLOPT] Add support for mask-register logical instructions and set mask instructions (PR #112231)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 14:59:04 PST 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/112231
>From 43d963649dfc439d21b0c2219b974d9cbc7ac374 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 14 Oct 2024 09:22:26 -0700
Subject: [PATCH 01/10] [RISCV][VLOPT] Add support for mask-register logical
instructions and set mask instructions
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 38 ++++
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 223 +++++++++++++++++++
2 files changed, 261 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 0df4c451894bec..26b928b2ebdcf3 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -492,6 +492,28 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
return OperandInfo(EMUL, Log2EEW);
}
+ // 15. Vector Mask Instructions
+ // 15.1. Vector Mask-Register Logical Instructions
+ // 15.4. vmsbf.m set-before-first mask bit
+ // 15.6. vmsof.m set-only-first mask bit
+ // EEW=1 and EMUL=(EEW/SEW)*LMUL
+ // We handle the cases when operand is a v0 mask operand above the switch,
+ // but these instructions may use non-v0 mask operands and need to be handled
+ // specifically.
+ case RISCV::VMAND_MM:
+ case RISCV::VMNAND_MM:
+ case RISCV::VMANDN_MM:
+ case RISCV::VMXOR_MM:
+ case RISCV::VMOR_MM:
+ case RISCV::VMNOR_MM:
+ case RISCV::VMORN_MM:
+ case RISCV::VMXNOR_MM:
+ case RISCV::VMSBF_M:
+ case RISCV::VMSIF_M:
+ case RISCV::VMSOF_M: {
+ return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(0, MI), 0);
+ }
+
default:
return {};
}
@@ -632,6 +654,22 @@ static bool isSupportedInstr(const MachineInstr &MI) {
// Vector Crypto
case RISCV::VWSLL_VI:
+
+ // 15. Vector Mask Instructions
+ // 15.1. Vector Mask-Register Logical Instructions
+ // 15.4. vmsbf.m set-before-first mask bit
+ // 15.6. vmsof.m set-only-first mask bit
+ case RISCV::VMAND_MM:
+ case RISCV::VMNAND_MM:
+ case RISCV::VMANDN_MM:
+ case RISCV::VMXOR_MM:
+ case RISCV::VMOR_MM:
+ case RISCV::VMNOR_MM:
+ case RISCV::VMORN_MM:
+ case RISCV::VMXNOR_MM:
+ case RISCV::VMSBF_M:
+ case RISCV::VMSIF_M:
+ case RISCV::VMSOF_M:
return true;
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index e13482d23a26f4..6211dd6ff6527c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -2159,3 +2159,226 @@ define <vscale x 1 x i8> @vmerge_vvm(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x
%3 = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(<vscale x 1 x i8> undef, <vscale x 1 x i8> %2, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, iXLen %vl)
ret <vscale x 1 x i8> %3
}
+
+
+define <vscale x 1 x i1> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmand_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmand_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmand.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmnand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmnand_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmnand.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmnand_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmnand.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmandn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmandn_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmandn.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmandn_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmandn.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmxor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmxor_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmxor.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmxor_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmxor.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmor_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmor.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmor_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmor.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+
+define <vscale x 1 x i1> @vmnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmnor_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmnor.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmnor_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmnor.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmorn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmorn_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmorn.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmorn_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmorn.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmxnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+; NOVLOPT-LABEL: vmxnor_mm:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmxnor.mm v8, v0, v8
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmxnor_mm:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmxnor.mm v8, v0, v8
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmsbf_m(<vscale x 1 x i1> %a, iXLen %vl) {
+; NOVLOPT-LABEL: vmsbf_m:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmsbf.m v8, v0
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmsbf_m:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmsbf.m v8, v0
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmsif_m(<vscale x 1 x i1> %a, iXLen %vl) {
+; NOVLOPT-LABEL: vmsbf_m:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmsbf.m v8, v0
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmsbf_m:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmsbf.m v8, v0
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
+define <vscale x 1 x i1> @vmsof_m(<vscale x 1 x i1> %a, iXLen %vl) {
+; NOVLOPT-LABEL: vmsbf_m:
+; NOVLOPT: # %bb.0:
+; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmsbf.m v8, v0
+; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: ret
+;
+; VLOPT-LABEL: vmsbf_m:
+; VLOPT: # %bb.0:
+; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; VLOPT-NEXT: vmsbf.m v8, v0
+; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: ret
+ %1 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
+ %2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
+ ret <vscale x 1 x i1> %2
+}
+
>From 6bfc65f1676d22aaddd849b24cdef02fb54f8fdb Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 15 Oct 2024 07:13:37 -0700
Subject: [PATCH 02/10] fixup! add 15.5 and remove chapter numbers
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 26b928b2ebdcf3..a11e9e108360c1 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -492,10 +492,11 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
return OperandInfo(EMUL, Log2EEW);
}
- // 15. Vector Mask Instructions
- // 15.1. Vector Mask-Register Logical Instructions
- // 15.4. vmsbf.m set-before-first mask bit
- // 15.6. vmsof.m set-only-first mask bit
+ // Vector Mask Instructions
+ // Vector Mask-Register Logical Instructions
+ // vmsbf.m set-before-first mask bit
+ // vmsif.m set-including-first mask bit
+ // vmsof.m set-only-first mask bit
// EEW=1 and EMUL=(EEW/SEW)*LMUL
// We handle the cases when operand is a v0 mask operand above the switch,
// but these instructions may use non-v0 mask operands and need to be handled
@@ -655,10 +656,11 @@ static bool isSupportedInstr(const MachineInstr &MI) {
// Vector Crypto
case RISCV::VWSLL_VI:
- // 15. Vector Mask Instructions
- // 15.1. Vector Mask-Register Logical Instructions
- // 15.4. vmsbf.m set-before-first mask bit
- // 15.6. vmsof.m set-only-first mask bit
+ // Vector Mask Instructions
+ // Vector Mask-Register Logical Instructions
+ // vmsbf.m set-before-first mask bit
+ // vmsif.m set-including-first mask bit
+ // vmsof.m set-only-first mask bit
case RISCV::VMAND_MM:
case RISCV::VMNAND_MM:
case RISCV::VMANDN_MM:
>From 19adeca388c74dc0a3f1b8056f6bfd2e82bf8776 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 15 Oct 2024 07:14:32 -0700
Subject: [PATCH 03/10] fixup! update test checks
---
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index 6211dd6ff6527c..a7a9b5d1054061 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -2343,18 +2343,18 @@ define <vscale x 1 x i1> @vmsbf_m(<vscale x 1 x i1> %a, iXLen %vl) {
}
define <vscale x 1 x i1> @vmsif_m(<vscale x 1 x i1> %a, iXLen %vl) {
-; NOVLOPT-LABEL: vmsbf_m:
+; NOVLOPT-LABEL: vmsif_m:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmsbf.m v8, v0
+; NOVLOPT-NEXT: vmsif.m v8, v0
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
; NOVLOPT-NEXT: ret
;
-; VLOPT-LABEL: vmsbf_m:
+; VLOPT-LABEL: vmsif_m:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLOPT-NEXT: vmsbf.m v8, v0
+; VLOPT-NEXT: vmsif.m v8, v0
; VLOPT-NEXT: vmand.mm v0, v0, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
@@ -2363,18 +2363,18 @@ define <vscale x 1 x i1> @vmsif_m(<vscale x 1 x i1> %a, iXLen %vl) {
}
define <vscale x 1 x i1> @vmsof_m(<vscale x 1 x i1> %a, iXLen %vl) {
-; NOVLOPT-LABEL: vmsbf_m:
+; NOVLOPT-LABEL: vmsof_m:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmsbf.m v8, v0
+; NOVLOPT-NEXT: vmsof.m v8, v0
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
; NOVLOPT-NEXT: ret
;
-; VLOPT-LABEL: vmsbf_m:
+; VLOPT-LABEL: vmsof_m:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLOPT-NEXT: vmsbf.m v8, v0
+; VLOPT-NEXT: vmsof.m v8, v0
; VLOPT-NEXT: vmand.mm v0, v0, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
>From a1e709de247d246882ed2e2e4481beaffc5f3911 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 15 Oct 2024 07:23:43 -0700
Subject: [PATCH 04/10] fixup! test when last instruction consumes as mask
operand
---
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 140 ++++++++++++++-----
1 file changed, 105 insertions(+), 35 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index a7a9b5d1054061..a21e3df85193fb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -2160,14 +2160,16 @@ define <vscale x 1 x i8> @vmerge_vvm(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x
ret <vscale x 1 x i8> %3
}
-
-define <vscale x 1 x i1> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmand_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmand_mm:
@@ -2175,19 +2177,26 @@ define <vscale x 1 x i1> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmand.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmnand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmnand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmnand_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmnand.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmnand_mm:
@@ -2195,19 +2204,26 @@ define <vscale x 1 x i1> @vmnand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmnand.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmandn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmandn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmandn_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmandn.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmandn_mm:
@@ -2215,19 +2231,26 @@ define <vscale x 1 x i1> @vmandn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmandn.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmxor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmxor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmxor_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmxor.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmxor_mm:
@@ -2235,19 +2258,26 @@ define <vscale x 1 x i1> @vmxor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmxor.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmor_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmor.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmor_mm:
@@ -2255,20 +2285,27 @@ define <vscale x 1 x i1> @vmor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iX
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmor.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmnor_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmnor.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmnor_mm:
@@ -2276,19 +2313,26 @@ define <vscale x 1 x i1> @vmnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmnor.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmorn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmorn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmorn_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmorn.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmorn_mm:
@@ -2296,19 +2340,26 @@ define <vscale x 1 x i1> @vmorn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmorn.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmxnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen %vl) {
+define <vscale x 1 x i32> @vmxnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmxnor_mm:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmxnor.mm v8, v0, v8
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmv1r.v v8, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmxnor_mm:
@@ -2316,69 +2367,88 @@ define <vscale x 1 x i1> @vmxnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLOPT-NEXT: vmxnor.mm v8, v0, v8
; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmv1r.v v8, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v9, v9, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmsbf_m(<vscale x 1 x i1> %a, iXLen %vl) {
+define <vscale x 1 x i32> @vmsbf_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmsbf_m:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmsbf.m v8, v0
+; NOVLOPT-NEXT: vmsbf.m v9, v0
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmand.mm v0, v0, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v8, v8, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmsbf_m:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLOPT-NEXT: vmsbf.m v8, v0
-; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmsbf.m v9, v0
+; VLOPT-NEXT: vmand.mm v0, v0, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v8, v8, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmsif_m(<vscale x 1 x i1> %a, iXLen %vl) {
+define <vscale x 1 x i32> @vmsif_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmsif_m:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmsif.m v8, v0
+; NOVLOPT-NEXT: vmsif.m v9, v0
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmand.mm v0, v0, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v8, v8, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmsif_m:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLOPT-NEXT: vmsif.m v8, v0
-; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmsif.m v9, v0
+; VLOPT-NEXT: vmand.mm v0, v0, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v8, v8, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
-define <vscale x 1 x i1> @vmsof_m(<vscale x 1 x i1> %a, iXLen %vl) {
+define <vscale x 1 x i32> @vmsof_m(<vscale x 1 x i1> %a, <vscale x 1 x i32> %c, iXLen %vl) {
; NOVLOPT-LABEL: vmsof_m:
; NOVLOPT: # %bb.0:
; NOVLOPT-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmsof.m v8, v0
+; NOVLOPT-NEXT: vmsof.m v9, v0
; NOVLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLOPT-NEXT: vmand.mm v0, v0, v8
+; NOVLOPT-NEXT: vmand.mm v0, v0, v9
+; NOVLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; NOVLOPT-NEXT: vadd.vv v8, v8, v8, v0.t
; NOVLOPT-NEXT: ret
;
; VLOPT-LABEL: vmsof_m:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLOPT-NEXT: vmsof.m v8, v0
-; VLOPT-NEXT: vmand.mm v0, v0, v8
+; VLOPT-NEXT: vmsof.m v9, v0
+; VLOPT-NEXT: vmand.mm v0, v0, v9
+; VLOPT-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
+; VLOPT-NEXT: vadd.vv v8, v8, v8, v0.t
; VLOPT-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(<vscale x 1 x i1> %a, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
- ret <vscale x 1 x i1> %2
+ %3 = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i32> %c, <vscale x 1 x i1> %2, iXLen %vl, iXLen 0)
+ ret <vscale x 1 x i32> %3
}
>From 40cfd39c1ff11727c28accfe1cdf3ad1637da008 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 11 Dec 2024 11:03:48 -0800
Subject: [PATCH 05/10] fixup! update tests
---
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 35035274ccd5e0..2a368e935a23dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -560,4 +560,34 @@ body: |
%z:gpr = ADDI $x0, 2
PseudoVSSE8_V_MF2 %x, %y, %z, 1, 3 /* e8 */
...
+---
+name: vmop_mm
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm
+ ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 3 /* e8 */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
+ %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
+ %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
+...
+---
+name: vmop_mm_incompatible_eew
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm_incompatible_eew
+ ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 4 /* e16 */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
+ %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 4 /* e16 */
+ %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
+...
+---
+name: vmop_mm_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm_incompatible_emul
+ ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 3 /* e8 */
+ %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
+ %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 3 /* e8 */
+...
>From 2999459e07f202becf2274831d18efc2e2a42096 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 11 Dec 2024 11:45:48 -0800
Subject: [PATCH 06/10] fixup! respond to review
---
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 34 ++++++++++++-------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 2a368e935a23dd..09f34c2203842a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -565,29 +565,39 @@ name: vmop_mm
body: |
bb.0:
; CHECK-LABEL: name: vmop_mm
- ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 3 /* e8 */
- ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
- %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
- %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
+ ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 0 /* e8 */
+ %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
+ %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 0
+...
+---
+name: vmop_mm_mask
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm_mask
+ ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 3 /* e8 */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
+ %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: vmop_mm_incompatible_eew
body: |
bb.0:
; CHECK-LABEL: name: vmop_mm_incompatible_eew
- ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 4 /* e16 */
- ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
- %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 4 /* e16 */
- %y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 3 /* e8 */
+ ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
+ ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
+ %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: vmop_mm_incompatible_emul
body: |
bb.0:
; CHECK-LABEL: name: vmop_mm_incompatible_emul
- ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
- ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 3 /* e8 */
- %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
- %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 3 /* e8 */
+ ; CHECK: %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
+ ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 0 /* e8 */
+ %x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
+ %y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 0
...
>From 7db13a912d0fc0076829965c2e86fd0107755d4f Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 11 Dec 2024 13:01:08 -0800
Subject: [PATCH 07/10] fixup! fix test case
---
llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 09f34c2203842a..34a2b94a574ebf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -575,9 +575,9 @@ name: vmop_mm_mask
body: |
bb.0:
; CHECK-LABEL: name: vmop_mm_mask
- ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 3 /* e8 */
+ ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
- %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 3 /* e8 */
+ %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
%y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
---
>From 46c21bc921c480c8971d23eb27735e9f65483531 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 11 Dec 2024 13:05:25 -0800
Subject: [PATCH 08/10] fixup! fix bug in getEMULEqualsEEWDivSEWTimesLMUL
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 6 ++++++
llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 2 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index a11e9e108360c1..1d5684d6038ea9 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -159,6 +159,12 @@ getEMULEqualsEEWDivSEWTimesLMUL(unsigned Log2EEW, const MachineInstr &MI) {
auto [MILMUL, MILMULIsFractional] = RISCVVType::decodeVLMUL(MIVLMUL);
unsigned MILog2SEW =
MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
+
+ // Mask instructions will have 0 as the SEW operand. But the LMUL of these
+ // instructions is calculated is as if the SEW operand was 3 (e8).
+ if (MILog2SEW == 0)
+ MILog2SEW = 3;
+
unsigned MISEW = 1 << MILog2SEW;
unsigned EEW = 1 << Log2EEW;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 34a2b94a574ebf..69cafcf604fb07 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -575,7 +575,7 @@ name: vmop_mm_mask
body: |
bb.0:
; CHECK-LABEL: name: vmop_mm_mask
- ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
+ ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
%y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
>From db6497df888770a1c02286f1f415ab091a0ca230 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 11 Dec 2024 13:11:16 -0800
Subject: [PATCH 09/10] fixup! add test for incompatible emul with mask instr
---
.../test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 30 ++++++++++++-------
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 69cafcf604fb07..a813cd621c35c7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -571,16 +571,6 @@ body: |
%y:vr = PseudoVMAND_MM_M1 $noreg, %x, 1, 0
...
---
-name: vmop_mm_mask
-body: |
- bb.0:
- ; CHECK-LABEL: name: vmop_mm_mask
- ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
- ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
- %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
- %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
-...
----
name: vmop_mm_incompatible_eew
body: |
bb.0:
@@ -600,4 +590,24 @@ body: |
%x:vr = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
%y:vr = PseudoVMAND_MM_MF2 $noreg, %x, 1, 0
...
+---
+name: vmop_mm_mask
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm_mask
+ ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
+ %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
+...
+---
+name: vmop_mm_mask_incompatible_emul
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm_mask_incompatible_emul
+ ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0 /* e8 */
+ ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
+ %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
+ %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
+...
>From 18a188c4f9015cc4144a1610c874be82a8e7edbc Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 11 Dec 2024 14:58:36 -0800
Subject: [PATCH 10/10] fixup! add requested test
---
llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index a813cd621c35c7..f7f97408b2ede2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -601,6 +601,16 @@ body: |
%y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
---
+name: vmop_mm_mask_larger_emul_user
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: vmop_mm_mask_larger_emul_user
+ ; CHECK: %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, 1, 0 /* e8 */
+ ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
+ %x:vmv0 = PseudoVMAND_MM_M1 $noreg, $noreg, -1, 0
+ %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0
+...
+---
name: vmop_mm_mask_incompatible_emul
body: |
bb.0:
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