[llvm] [GlobalISel][AArch64] Legalize G_FABS and G_FNEG for SVE (PR #114784)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 12:54:15 PST 2024
Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>,
Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/114784 at github.com>
================
@@ -0,0 +1,36 @@
+//===-- AArch64GlobalISelPatterns.td - GlobalISel patterns -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Selection and combine patterns for GlobalISel.
+//
+//===----------------------------------------------------------------------===//
+
+
+//unpredicate patterns
+
+
+
+// fneg
+def : Pat<(nxv2f64 (fneg nxv2f64:$src)),
+ (FNEG_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$src)>;
----------------
topperc wrote:
I grabbed `fabsnxv8half` from your test and ran it through SelectionDAG with -stop-after=finalize-isel. This is the resulting MIR.
```
%0:zpr = COPY $z0
%1:ppr_3b = PTRUE_H 31, implicit $vg
%3:zpr = IMPLICIT_DEF
%2:zpr = FABS_ZPmZ_H_UNDEF killed %3, killed %1, %0
$z0 = COPY %2
RET_ReallyLR implicit $z0
```
I would expect GISel to produce the same MIR.
https://github.com/llvm/llvm-project/pull/114784
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