[llvm] [AArch64] Improve code generation of bool vector reduce operations (PR #115713)

[David Green via llvm-commits]

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In-Reply-To: <llvm.org/llvm/llvm-project/pull/115713 at github.com>


davemgreen wrote:

I see, with fast math.. I'll revert this for now if that is OK.

I think it might be conflicting with DAZ/FTZ that gets set by fast-math. The start-up object sets the flags in FPCR.

https://github.com/llvm/llvm-project/pull/115713