[llvm] [RISCV][VLOPT] Add support for mask-register logical instructions and set mask instructions (PR #112231)

[Craig Topper via llvm-commits]

topperc wrote:

There are deeper problems. The Log2SEW read from the SEWOp in getEMULEqualsEEWDivSEWTimesLMUL, getOperandInfo, etc. needs to be changed from 0 to 3 to make the SEW/LMUL ratio correct.

https://github.com/llvm/llvm-project/pull/112231