[llvm] e7c626c - [RISCV][VLOPT] Fix test case as a result of changes in #119602

Michael Maitland via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 11 11:10:13 PST 2024


Author: Michael Maitland
Date: 2024-12-11T11:08:55-08:00
New Revision: e7c626cdd154b3c7b36ba0243cf75ff1cec76952

URL: https://github.com/llvm/llvm-project/commit/e7c626cdd154b3c7b36ba0243cf75ff1cec76952
DIFF: https://github.com/llvm/llvm-project/commit/e7c626cdd154b3c7b36ba0243cf75ff1cec76952.diff

LOG: [RISCV][VLOPT] Fix test case as a result of changes in #119602

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
index 81b4742405c868..35035274ccd5e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
@@ -392,13 +392,12 @@ body: |
     %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
     %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0
 ...
-# TODO: VNSRL_WV isn't yet a supported instruction for VL reduction
 ---
 name: vnop_wv_vd
 body: |
   bb.0:
     ; CHECK-LABEL: name: vnop_wv_vd
-    ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
+    ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
     ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
     %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
     %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0


        


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