[llvm] [TableGen] Replace WantRoot/WantParent SDNode properties with flags (PR #119599)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 09:47:32 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Sergei Barannikov (s-barannikov)
<details>
<summary>Changes</summary>
These properties are only valid on ComplexPatterns. Having them as flags is more convenient because one can now use "let = ... in" syntax to set these flags on several patterns at a time. This is also less error-prone as it makes it impossible to specify these properties on records derived from SDPatternOperator.
---
Patch is 23.26 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119599.diff
19 Files Affected:
- (modified) llvm/include/llvm/CodeGen/SDNodeProperties.td (-2)
- (modified) llvm/include/llvm/Target/TargetSelectionDAG.td (+8)
- (modified) llvm/lib/Target/AArch64/SMEInstrFormats.td (+2-1)
- (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+4-2)
- (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+4-2)
- (modified) llvm/lib/Target/AMDGPU/FLATInstructions.td (+8-6)
- (modified) llvm/lib/Target/ARM/ARMInstrInfo.td (+18-19)
- (modified) llvm/lib/Target/ARM/ARMInstrMVE.td (+4-3)
- (modified) llvm/lib/Target/ARM/ARMInstrThumb.td (+2-2)
- (modified) llvm/lib/Target/ARM/ARMInstrThumb2.td (+2-2)
- (modified) llvm/lib/Target/AVR/AVRInstrInfo.td (+2-1)
- (modified) llvm/lib/Target/M68k/M68kInstrInfo.td (+15-21)
- (modified) llvm/lib/Target/NVPTX/NVPTXInstrInfo.td (+4-4)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.td (+9-7)
- (modified) llvm/lib/Target/X86/X86InstrFragments.td (+4-2)
- (modified) llvm/utils/TableGen/Basic/SDNodeProperties.h (-2)
- (modified) llvm/utils/TableGen/Common/CodeGenTarget.cpp (+3-4)
- (modified) llvm/utils/TableGen/Common/CodeGenTarget.h (+4)
- (modified) llvm/utils/TableGen/DAGISelMatcherEmitter.cpp (+2-2)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/SDNodeProperties.td b/llvm/include/llvm/CodeGen/SDNodeProperties.td
index 3cb304f47f4b9d..d32904283a11a9 100644
--- a/llvm/include/llvm/CodeGen/SDNodeProperties.td
+++ b/llvm/include/llvm/CodeGen/SDNodeProperties.td
@@ -29,5 +29,3 @@ def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
-def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
-def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 7bb6c3156c43e0..2c58eedce1de0b 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -2086,4 +2086,12 @@ class ComplexPattern<ValueType ty, int numops, string fn,
list<SDNode> RootNodes = roots;
list<SDNodeProperty> Properties = props;
int Complexity = complexity;
+
+ // Set this to true if SelectFunc wants an additional argument
+ // that is the root of the matched pattern.
+ bit WantsRoot = false;
+
+ // Set this to true if SelectFunc wants an additional argument
+ // that is the parent of the matched node.
+ bit WantsParent = false;
}
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
index 27995ca5bb701f..a67093b1a58c3d 100644
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -32,7 +32,8 @@ def tileslicerange2s4 : ComplexPattern<i32, 2, "SelectSMETileSlice<12, 4>", []>;
def tileslicerange1s4 : ComplexPattern<i32, 2, "SelectSMETileSlice<4, 4>", []>;
def tileslicerange0s4 : ComplexPattern<i32, 2, "SelectSMETileSlice<0, 4>", []>;
-def am_sme_indexed_b4 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<0,15>", [], [SDNPWantRoot]>;
+let WantsRoot = true in
+def am_sme_indexed_b4 : ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<0, 15>">;
def SDTZALoadStore : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>]>;
def AArch64SMELdr : SDNode<"AArch64ISD::SME_ZA_LDR", SDTZALoadStore,
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 9ae66518dfb4ed..34792f86521e50 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -9567,8 +9567,10 @@ multiclass sve_int_perm_bin_perm_128_zz<bits<2> opc, bit P, string asm, SDPatter
}
/// Addressing modes
-def am_sve_indexed_s4 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-8,7>", [], [SDNPWantRoot]>;
-def am_sve_indexed_s6 :ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-32,31>", [], [SDNPWantRoot]>;
+let WantsRoot = true in {
+ def am_sve_indexed_s4 : ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-8, 7>">;
+ def am_sve_indexed_s6 : ComplexPattern<iPTR, 2, "SelectAddrModeIndexedSVE<-32, 31>">;
+}
def am_sve_regreg_lsl0 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<0>", []>;
def am_sve_regreg_lsl1 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<1>", []>;
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index a288c58def5cbd..a351f451584f9d 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -9,8 +9,10 @@
def MUBUFAddr64 : ComplexPattern<iPTR, 4, "SelectMUBUFAddr64">;
def MUBUFOffset : ComplexPattern<iPTR, 3, "SelectMUBUFOffset">;
-def MUBUFScratchOffen : ComplexPattern<iPTR, 4, "SelectMUBUFScratchOffen", [], [SDNPWantParent]>;
-def MUBUFScratchOffset : ComplexPattern<iPTR, 3, "SelectMUBUFScratchOffset", [], [SDNPWantParent], 20>;
+let WantsParent = true in {
+ def MUBUFScratchOffen : ComplexPattern<iPTR, 4, "SelectMUBUFScratchOffen">;
+ def MUBUFScratchOffset : ComplexPattern<iPTR, 3, "SelectMUBUFScratchOffset", [], [], 20>;
+}
def BUFSOffset : ComplexPattern<iPTR, 1, "SelectBUFSOffset">;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 9244b4a6649861..8fa708b74dde32 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -6,13 +6,15 @@
//
//===----------------------------------------------------------------------===//
-def FlatOffset : ComplexPattern<iPTR, 2, "SelectFlatOffset", [], [SDNPWantRoot], -10>;
-def GlobalOffset : ComplexPattern<iPTR, 2, "SelectGlobalOffset", [], [SDNPWantRoot], -10>;
-def ScratchOffset : ComplexPattern<iPTR, 2, "SelectScratchOffset", [], [SDNPWantRoot], -10>;
+let WantsRoot = true in {
+ def FlatOffset : ComplexPattern<iPTR, 2, "SelectFlatOffset", [], [], -10>;
+ def GlobalOffset : ComplexPattern<iPTR, 2, "SelectGlobalOffset", [], [], -10>;
+ def ScratchOffset : ComplexPattern<iPTR, 2, "SelectScratchOffset", [], [], -10>;
-def GlobalSAddr : ComplexPattern<iPTR, 3, "SelectGlobalSAddr", [], [SDNPWantRoot], -10>;
-def ScratchSAddr : ComplexPattern<iPTR, 2, "SelectScratchSAddr", [], [SDNPWantRoot], -10>;
-def ScratchSVAddr : ComplexPattern<iPTR, 3, "SelectScratchSVAddr", [], [SDNPWantRoot], -10>;
+ def GlobalSAddr : ComplexPattern<iPTR, 3, "SelectGlobalSAddr", [], [], -10>;
+ def ScratchSAddr : ComplexPattern<iPTR, 2, "SelectScratchSAddr", [], [], -10>;
+ def ScratchSVAddr : ComplexPattern<iPTR, 3, "SelectScratchSVAddr", [], [], -10>;
+}
//===----------------------------------------------------------------------===//
// FLAT classes
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 718cb964ab7c3b..1cb6589184b603 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -1225,25 +1225,25 @@ def PostIdxRegShiftedAsmOperand : AsmOperandClass {
let ParserMethod = "parsePostIdxReg";
}
def am2offset_reg : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
- [], [SDNPWantRoot]> {
+ ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg"> {
let EncoderMethod = "getAddrMode2OffsetOpValue";
let PrintMethod = "printAddrMode2OffsetOperand";
// When using this for assembly, it's always as a post-index offset.
let ParserMatchClass = PostIdxRegShiftedAsmOperand;
let MIOperandInfo = (ops GPRnopc, i32imm);
+ let WantsRoot = true;
}
// FIXME: am2offset_imm should only need the immediate, not the GPR. Having
// the GPR is purely vestigal at this point.
def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
def am2offset_imm : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
- [], [SDNPWantRoot]> {
+ ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm"> {
let EncoderMethod = "getAddrMode2OffsetOpValue";
let PrintMethod = "printAddrMode2OffsetOperand";
let ParserMatchClass = AM2OffsetImmAsmOperand;
let MIOperandInfo = (ops GPRnopc, i32imm);
+ let WantsRoot = true;
}
@@ -1275,13 +1275,12 @@ def AM3OffsetAsmOperand : AsmOperandClass {
let Name = "AM3Offset";
let ParserMethod = "parseAM3Offset";
}
-def am3offset : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode3Offset",
- [], [SDNPWantRoot]> {
+def am3offset : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode3Offset"> {
let EncoderMethod = "getAddrMode3OffsetOpValue";
let PrintMethod = "printAddrMode3OffsetOperand";
let ParserMatchClass = AM3OffsetAsmOperand;
let MIOperandInfo = (ops GPR, i32imm);
+ let WantsRoot = true;
}
// ldstm_mode := {ia, ib, da, db}
@@ -1328,40 +1327,39 @@ def addrmode5fp16 : AddrMode5FP16 {
// addrmode6 := reg with optional alignment
//
def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
-def addrmode6 : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
+def addrmode6 : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
let EncoderMethod = "getAddrMode6AddressOpValue";
let DecoderMethod = "DecodeAddrMode6Operand";
let ParserMatchClass = AddrMode6AsmOperand;
+ let WantsParent = true;
}
-def am6offset : MemOperand,
- ComplexPattern<i32, 1, "SelectAddrMode6Offset",
- [], [SDNPWantRoot]> {
+def am6offset : MemOperand, ComplexPattern<i32, 1, "SelectAddrMode6Offset"> {
let PrintMethod = "printAddrMode6OffsetOperand";
let MIOperandInfo = (ops GPR);
let EncoderMethod = "getAddrMode6OffsetOpValue";
let DecoderMethod = "DecodeGPRRegisterClass";
+ let WantsRoot = true;
}
// Special version of addrmode6 to handle alignment encoding for VST1/VLD1
// (single element from one lane) for size 32.
-def addrmode6oneL32 : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
+def addrmode6oneL32 : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
+ let WantsParent = true;
}
// Base class for addrmode6 with specific alignment restrictions.
-class AddrMode6Align : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
+class AddrMode6Align : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
let EncoderMethod = "getAddrMode6AddressOpValue";
let DecoderMethod = "DecodeAddrMode6Operand";
+ let WantsParent = true;
}
// Special version of addrmode6 to handle no allowed alignment encoding for
@@ -1432,22 +1430,23 @@ def addrmode6align64or128or256 : AddrMode6Align {
// Special version of addrmode6 to handle alignment encoding for VLD-dup
// instructions, specifically VLD4-dup.
-def addrmode6dup : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
+def addrmode6dup : MemOperand, ComplexPattern<i32, 2, "SelectAddrMode6"> {
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
let EncoderMethod = "getAddrMode6DupAddressOpValue";
// FIXME: This is close, but not quite right. The alignment specifier is
// different.
let ParserMatchClass = AddrMode6AsmOperand;
+ let WantsParent = true;
}
// Base class for addrmode6dup with specific alignment restrictions.
class AddrMode6DupAlign : MemOperand,
- ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
+ ComplexPattern<i32, 2, "SelectAddrMode6"> {
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
let EncoderMethod = "getAddrMode6DupAddressOpValue";
+ let WantsParent = true;
}
// Special version of addrmode6 to handle no allowed alignment encoding for
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index bdd0d739a05684..6dd8a374a92af4 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -184,15 +184,16 @@ def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;
def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;
def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;
-class t2am_imm7_offset<int shift> : MemOperand,
- ComplexPattern<i32, 1, "SelectT2AddrModeImm7Offset<"#shift#">",
- [], [SDNPWantRoot]> {
+class t2am_imm7_offset<int shift>
+ : MemOperand,
+ ComplexPattern<i32, 1, "SelectT2AddrModeImm7Offset<"#shift#">"> {
// They are printed the same way as the imm8 version
let PrintMethod = "printT2AddrModeImm8OffsetOperand";
let ParserMatchClass =
!cast<AsmOperandClass>("t2am_imm7shift"#shift#"OffsetAsmOperand");
let EncoderMethod = "getT2ScaledImmOpValue<7,"#shift#">";
let DecoderMethod = "DecodeT2Imm7<"#shift#">";
+ let WantsRoot = true;
}
// Operands for gather/scatter loads of the form [Rbase, Qoffsets]
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index cc7fc743fe4f92..b69bc601a0cdce 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -287,8 +287,8 @@ def t_addrmode_sp : MemOperand,
// Inspects parent to determine whether an or instruction can be implemented as
// an add (i.e. whether we know overflow won't occur in the add).
-def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr", [],
- [SDNPWantParent]>;
+let WantsParent = true in
+def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr">;
// Pattern to exclude immediates from matching
def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 99617e53d657a9..9ff056f9c06a16 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -267,11 +267,11 @@ def t2addrmode_imm8_pre : T2AddrMode_Imm8 {
}
def t2am_imm8_offset : MemOperand,
- ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
- [], [SDNPWantRoot]> {
+ ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset"> {
let PrintMethod = "printT2AddrModeImm8OffsetOperand";
let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
let DecoderMethod = "DecodeT2Imm8";
+ let WantsRoot = true;
}
// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 61c17090e3fbe8..5474a42e58848d 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -232,7 +232,8 @@ def imm_port6 : Operand<i8> {
}
// Addressing mode pattern reg+imm6
-def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>;
+let WantsRoot = true in
+def addr : ComplexPattern<iPTR, 2, "SelectAddr">;
//===----------------------------------------------------------------------===//
// AVR predicates for subtarget features
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 3a9e4fe77f1ccf..dca774e94b9b5a 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -466,34 +466,28 @@ def MxCONDle : PatLeaf<(i8 15)>; // Less or Equal
// NOTE Though this CP is not strictly necessarily it will simplify instruciton
// definitions
-def MxCP_ARI : ComplexPattern<iPTR, 1, "SelectARI",
- [], [SDNPWantParent]>;
+let WantsParent = true in {
+ def MxCP_ARI : ComplexPattern<iPTR, 1, "SelectARI">;
-def MxCP_ARIPI : ComplexPattern<iPTR, 1, "SelectARIPI",
- [], [SDNPWantParent]>;
+ def MxCP_ARIPI : ComplexPattern<iPTR, 1, "SelectARIPI">;
-def MxCP_ARIPD : ComplexPattern<iPTR, 1, "SelectARIPD",
- [], [SDNPWantParent]>;
+ def MxCP_ARIPD : ComplexPattern<iPTR, 1, "SelectARIPD">;
-def MxCP_ARID : ComplexPattern<iPTR, 2, "SelectARID",
- [add, sub, mul, or, shl, frameindex],
- [SDNPWantParent]>;
+ def MxCP_ARID : ComplexPattern<iPTR, 2, "SelectARID",
+ [add, sub, mul, or, shl, frameindex]>;
-def MxCP_ARII : ComplexPattern<iPTR, 3, "SelectARII",
- [add, sub, mul, or, shl, frameindex],
- [SDNPWantParent]>;
+ def MxCP_ARII : ComplexPattern<iPTR, 3, "SelectARII",
+ [add, sub, mul, or, shl, frameindex]>;
-def MxCP_AL : ComplexPattern<iPTR, 1, "SelectAL",
- [add, sub, mul, or, shl],
- [SDNPWantParent]>;
+ def MxCP_AL : ComplexPattern<iPTR, 1, "SelectAL",
+ [add, sub, mul, or, shl]>;
-def MxCP_PCD : ComplexPattern<iPTR, 1, "SelectPCD",
- [add, sub, mul, or, shl],
- [SDNPWantParent]>;
-
-def MxCP_PCI : ComplexPattern<iPTR, 2, "SelectPCI",
- [add, sub, mul, or, shl], [SDNPWantParent]>;
+ def MxCP_PCD : ComplexPattern<iPTR, 1, "SelectPCD",
+ [add, sub, mul, or, shl]>;
+ def MxCP_PCI : ComplexPattern<iPTR, 2, "SelectPCI",
+ [add, sub, mul, or, shl]>;
+}
//===----------------------------------------------------------------------===//
// Pattern Fragments
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 66684dbff6b335..a7836ccc45f476 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -1907,10 +1907,10 @@ defm SET_f64 : SET<"f64", Float64Regs, f64imm>;
// Data Movement (Load / Store, Move)
//-----------------------------------
-def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex],
- [SDNPWantRoot]>;
-def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri64", [frameindex],
- [SDNPWantRoot]>;
+let WantsRoot = true in {
+ def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
+ def ADDRri64 : ComplexPattern<i64, 2, "SelectADDRri64", [frameindex]>;
+}
def ADDRvar : ComplexPattern<iPTR, 1, "SelectDirectAddr", [], []>;
def MEMri : Operand<i32> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 0d3c07aa87ff25..be90a5c562c570 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -686,13 +686,15 @@ def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
// Load and Store Instruction Selection addressing modes.
-def DForm : ComplexPattern<iPTR, 2, "SelectDForm", [], [SDNPWantParent]>;
-def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm", [], [SDNPWantParent]>;
-def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm", [], [SDNPWantParent]>;
-def XForm : ComplexPattern<iPTR, 2, "SelectXForm", [], [SDNPWantParent]>;
-def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm", [], [SDNPWantParent]>;
-def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm", [], [SDNPWantParent]>;
-def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm", [], [SDNPWantParent]>;
+let WantsParent = true in {
+ def DForm : ComplexPattern<iPTR, 2, "SelectDForm">;
+ def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm">;
+ def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm">;
+ def XForm : ComplexPattern<iPTR, 2, "SelectXForm">;
+ def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm">;
+ def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm">;
+ def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm">;
+}
//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td
index ba9779cdc335d6..ea7af893ce103f 100644
--- a/llvm/lib/Target/X86/X86InstrFragments.td
+++ b/llvm/lib/Target/X86/X86InstrFragments.td
@@ -352,7 +352,8 @@ def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd,
SDNPMemOperand]>;
// Define X86-specific addressing mode.
-def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>;
+let WantsParent = true in
+def addr : ComplexPattern<iPTR, 5, "selectAddr">;
def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr",
[add, sub, mul, X86mul_imm, shl, or, xor, frameindex],
[]>;
@@ -378,7 +379,8 @@ def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr",
[tglobaltlsaddr], []>;
-def vectoraddr : ComplexPattern<iPTR, 5, "sele...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/119599
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