[llvm] [M68k] add 32 bit branch instrs and relaxations (PR #117371)

[Min-Yih Hsu via llvm-commits]

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@@ -166,26 +225,37 @@ bool M68kAsmBackend::mayNeedRelaxation(const MCInst &Inst,
 }
 
 bool M68kAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
-                                          uint64_t Value) const {
-  // TODO Newer CPU can use 32 bit offsets, so check for this when ready
-  if (!isInt<16>(Value)) {
+                                          uint64_t UnsignedValue) const {
+  int64_t Value = static_cast<int64_t>(UnsignedValue);
+
+  if (!isInt<32>(Value) || (!Allows32BitBranch && !isInt<16>(Value))) {
     llvm_unreachable("Cannot relax the instruction, value does not fit");
   }
-  // Relax if the value is too big for a (signed) i8. This means that byte-wide
-  // instructions have to matched by default
-  //
+
+  // Relax if the value is too big for a (signed) i8
+  // (or signed i16 if 32 bit branches can be used). This means
+  // that byte-wide instructions have to matched by default
+  unsigned KindLog2Size = getFixupKindLog2Size(Fixup.getKind());
+  bool FixupFieldTooSmall = false;
+  if (!isInt<8>(Value) && KindLog2Size == 0) {
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mshockwave wrote:

single statement should not have curly braces

https://github.com/llvm/llvm-project/pull/117371