[llvm] [AArch64] Handle ANY_EXTEND in BuildShuffleExtendCombine (PR #118308)

[Nicholas Guy via llvm-commits]

================
@@ -18594,7 +18608,10 @@ static SDValue performBuildShuffleExtendCombine(SDValue BV, SelectionDAG &DAG) {
                                    : BV.getOperand(1).getOperand(0),
                                cast<ShuffleVectorSDNode>(BV)->getMask());
   }
-  return DAG.getNode(IsSExt ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, VT, NBV);
+  unsigned ExtOpc = !SeenZExtOrSExt ? ISD::ANY_EXTEND
+                    : IsSExt        ? ISD::SIGN_EXTEND
+                                    : ISD::ZERO_EXTEND;
----------------
NickGuy-Arm wrote:

Minor nitpick: I'm not keen on the readability of nested ternary operators like this. Can we add some brackets to make it clear
```suggestion
  unsigned ExtOpc = !SeenZExtOrSExt ? ISD::ANY_EXTEND
                    :(IsSExt        ? ISD::SIGN_EXTEND
                                    : ISD::ZERO_EXTEND);
```

https://github.com/llvm/llvm-project/pull/118308