[llvm] [RISCV][VLOPT] Add getOperandInfo for Vector Store Whole Register Instructions (PR #119570)

[Luke Lau via llvm-commits]

https://github.com/lukel97 commented:

Can we not get a different LMUL to typecheck with MIR if we use MF2/MF4/MF8? They should all use the same register class

https://github.com/llvm/llvm-project/pull/119570