[llvm] [RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (PR #119567)

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git-clang-format --diff 7ea1fe773225fe88fd3ceb0aa17152eec496d135 7a5b5482c3371125e57bc633647fef5774420896 --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 4490e1b4c0..eb3a06b1ac 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1041,20 +1041,19 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
             CurDAG->getTargetConstant(TrailingZeros + ShAmt, DL, VT));
         ReplaceNode(Node, SLLI);
         return;
-      }
-      else if (TrailingZeros == 0 && LeadingZeros > ShAmt &&
-          XLen - LeadingZeros > 11 && LeadingZeros != 32) {
+      } else if (TrailingZeros == 0 && LeadingZeros > ShAmt &&
+                 XLen - LeadingZeros > 11 && LeadingZeros != 32) {
         // Optimize (shl (and X, C2), C) -> (srli (slli X, C4), C4-C)
         // where C2 has C4 leading zeros and no trailing zeros.
         // This is profitable if the "and" was to be lowered to
         // (srli (slli X, C4), C4) and not (andi X, C2).
         // For "LeadingZeros == 32" we prefer Zba (slli.uw X, C).
         SDNode *SLLI = CurDAG->getMachineNode(
-          RISCV::SLLI, DL, VT, N0->getOperand(0),
-          CurDAG->getTargetConstant(LeadingZeros, DL, VT));
+            RISCV::SLLI, DL, VT, N0->getOperand(0),
+            CurDAG->getTargetConstant(LeadingZeros, DL, VT));
         SDNode *SRLI = CurDAG->getMachineNode(
-          RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
-          CurDAG->getTargetConstant(LeadingZeros - ShAmt, DL, VT));
+            RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
+            CurDAG->getTargetConstant(LeadingZeros - ShAmt, DL, VT));
         ReplaceNode(Node, SRLI);
         return;
       }

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https://github.com/llvm/llvm-project/pull/119567