[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -21834,15 +21824,23 @@ SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
   auto Acc = N->getOperand(0);
   auto Input = N->getOperand(1);
 
-  EVT AccVT = Acc.getValueType();
+  unsigned Opcode = N->getOpcode();
+  unsigned InputOpcode = Input.getOpcode();
+  if (ISD::isExtOpcode(InputOpcode)) {
+    Input = Input.getOperand(0);
+    if (InputOpcode == ISD::SIGN_EXTEND)
+      Opcode = ISD::PARTIAL_REDUCE_SADD;
+  }
+
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JamesChesterman wrote:

I've now made it so the DAG-combine function decides whether to keep the node opcode as `ISD::PARTIAL_REDUCE_UADD` or whether to convert it to `ISD::PARTIAL_REDUCE_SADD`. But, the DAG-combine function also includes the lowering for `usdot` IR patterns (due to the reasons described in the above comment). Also, the DAG-combine needed to include lowering for `(nx)v16i8` to `(nx)v4i64`, because otherwise the instruction would be attempted to be legalised. But, there is now a lowering function called by `LowerOperation` which covers the general cases for lowering to wide add / dot product instructions.

https://github.com/llvm/llvm-project/pull/117185