[llvm] [AArch64] Fixup destructive floating-point precision conversions (PR #118788)

[Momchil Velikov via llvm-commits]

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@@ -4268,17 +4269,16 @@ let Predicates = [HasSVE2p2orSME2p2] in {
   defm FCVT_ZPzZ : sve_fp_z2op_p_zd_b_0<"fcvt", "int_aarch64_sve_fcvt">;
 
   // SVE2p2 floating-point convert precision down (placing odd), zeroing predicate
-  defm FCVTNT_ZPzZ      : sve_fp_fcvtntz<"fcvtnt">;
-  def FCVTXNT_ZPzZ_DtoS : sve_fp_fcvt2z<0b0010, "fcvtxnt", ZPR32, ZPR64>;
+  defm FCVTNT_ZPzZ : sve2_fp_convert_down_narrow_z<"fcvtnt">;
+  def FCVTXNT_ZPzZ : sve2_fp_convert_precision<0b0010, 0b0, "fcvtxnt", ZPR32, ZPR64, /*destructive*/ true>;
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momchil-velikov wrote:

(1) Or one can copy instruction class instead of adding conditional dag patterns.

(2) Also one can go with decoupling the (currently implied) `movprfx`-ability property from the destructive property by adding an explicit flag `bool IsMOVPRFXAble = false` to `AArch64Inst` and setting it to true in the appropriate instructions.

(3) Alternatively, to save some typing, an uglier hackish way could be to  add a `movprfxz`-override flag and change the test to 
```
    if ((MCID.TSFlags & AArch64::NoMOVPRFX) || (MCID.TSFlags & AArch64::DestructiveInstTypeMask) ==
        AArch64::NotDestructive) { ...
```

I don't think (2) or (3) need to be in this patch though.
I would prefer (1), but not hugely important.

https://github.com/llvm/llvm-project/pull/118788