[llvm] Make CombinerHelper methods const (PR #119529)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 01:30:32 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Paul Bowen-Huggett (paulhuggett)
<details>
<summary>Changes</summary>
There are a number of backends (specifically AArch64, AMDGPU, Mips, and RISCV) which contain a “TODO: make CombinerHelper methods const” comment. This PR does just that and makes all of the CombinerHelper methods const, removes the TODO comments and makes the associated instances const. This change makes some sense because the CombinerHelper class simply modifies the state of _other_ objects to which it holds pointers or references.
Note that AMDGPU contains an identical comment for an instance of AMDGPUCombinerHelper (a subclass of CombinerHelper). I deliberately haven’t modified the methods of that class in order to limit the scope of the change. I’m happy to do so either now or as a follow-up.
---
Patch is 165.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119529.diff
16 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h (+309-262)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+295-246)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelperArtifacts.cpp (+2-2)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp (+9-9)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelperCompares.cpp (+4-4)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelperVectorOps.cpp (+12-10)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp (+1-2)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 55c3b72c8e027f..871456d2a55b5e 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -172,17 +172,18 @@ class CombinerHelper {
/// Set the register bank of \p Reg.
/// Does nothing if the RegBank is null.
/// This is the counterpart to getRegBank.
- void setRegBank(Register Reg, const RegisterBank *RegBank);
+ void setRegBank(Register Reg, const RegisterBank *RegBank) const;
/// If \p MI is COPY, try to combine it.
/// Returns true if MI changed.
- bool tryCombineCopy(MachineInstr &MI);
- bool matchCombineCopy(MachineInstr &MI);
- void applyCombineCopy(MachineInstr &MI);
+ bool tryCombineCopy(MachineInstr &MI) const;
+ bool matchCombineCopy(MachineInstr &MI) const;
+ void applyCombineCopy(MachineInstr &MI) const;
/// Returns true if \p DefMI precedes \p UseMI or they are the same
/// instruction. Both must be in the same basic block.
- bool isPredecessor(const MachineInstr &DefMI, const MachineInstr &UseMI);
+ bool isPredecessor(const MachineInstr &DefMI,
+ const MachineInstr &UseMI) const;
/// Returns true if \p DefMI dominates \p UseMI. By definition an
/// instruction dominates itself.
@@ -190,40 +191,50 @@ class CombinerHelper {
/// If we haven't been provided with a MachineDominatorTree during
/// construction, this function returns a conservative result that tracks just
/// a single basic block.
- bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI);
+ bool dominates(const MachineInstr &DefMI, const MachineInstr &UseMI) const;
/// If \p MI is extend that consumes the result of a load, try to combine it.
/// Returns true if MI changed.
- bool tryCombineExtendingLoads(MachineInstr &MI);
- bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
- void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
+ bool tryCombineExtendingLoads(MachineInstr &MI) const;
+ bool matchCombineExtendingLoads(MachineInstr &MI,
+ PreferredTuple &MatchInfo) const;
+ void applyCombineExtendingLoads(MachineInstr &MI,
+ PreferredTuple &MatchInfo) const;
/// Match (and (load x), mask) -> zextload x
- bool matchCombineLoadWithAndMask(MachineInstr &MI, BuildFnTy &MatchInfo);
+ bool matchCombineLoadWithAndMask(MachineInstr &MI,
+ BuildFnTy &MatchInfo) const;
/// Combine a G_EXTRACT_VECTOR_ELT of a load into a narrowed
/// load.
- bool matchCombineExtractedVectorLoad(MachineInstr &MI, BuildFnTy &MatchInfo);
+ bool matchCombineExtractedVectorLoad(MachineInstr &MI,
+ BuildFnTy &MatchInfo) const;
- bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
- void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
+ bool matchCombineIndexedLoadStore(MachineInstr &MI,
+ IndexedLoadStoreMatchInfo &MatchInfo) const;
+ void applyCombineIndexedLoadStore(MachineInstr &MI,
+ IndexedLoadStoreMatchInfo &MatchInfo) const;
- bool matchSextTruncSextLoad(MachineInstr &MI);
- void applySextTruncSextLoad(MachineInstr &MI);
+ bool matchSextTruncSextLoad(MachineInstr &MI) const;
+ void applySextTruncSextLoad(MachineInstr &MI) const;
/// Match sext_inreg(load p), imm -> sextload p
- bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
- void applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
+ bool matchSextInRegOfLoad(MachineInstr &MI,
+ std::tuple<Register, unsigned> &MatchInfo) const;
+ void applySextInRegOfLoad(MachineInstr &MI,
+ std::tuple<Register, unsigned> &MatchInfo) const;
/// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
/// when their source operands are identical.
- bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI);
- void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI);
+ bool matchCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const;
+ void applyCombineDivRem(MachineInstr &MI, MachineInstr *&OtherMI) const;
/// If a brcond's true block is not the fallthrough, make it so by inverting
/// the condition and swapping operands.
- bool matchOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond);
- void applyOptBrCondByInvertingCond(MachineInstr &MI, MachineInstr *&BrCond);
+ bool matchOptBrCondByInvertingCond(MachineInstr &MI,
+ MachineInstr *&BrCond) const;
+ void applyOptBrCondByInvertingCond(MachineInstr &MI,
+ MachineInstr *&BrCond) const;
/// If \p MI is G_CONCAT_VECTORS, try to combine it.
/// Returns true if MI changed.
@@ -239,21 +250,25 @@ class CombinerHelper {
/// needed to produce the flattened build_vector.
///
/// \pre MI.getOpcode() == G_CONCAT_VECTORS.
- bool matchCombineConcatVectors(MachineInstr &MI, SmallVector<Register> &Ops);
+ bool matchCombineConcatVectors(MachineInstr &MI,
+ SmallVector<Register> &Ops) const;
/// Replace \p MI with a flattened build_vector with \p Ops
/// or an implicit_def if \p Ops is empty.
- void applyCombineConcatVectors(MachineInstr &MI, SmallVector<Register> &Ops);
+ void applyCombineConcatVectors(MachineInstr &MI,
+ SmallVector<Register> &Ops) const;
- bool matchCombineShuffleConcat(MachineInstr &MI, SmallVector<Register> &Ops);
+ bool matchCombineShuffleConcat(MachineInstr &MI,
+ SmallVector<Register> &Ops) const;
/// Replace \p MI with a flattened build_vector with \p Ops
/// or an implicit_def if \p Ops is empty.
- void applyCombineShuffleConcat(MachineInstr &MI, SmallVector<Register> &Ops);
+ void applyCombineShuffleConcat(MachineInstr &MI,
+ SmallVector<Register> &Ops) const;
/// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
/// Returns true if MI changed.
///
/// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
- bool tryCombineShuffleVector(MachineInstr &MI);
+ bool tryCombineShuffleVector(MachineInstr &MI) const;
/// Check if the G_SHUFFLE_VECTOR \p MI can be replaced by a
/// concat_vectors.
/// \p Ops will contain the operands needed to produce the flattened
@@ -261,12 +276,12 @@ class CombinerHelper {
///
/// \pre MI.getOpcode() == G_SHUFFLE_VECTOR.
bool matchCombineShuffleVector(MachineInstr &MI,
- SmallVectorImpl<Register> &Ops);
+ SmallVectorImpl<Register> &Ops) const;
/// Replace \p MI with a concat_vectors with \p Ops.
void applyCombineShuffleVector(MachineInstr &MI,
- const ArrayRef<Register> Ops);
- bool matchShuffleToExtract(MachineInstr &MI);
- void applyShuffleToExtract(MachineInstr &MI);
+ const ArrayRef<Register> Ops) const;
+ bool matchShuffleToExtract(MachineInstr &MI) const;
+ void applyShuffleToExtract(MachineInstr &MI) const;
/// Optimize memcpy intrinsics et al, e.g. constant len calls.
/// /p MaxLen if non-zero specifies the max length of a mem libcall to inline.
@@ -298,101 +313,105 @@ class CombinerHelper {
/// $addr = G_INDEXED_STORE $val, $base, $offset
/// [...]
/// $whatever = COPY $addr
- bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
+ bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0) const;
- bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
- void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
+ bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const;
+ void applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo) const;
/// Fold (shift (shift base, x), y) -> (shift base (x+y))
- bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
- void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
+ bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const;
+ void applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo) const;
/// If we have a shift-by-constant of a bitwise logic op that itself has a
/// shift-by-constant operand with identical opcode, we may be able to convert
/// that into 2 independent shifts followed by the logic op.
bool matchShiftOfShiftedLogic(MachineInstr &MI,
- ShiftOfShiftedLogic &MatchInfo);
+ ShiftOfShiftedLogic &MatchInfo) const;
void applyShiftOfShiftedLogic(MachineInstr &MI,
- ShiftOfShiftedLogic &MatchInfo);
+ ShiftOfShiftedLogic &MatchInfo) const;
- bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo);
+ bool matchCommuteShift(MachineInstr &MI, BuildFnTy &MatchInfo) const;
/// Transform a multiply by a power-of-2 value to a left shift.
- bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
- void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
+ bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const;
+ void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const;
// Transform a G_SUB with constant on the RHS to G_ADD.
- bool matchCombineSubToAdd(MachineInstr &MI, BuildFnTy &MatchInfo);
+ bool matchCombineSubToAdd(MachineInstr &MI, BuildFnTy &MatchInfo) const;
// Transform a G_SHL with an extended source into a narrower shift if
// possible.
- bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData);
+ bool matchCombineShlOfExtend(MachineInstr &MI,
+ RegisterImmPair &MatchData) const;
void applyCombineShlOfExtend(MachineInstr &MI,
- const RegisterImmPair &MatchData);
+ const RegisterImmPair &MatchData) const;
/// Fold away a merge of an unmerge of the corresponding values.
- bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo);
+ bool matchCombineMergeUnmerge(MachineInstr &MI, Register &MatchInfo) const;
/// Reduce a shift by a constant to an unmerge and a shift on a half sized
/// type. This will not produce a shift smaller than \p TargetShiftSize.
bool matchCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftSize,
- unsigned &ShiftVal);
- void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
- bool tryCombineShiftToUnmerge(MachineInstr &MI, unsigned TargetShiftAmount);
+ unsigned &ShiftVal) const;
+ void applyCombineShiftToUnmerge(MachineInstr &MI,
+ const unsigned &ShiftVal) const;
+ bool tryCombineShiftToUnmerge(MachineInstr &MI,
+ unsigned TargetShiftAmount) const;
/// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
- bool
- matchCombineUnmergeMergeToPlainValues(MachineInstr &MI,
- SmallVectorImpl<Register> &Operands);
- void
- applyCombineUnmergeMergeToPlainValues(MachineInstr &MI,
- SmallVectorImpl<Register> &Operands);
+ bool matchCombineUnmergeMergeToPlainValues(
+ MachineInstr &MI, SmallVectorImpl<Register> &Operands) const;
+ void applyCombineUnmergeMergeToPlainValues(
+ MachineInstr &MI, SmallVectorImpl<Register> &Operands) const;
/// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
bool matchCombineUnmergeConstant(MachineInstr &MI,
- SmallVectorImpl<APInt> &Csts);
+ SmallVectorImpl<APInt> &Csts) const;
void applyCombineUnmergeConstant(MachineInstr &MI,
- SmallVectorImpl<APInt> &Csts);
+ SmallVectorImpl<APInt> &Csts) const;
/// Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
- bool
- matchCombineUnmergeUndef(MachineInstr &MI,
- std::function<void(MachineIRBuilder &)> &MatchInfo);
+ bool matchCombineUnmergeUndef(
+ MachineInstr &MI,
+ std::function<void(MachineIRBuilder &)> &MatchInfo) const;
/// Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
- bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
- void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI);
+ bool matchCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) const;
+ void applyCombineUnmergeWithDeadLanesToTrunc(MachineInstr &MI) const;
/// Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0
- bool matchCombineUnmergeZExtToZExt(MachineInstr &MI);
- void applyCombineUnmergeZExtToZExt(MachineInstr &MI);
+ bool matchCombineUnmergeZExtToZExt(MachineInstr &MI) const;
+ void applyCombineUnmergeZExtToZExt(MachineInstr &MI) const;
/// Transform fp_instr(cst) to constant result of the fp operation.
- void applyCombineConstantFoldFpUnary(MachineInstr &MI, const ConstantFP *Cst);
+ void applyCombineConstantFoldFpUnary(MachineInstr &MI,
+ const ConstantFP *Cst) const;
/// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
- bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg);
- void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg);
+ bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg) const;
+ void applyCombineI2PToP2I(MachineInstr &MI, Register &Reg) const;
/// Transform PtrToInt(IntToPtr(x)) to x.
- void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg);
+ void applyCombineP2IToI2P(MachineInstr &MI, Register &Reg) const;
/// Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y)
/// Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
- bool matchCombineAddP2IToPtrAdd(MachineInstr &MI,
- std::pair<Register, bool> &PtrRegAndCommute);
- void applyCombineAddP2IToPtrAdd(MachineInstr &MI,
- std::pair<Register, bool> &PtrRegAndCommute);
+ bool
+ matchCombineAddP2IToPtrAdd(MachineInstr &MI,
+ std::pair<Register, bool> &PtrRegAndCommute) const;
+ void
+ applyCombineAddP2IToPtrAdd(MachineInstr &MI,
+ std::pair<Register, bool> &PtrRegAndCommute) const;
// Transform G_PTR_ADD (G_PTRTOINT C1), C2 -> C1 + C2
- bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst);
- void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst);
+ bool matchCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst) const;
+ void applyCombineConstPtrAddToI2P(MachineInstr &MI, APInt &NewCst) const;
/// Transform anyext(trunc(x)) to x.
- bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg);
+ bool matchCombineAnyExtTrunc(MachineInstr &MI, Register &Reg) const;
/// Transform zext(trunc(x)) to x.
- bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg);
+ bool matchCombineZextTrunc(MachineInstr &MI, Register &Reg) const;
/// Transform trunc (shl x, K) to shl (trunc x), K
/// if K < VT.getScalarSizeInBits().
@@ -401,118 +420,121 @@ class CombinerHelper {
/// if K <= (MidVT.getScalarSizeInBits() - VT.getScalarSizeInBits())
/// MidVT is obtained by finding a legal type between the trunc's src and dst
/// types.
- bool matchCombineTruncOfShift(MachineInstr &MI,
- std::pair<MachineInstr *, LLT> &MatchInfo);
- void applyCombineTruncOfShift(MachineInstr &MI,
- std::pair<MachineInstr *, LLT> &MatchInfo);
+ bool
+ matchCombineTruncOfShift(MachineInstr &MI,
+ std::pair<MachineInstr *, LLT> &MatchInfo) const;
+ void
+ applyCombineTruncOfShift(MachineInstr &MI,
+ std::pair<MachineInstr *, LLT> &MatchInfo) const;
/// Return true if any explicit use operand on \p MI is defined by a
/// G_IMPLICIT_DEF.
- bool matchAnyExplicitUseIsUndef(MachineInstr &MI);
+ bool matchAnyExplicitUseIsUndef(MachineInstr &MI) const;
/// Return true if all register explicit use operands on \p MI are defined by
/// a G_IMPLICIT_DEF.
- bool matchAllExplicitUsesAreUndef(MachineInstr &MI);
+ bool matchAllExplicitUsesAreUndef(MachineInstr &MI) const;
/// Return true if a G_SHUFFLE_VECTOR instruction \p MI has an undef mask.
- bool matchUndefShuffleVectorMask(MachineInstr &MI);
+ bool matchUndefShuffleVectorMask(MachineInstr &MI) const;
/// Return true if a G_STORE instruction \p MI is storing an undef value.
- bool matchUndefStore(MachineInstr &MI);
+ bool matchUndefStore(MachineInstr &MI) const;
/// Return true if a G_SELECT instruction \p MI has an undef comparison.
- bool matchUndefSelectCmp(MachineInstr &MI);
+ bool matchUndefSelectCmp(MachineInstr &MI) const;
/// Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
- bool matchInsertExtractVecEltOutOfBounds(MachineInstr &MI);
+ bool matchInsertExtractVecEltOutOfBounds(MachineInstr &MI) const;
/// Return true if a G_SELECT instruction \p MI has a constant comparison. If
/// true, \p OpIdx will store the operand index of the known selected value.
- bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx);
+ bool matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx) const;
/// Replace an instruction with a G_FCONSTANT with value \p C.
- void replaceInstWithFConstant(MachineInstr &MI, double C);
+ void replaceInstWithFConstant(MachineInstr &MI, double C) const;
/// Replace an instruction with an G_FCONSTANT with value \p CFP.
- void replaceInstWithFConstant(MachineInstr &MI, ConstantFP *CFP);
+ void replaceInstWithFConstant(MachineInstr &MI, ConstantFP *CFP) const;
/// Replace an instruction with a G_CONSTANT with value \p C.
- void replaceInstWithConstant(MachineInstr &MI, int64_t C);
+ void replaceInstWithConstant(MachineInstr &MI, int64_t C) const;
/// Replace an instruction with a G_CONSTANT with value \p C.
- void replaceInstWithConstant(MachineInstr &MI, APInt C);
+ void replaceInstWithConstant(MachineInstr &MI, APInt C) const;
/// Replace an instruction with a G_IMPLICIT_DEF.
- void replaceInstWithUndef(MachineInstr &MI);
+ void replaceInstWithUndef(MachineInstr &MI) const;
/// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
- void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
+ void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx) const;
/// Delete \p MI and replace all of its uses with \p Replacement.
- void replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement);
+ void replaceSingleDefInstWithReg(MachineInstr &MI,
+ Register Replacement) const;
/// @brief Replaces the shift amount in \p MI with ShiftAmt % BW
/// @param MI
- void applyFunnelShiftConstantModulo(MachineInstr &MI);
+ void applyFunnelShiftConstantModulo(MachineInstr &MI) const;
/// Return true if \p MOP1 and \p MOP2 are register operands are defined by
/// equivalent instructions.
- bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
+ bool matchEqualDefs(const MachineOperand &MOP1,
+ const MachineOperand &MOP2) const;
/// Return true if \p MOP is defined by a G_CONSTANT or splat with a value equal to
/// \p C.
- bool matchConstantOp(const MachineOperand &MOP, int64_t C);
+ bool matchConstantOp(const MachineOperand &MOP, int64_t C) const;
/// Return true if \p MOP is defined by a G_FCONSTANT or splat with a value exactly
/// equal to \p C.
- bool matchConstantFPOp(const MachineOperand &MOP, double C);
+ bool matchConstantFPOp(const MachineOperand &MOP, double C) const;
/// @brief Checks if constant at \p ConstIdx is lar...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/119529
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