[llvm] ae26f50 - [test] Change llc -march=mips* to -mtriple=mips*
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 10 22:14:13 PST 2024
Author: Fangrui Song
Date: 2024-12-10T22:14:06-08:00
New Revision: ae26f50aea4ef1a6c7058019f0db11a91bbcdade
URL: https://github.com/llvm/llvm-project/commit/ae26f50aea4ef1a6c7058019f0db11a91bbcdade
DIFF: https://github.com/llvm/llvm-project/commit/ae26f50aea4ef1a6c7058019f0db11a91bbcdade.diff
LOG: [test] Change llc -march=mips* to -mtriple=mips*
Similar to 806761a7629df268c8aed49657aeccffa6bca449
Added:
Modified:
llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
llvm/test/CodeGen/MIR/Mips/memory-operands.mir
llvm/test/CodeGen/Mips/2008-06-05-Carry.ll
llvm/test/CodeGen/Mips/2008-07-03-SRet.ll
llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll
llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll
llvm/test/CodeGen/Mips/2008-07-29-icmp.ll
llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll
llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll
llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll
llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll
llvm/test/CodeGen/Mips/2008-08-07-CC.ll
llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll
llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll
llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll
llvm/test/CodeGen/Mips/2010-11-09-Mul.ll
llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
llvm/test/CodeGen/Mips/DbgValueOtherTargets.test
llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll
llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll
llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
llvm/test/CodeGen/Mips/addc.ll
llvm/test/CodeGen/Mips/address-selection.ll
llvm/test/CodeGen/Mips/addressing-mode.ll
llvm/test/CodeGen/Mips/adjust-callstack-sp.ll
llvm/test/CodeGen/Mips/alloca.ll
llvm/test/CodeGen/Mips/alloca16.ll
llvm/test/CodeGen/Mips/and1.ll
llvm/test/CodeGen/Mips/ase_warnings.ll
llvm/test/CodeGen/Mips/asm-large-immediate.ll
llvm/test/CodeGen/Mips/assertzext-trunc.ll
llvm/test/CodeGen/Mips/atomic-min-max-64.ll
llvm/test/CodeGen/Mips/atomic-min-max.ll
llvm/test/CodeGen/Mips/atomicops.ll
llvm/test/CodeGen/Mips/biggot.ll
llvm/test/CodeGen/Mips/brconeq.ll
llvm/test/CodeGen/Mips/brconeqk.ll
llvm/test/CodeGen/Mips/brconeqz.ll
llvm/test/CodeGen/Mips/brconge.ll
llvm/test/CodeGen/Mips/brcongt.ll
llvm/test/CodeGen/Mips/brconle.ll
llvm/test/CodeGen/Mips/brconlt.ll
llvm/test/CodeGen/Mips/brconne.ll
llvm/test/CodeGen/Mips/brconnek.ll
llvm/test/CodeGen/Mips/brconnez.ll
llvm/test/CodeGen/Mips/brind.ll
llvm/test/CodeGen/Mips/brundef.ll
llvm/test/CodeGen/Mips/bswap.ll
llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
llvm/test/CodeGen/Mips/call-optimization.ll
llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
llvm/test/CodeGen/Mips/cconv/callee-saved.ll
llvm/test/CodeGen/Mips/cconv/memory-layout.ll
llvm/test/CodeGen/Mips/cconv/pr33883.ll
llvm/test/CodeGen/Mips/cconv/reserved-space.ll
llvm/test/CodeGen/Mips/cconv/roundl-call.ll
llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
llvm/test/CodeGen/Mips/cfi_offset.ll
llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll
llvm/test/CodeGen/Mips/check-noat.ll
llvm/test/CodeGen/Mips/cins.ll
llvm/test/CodeGen/Mips/cmov.ll
llvm/test/CodeGen/Mips/cmplarge.ll
llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll
llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
llvm/test/CodeGen/Mips/constantfp0.ll
llvm/test/CodeGen/Mips/constraint-c-err.ll
llvm/test/CodeGen/Mips/constraint-c.ll
llvm/test/CodeGen/Mips/constraint-empty.ll
llvm/test/CodeGen/Mips/countleading.ll
llvm/test/CodeGen/Mips/cprestore.ll
llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll
llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
llvm/test/CodeGen/Mips/cstmaterialization/stack.ll
llvm/test/CodeGen/Mips/ctlz-v.ll
llvm/test/CodeGen/Mips/cttz-v.ll
llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll
llvm/test/CodeGen/Mips/delay-slot-kill.ll
llvm/test/CodeGen/Mips/dext.ll
llvm/test/CodeGen/Mips/dins.ll
llvm/test/CodeGen/Mips/disable-tail-merge.ll
llvm/test/CodeGen/Mips/div.ll
llvm/test/CodeGen/Mips/div_rem.ll
llvm/test/CodeGen/Mips/divrem.ll
llvm/test/CodeGen/Mips/divu.ll
llvm/test/CodeGen/Mips/divu_remu.ll
llvm/test/CodeGen/Mips/double2int.ll
llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
llvm/test/CodeGen/Mips/dsp-patterns.ll
llvm/test/CodeGen/Mips/dsp-r1.ll
llvm/test/CodeGen/Mips/dsp-r2.ll
llvm/test/CodeGen/Mips/dsp-vec-load-store.ll
llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll
llvm/test/CodeGen/Mips/eh-return32.ll
llvm/test/CodeGen/Mips/eh-return64.ll
llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
llvm/test/CodeGen/Mips/emit-big-cst.ll
llvm/test/CodeGen/Mips/ex2.ll
llvm/test/CodeGen/Mips/extins.ll
llvm/test/CodeGen/Mips/fastcc.ll
llvm/test/CodeGen/Mips/fcmp.ll
llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
llvm/test/CodeGen/Mips/fcopysign.ll
llvm/test/CodeGen/Mips/fmadd1.ll
llvm/test/CodeGen/Mips/fp-contract.ll
llvm/test/CodeGen/Mips/fp-indexed-ls.ll
llvm/test/CodeGen/Mips/fp-spill-reload.ll
llvm/test/CodeGen/Mips/fp64a.ll
llvm/test/CodeGen/Mips/fpbr.ll
llvm/test/CodeGen/Mips/fpxx.ll
llvm/test/CodeGen/Mips/frame-address-err.ll
llvm/test/CodeGen/Mips/frame-address.ll
llvm/test/CodeGen/Mips/frem.ll
llvm/test/CodeGen/Mips/global-pointer-reg.ll
llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll
llvm/test/CodeGen/Mips/hf16_1.ll
llvm/test/CodeGen/Mips/i64arg.ll
llvm/test/CodeGen/Mips/imm.ll
llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
llvm/test/CodeGen/Mips/inlineasm-constraint.ll
llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll
llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
llvm/test/CodeGen/Mips/ins.ll
llvm/test/CodeGen/Mips/instverify/dext-pos.mir
llvm/test/CodeGen/Mips/instverify/dext-size.mir
llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
llvm/test/CodeGen/Mips/instverify/dextm-size.mir
llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
llvm/test/CodeGen/Mips/instverify/dextu-size.mir
llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
llvm/test/CodeGen/Mips/instverify/dins-pos.mir
llvm/test/CodeGen/Mips/instverify/dins-size.mir
llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
llvm/test/CodeGen/Mips/instverify/ext-pos.mir
llvm/test/CodeGen/Mips/instverify/ext-size.mir
llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
llvm/test/CodeGen/Mips/instverify/ins-pos.mir
llvm/test/CodeGen/Mips/instverify/ins-size.mir
llvm/test/CodeGen/Mips/int-to-float-conversion.ll
llvm/test/CodeGen/Mips/internalfunc.ll
llvm/test/CodeGen/Mips/jumptable_labels.ll
llvm/test/CodeGen/Mips/largeimm1.ll
llvm/test/CodeGen/Mips/largeimmprinting.ll
llvm/test/CodeGen/Mips/lazy-binding.ll
llvm/test/CodeGen/Mips/lb1.ll
llvm/test/CodeGen/Mips/lbu1.ll
llvm/test/CodeGen/Mips/lh1.ll
llvm/test/CodeGen/Mips/lhu1.ll
llvm/test/CodeGen/Mips/llcarry.ll
llvm/test/CodeGen/Mips/llvm-ir/abs.ll
llvm/test/CodeGen/Mips/llvm-ir/add.ll
llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll
llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
llvm/test/CodeGen/Mips/llvm-ir/call.ll
llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll
llvm/test/CodeGen/Mips/llvm-ir/mul.ll
llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll
llvm/test/CodeGen/Mips/llvm-ir/not.ll
llvm/test/CodeGen/Mips/llvm-ir/ret.ll
llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll
llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll
llvm/test/CodeGen/Mips/llvm-ir/sub.ll
llvm/test/CodeGen/Mips/load-store-left-right.ll
llvm/test/CodeGen/Mips/long-call-attr.ll
llvm/test/CodeGen/Mips/long-call-mcount.ll
llvm/test/CodeGen/Mips/long-calls.ll
llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
llvm/test/CodeGen/Mips/machineverifier.ll
llvm/test/CodeGen/Mips/madd-msub.ll
llvm/test/CodeGen/Mips/mcount.ll
llvm/test/CodeGen/Mips/memcpy.ll
llvm/test/CodeGen/Mips/micromips-addiu.ll
llvm/test/CodeGen/Mips/micromips-addu16.ll
llvm/test/CodeGen/Mips/micromips-and16.ll
llvm/test/CodeGen/Mips/micromips-andi.ll
llvm/test/CodeGen/Mips/micromips-attr.ll
llvm/test/CodeGen/Mips/micromips-compact-branches.ll
llvm/test/CodeGen/Mips/micromips-compact-jump.ll
llvm/test/CodeGen/Mips/micromips-gp-rc.ll
llvm/test/CodeGen/Mips/micromips-li.ll
llvm/test/CodeGen/Mips/micromips-load-effective-address.ll
llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
llvm/test/CodeGen/Mips/micromips-not16.ll
llvm/test/CodeGen/Mips/micromips-or16.ll
llvm/test/CodeGen/Mips/micromips-shift.ll
llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll
llvm/test/CodeGen/Mips/micromips-subu16.ll
llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll
llvm/test/CodeGen/Mips/micromips-xor16.ll
llvm/test/CodeGen/Mips/mips16_32_1.ll
llvm/test/CodeGen/Mips/mips16fpe.ll
llvm/test/CodeGen/Mips/mips3-spill-slot.ll
llvm/test/CodeGen/Mips/mips32r6/compatibility.ll
llvm/test/CodeGen/Mips/mips64-f128-call.ll
llvm/test/CodeGen/Mips/mips64-libcall.ll
llvm/test/CodeGen/Mips/mips64-sret.ll
llvm/test/CodeGen/Mips/mips64directive.ll
llvm/test/CodeGen/Mips/mips64ext.ll
llvm/test/CodeGen/Mips/mips64extins.ll
llvm/test/CodeGen/Mips/mips64fpimm0.ll
llvm/test/CodeGen/Mips/mips64fpldst.ll
llvm/test/CodeGen/Mips/mips64imm.ll
llvm/test/CodeGen/Mips/mips64instrs.ll
llvm/test/CodeGen/Mips/mips64intldst.ll
llvm/test/CodeGen/Mips/mips64lea.ll
llvm/test/CodeGen/Mips/mips64muldiv.ll
llvm/test/CodeGen/Mips/mips64r6/compatibility.ll
llvm/test/CodeGen/Mips/mips64shift.ll
llvm/test/CodeGen/Mips/mips64signextendsesf.ll
llvm/test/CodeGen/Mips/mips64sinttofpsf.ll
llvm/test/CodeGen/Mips/mipslopat.ll
llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
llvm/test/CodeGen/Mips/misha.ll
llvm/test/CodeGen/Mips/msa/2r.ll
llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
llvm/test/CodeGen/Mips/msa/2rf.ll
llvm/test/CodeGen/Mips/msa/2rf_exup.ll
llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
llvm/test/CodeGen/Mips/msa/2rf_fq.ll
llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
llvm/test/CodeGen/Mips/msa/2rf_tq.ll
llvm/test/CodeGen/Mips/msa/3r-a.ll
llvm/test/CodeGen/Mips/msa/3r-b.ll
llvm/test/CodeGen/Mips/msa/3r-c.ll
llvm/test/CodeGen/Mips/msa/3r-d.ll
llvm/test/CodeGen/Mips/msa/3r-i.ll
llvm/test/CodeGen/Mips/msa/3r-m.ll
llvm/test/CodeGen/Mips/msa/3r-p.ll
llvm/test/CodeGen/Mips/msa/3r-s.ll
llvm/test/CodeGen/Mips/msa/3r-v.ll
llvm/test/CodeGen/Mips/msa/3r_4r.ll
llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
llvm/test/CodeGen/Mips/msa/3r_splat.ll
llvm/test/CodeGen/Mips/msa/3rf.ll
llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
llvm/test/CodeGen/Mips/msa/3rf_q.ll
llvm/test/CodeGen/Mips/msa/arithmetic.ll
llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
llvm/test/CodeGen/Mips/msa/basic_operations.ll
llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
llvm/test/CodeGen/Mips/msa/bit.ll
llvm/test/CodeGen/Mips/msa/bitcast.ll
llvm/test/CodeGen/Mips/msa/bitwise.ll
llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
llvm/test/CodeGen/Mips/msa/compare.ll
llvm/test/CodeGen/Mips/msa/compare_float.ll
llvm/test/CodeGen/Mips/msa/elm_copy.ll
llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
llvm/test/CodeGen/Mips/msa/elm_insv.ll
llvm/test/CodeGen/Mips/msa/elm_move.ll
llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
llvm/test/CodeGen/Mips/msa/emergency-spill.mir
llvm/test/CodeGen/Mips/msa/endian.ll
llvm/test/CodeGen/Mips/msa/fexuprl.ll
llvm/test/CodeGen/Mips/msa/frameindex.ll
llvm/test/CodeGen/Mips/msa/i10.ll
llvm/test/CodeGen/Mips/msa/i5-a.ll
llvm/test/CodeGen/Mips/msa/i5-b.ll
llvm/test/CodeGen/Mips/msa/i5-c.ll
llvm/test/CodeGen/Mips/msa/i5-m.ll
llvm/test/CodeGen/Mips/msa/i5-s.ll
llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
llvm/test/CodeGen/Mips/msa/i8.ll
llvm/test/CodeGen/Mips/msa/immediates-bad.ll
llvm/test/CodeGen/Mips/msa/immediates.ll
llvm/test/CodeGen/Mips/msa/inline-asm.ll
llvm/test/CodeGen/Mips/msa/ldr_str.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll
llvm/test/CodeGen/Mips/msa/nori.b.ll
llvm/test/CodeGen/Mips/msa/remat-ldi.ll
llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
llvm/test/CodeGen/Mips/msa/shift_no_and.ll
llvm/test/CodeGen/Mips/msa/shuffle.ll
llvm/test/CodeGen/Mips/msa/special.ll
llvm/test/CodeGen/Mips/msa/spill.ll
llvm/test/CodeGen/Mips/msa/vec.ll
llvm/test/CodeGen/Mips/msa/vecs10.ll
llvm/test/CodeGen/Mips/mul.ll
llvm/test/CodeGen/Mips/mulll.ll
llvm/test/CodeGen/Mips/mulull.ll
llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
llvm/test/CodeGen/Mips/neg1.ll
llvm/test/CodeGen/Mips/nmadd.ll
llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll
llvm/test/CodeGen/Mips/not1.ll
llvm/test/CodeGen/Mips/null.ll
llvm/test/CodeGen/Mips/o32_cc.ll
llvm/test/CodeGen/Mips/o32_cc_vararg.ll
llvm/test/CodeGen/Mips/octeon.ll
llvm/test/CodeGen/Mips/octeon_popcnt.ll
llvm/test/CodeGen/Mips/optimize-fp-math.ll
llvm/test/CodeGen/Mips/or1.ll
llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
llvm/test/CodeGen/Mips/pr33682.ll
llvm/test/CodeGen/Mips/pr33978.ll
llvm/test/CodeGen/Mips/prevent-hoisting.ll
llvm/test/CodeGen/Mips/private.ll
llvm/test/CodeGen/Mips/ra-allocatable.ll
llvm/test/CodeGen/Mips/rem.ll
llvm/test/CodeGen/Mips/remat-immed-load.ll
llvm/test/CodeGen/Mips/remu.ll
llvm/test/CodeGen/Mips/return-vector.ll
llvm/test/CodeGen/Mips/return_address.ll
llvm/test/CodeGen/Mips/return_address_err.ll
llvm/test/CodeGen/Mips/rotate.ll
llvm/test/CodeGen/Mips/sb1.ll
llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
llvm/test/CodeGen/Mips/selTBtnezSlti.ll
llvm/test/CodeGen/Mips/selectcc.ll
llvm/test/CodeGen/Mips/selectiondag-optlevel.ll
llvm/test/CodeGen/Mips/seleq.ll
llvm/test/CodeGen/Mips/seleqk.ll
llvm/test/CodeGen/Mips/selgek.ll
llvm/test/CodeGen/Mips/selgt.ll
llvm/test/CodeGen/Mips/selle.ll
llvm/test/CodeGen/Mips/selltk.ll
llvm/test/CodeGen/Mips/selne.ll
llvm/test/CodeGen/Mips/selnek.ll
llvm/test/CodeGen/Mips/selpat.ll
llvm/test/CodeGen/Mips/setcc-se.ll
llvm/test/CodeGen/Mips/seteq.ll
llvm/test/CodeGen/Mips/seteqz.ll
llvm/test/CodeGen/Mips/setge.ll
llvm/test/CodeGen/Mips/setgek.ll
llvm/test/CodeGen/Mips/setle.ll
llvm/test/CodeGen/Mips/setlt.ll
llvm/test/CodeGen/Mips/setltk.ll
llvm/test/CodeGen/Mips/setne.ll
llvm/test/CodeGen/Mips/setuge.ll
llvm/test/CodeGen/Mips/setugt.ll
llvm/test/CodeGen/Mips/setule.ll
llvm/test/CodeGen/Mips/setult.ll
llvm/test/CodeGen/Mips/setultk.ll
llvm/test/CodeGen/Mips/sh1.ll
llvm/test/CodeGen/Mips/shift-parts.ll
llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll
llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
llvm/test/CodeGen/Mips/sll1.ll
llvm/test/CodeGen/Mips/sll2.ll
llvm/test/CodeGen/Mips/slt.ll
llvm/test/CodeGen/Mips/spill-copy-acreg.ll
llvm/test/CodeGen/Mips/sra1.ll
llvm/test/CodeGen/Mips/sra2.ll
llvm/test/CodeGen/Mips/srl1.ll
llvm/test/CodeGen/Mips/srl2.ll
llvm/test/CodeGen/Mips/stack-alignment.ll
llvm/test/CodeGen/Mips/stackcoloring.ll
llvm/test/CodeGen/Mips/stchar.ll
llvm/test/CodeGen/Mips/stldst.ll
llvm/test/CodeGen/Mips/sub1.ll
llvm/test/CodeGen/Mips/sub2.ll
llvm/test/CodeGen/Mips/swzero.ll
llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll
llvm/test/CodeGen/Mips/thread-pointer.ll
llvm/test/CodeGen/Mips/tls-alias.ll
llvm/test/CodeGen/Mips/tnaked.ll
llvm/test/CodeGen/Mips/trap.ll
llvm/test/CodeGen/Mips/uitofp.ll
llvm/test/CodeGen/Mips/ul1.ll
llvm/test/CodeGen/Mips/unaligned-memops.ll
llvm/test/CodeGen/Mips/unalignedload.ll
llvm/test/CodeGen/Mips/vector-load-store.ll
llvm/test/CodeGen/Mips/vector-setcc.ll
llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
llvm/test/CodeGen/Mips/vr4300-mulmul.ll
llvm/test/CodeGen/Mips/weak.ll
llvm/test/CodeGen/Mips/whitespace.ll
llvm/test/CodeGen/Mips/xor1.ll
llvm/test/CodeGen/Mips/zeroreg.ll
llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
llvm/test/DebugInfo/Mips/tls.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
index 4874410c6a6e94..da0af94b98268c 100644
--- a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
+++ b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %a) {
entry:
diff --git a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
index c64b9dacd9a624..f7da11372fa65c 100644
--- a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
+++ b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the call entry pseudo source
# values in memory operands correctly.
diff --git a/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll b/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll
index 5e6092fc7848dd..d233ef978276f6 100644
--- a/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll
+++ b/llvm/test/CodeGen/Mips/2008-06-05-Carry.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
define i64 @add64(i64 %u, i64 %v) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll b/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll
index 7654ef271fcc96..51d73a319494c4 100644
--- a/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
%struct.sret0 = type { i32, i32, i32 }
diff --git a/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll b/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll
index 29c8e8446e3d2f..dcd3adc3c671e3 100644
--- a/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-07-FPExtend.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=single-float < %s | FileCheck %s
define double @dofloat(float %a) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll b/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
index 9a6bbdfb22ff5b..a748841afe7678 100644
--- a/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=single-float < %s | FileCheck %s
define double @int2fp(i32 %a) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
index 8807d750e49928..e4c1eba9a6ca50 100644
--- a/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s
define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind {
diff --git a/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll
index 9c547f15c9a6b8..8fe8ac539a90f8 100644
--- a/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-23-fpcmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -o %t
+; RUN: llc < %s -mtriple=mips -o %t
; RUN: grep "c\..*\.s" %t | count 3
; RUN: grep "bc1[tf]" %t | count 3
diff --git a/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll b/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll
index e88e3d3755c4b6..e962ec6cfb8b90 100644
--- a/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-29-icmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips | grep "b[ne][eq]" | count 1
+; RUN: llc < %s -mtriple=mips | grep "b[ne][eq]" | count 1
; FIXME: Disabled because branch instructions are generated where
; conditional move instructions are expected.
diff --git a/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll b/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll
index f152acc9a15d21..cfbea9cf6277b6 100644
--- a/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll
+++ b/llvm/test/CodeGen/Mips/2008-07-31-fcopysign.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -o %t
+; RUN: llc < %s -mtriple=mips -o %t
; RUN: grep abs.s %t | count 1
; RUN: grep neg.s %t | count 1
diff --git a/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll b/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll
index 74a3f218379b52..4eaf0095007458 100644
--- a/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-01-AsmInline.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
%struct.DWstruct = type { i32, i32 }
diff --git a/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll b/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
index 7c19c15ca7bb46..c3931417a758b2 100644
--- a/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-03-ReturnDouble.ll
@@ -1,5 +1,5 @@
; Double return in abicall (default)
-; RUN: llc < %s -march=mips
+; RUN: llc < %s -mtriple=mips
; PR2615
define double @main(...) {
diff --git a/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll b/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll
index 2b1713c39f7268..18c01065dec95b 100644
--- a/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-03-fabs64.ll
@@ -1,4 +1,4 @@
-; DISABLED: llc < %s -march=mips -o %t
+; DISABLED: llc < %s -mtriple=mips -o %t
; DISABLED: grep {lui.*32767} %t | count 1
; DISABLED: grep {ori.*65535} %t | count 1
; RUN: false
diff --git a/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll b/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
index 78a49ffbe44430..8fcda34f889a5a 100644
--- a/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-04-Bitconvert.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
define float @A(i32 %u) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll b/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll
index 84d92e3189ea16..e4c648888cce89 100644
--- a/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-06-Alloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
define i32 @twoalloca(i32 %size) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-08-07-CC.ll b/llvm/test/CodeGen/Mips/2008-08-07-CC.ll
index 63c25951423a03..cc7493759d423d 100644
--- a/llvm/test/CodeGen/Mips/2008-08-07-CC.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-07-CC.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips
+; RUN: llc < %s -mtriple=mips
; Mips must ignore fastcc
target datalayout =
diff --git a/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll b/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll
index 4fa43b6833bde9..ff15bdf367dfc8 100644
--- a/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-07-FPRound.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=single-float < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=single-float < %s | FileCheck %s
define float @round2float(double %a) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll b/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll
index abd61de5a8d870..e76aef9a13408d 100644
--- a/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll
+++ b/llvm/test/CodeGen/Mips/2008-08-08-ctlz.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
define i32 @A0(i32 %u) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll b/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
index d2e054b17973df..ed3938d2b42f16 100644
--- a/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
+++ b/llvm/test/CodeGen/Mips/2008-10-13-LegalizerBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips
+; RUN: llc < %s -mtriple=mips
; PR2794
define i32 @main(ptr) nounwind {
diff --git a/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll b/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
index d80da658d92837..c2a8eb06fbcec5 100644
--- a/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
+++ b/llvm/test/CodeGen/Mips/2008-11-10-xint_to_fp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=+soft-float < %s
+; RUN: llc -mtriple=mips -mattr=+soft-float < %s
; PR2667
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
%struct._Bigint = type { ptr, i32, i32, i32, i32, [1 x i32] }
diff --git a/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll b/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll
index 6174500d3e0b41..05a29ed06bea98 100644
--- a/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll
+++ b/llvm/test/CodeGen/Mips/2010-11-09-CountLeading.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
; CHECK: clz $2, $4
define i32 @t1(i32 %X) nounwind readnone {
diff --git a/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll b/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll
index dcade3c671db18..52112e83be5360 100644
--- a/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll
+++ b/llvm/test/CodeGen/Mips/2010-11-09-Mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
; CHECK: mul $2, $5, $4
define i32 @mul1(i32 %a, i32 %b) nounwind readnone {
diff --git a/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll b/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
index 745d57c8e9a2d7..9cf5c9a72ea047 100644
--- a/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
+++ b/llvm/test/CodeGen/Mips/2012-12-12-ExpandMemcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s
@.str = private unnamed_addr constant [7 x i8] c"hello\0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test b/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test
index da20e7ef5224ec..4d32a7fb9cbb5f 100644
--- a/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test
+++ b/llvm/test/CodeGen/Mips/DbgValueOtherTargets.test
@@ -1 +1 @@
-RUN: llc -O0 -march=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
+RUN: llc -O0 -mtriple=mips -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
index 2f0f1a04a55886..203202e0bd0535 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@b = global i32 1, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
index b5cf2a2030d29e..cb2ff41fa7fb48 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
; RUN: < %s -verify-machineinstrs | FileCheck %s
define void @testeq(i32, i32) {
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
index b8973efda17985..c3b1584a7e9a0d 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
@@ -1,39 +1,39 @@
; Targets where we should not enable FastISel.
-; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips2 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mattr=mips16 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s
; Valid targets for FastISel.
-; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r0 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL
-; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL
; The CHECK prefix is being used by those targets that do not support FastISel.
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll b/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
index f89802d1a11c05..b1fc6cf52a37e9 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic \
; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic \
; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s
@ARR = external global [10 x i32], align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
index effa0473838828..fb35864171aead 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
; RUN: -fast-isel-abort=3 | FileCheck %s
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel-abort=3 | FileCheck %s
@sj = global i32 200000, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
index 16cba99ad0657d..6eccc9f498da1f 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \
+; RUN: not --crash llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 \
; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s
; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
index b69000fc625eae..baac5950823652 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \
+; RUN: not --crash llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+soft-float \
; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s
; Test that FastISel aborts instead of trying to lower arguments for soft-float.
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
index 73e5f714802f60..6044e6b6dd90a0 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s -verify-machineinstrs | FileCheck %s
%struct.x = type { i32 }
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
index 0aec8d506f778a..9156cc6da25e14 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -pass-remarks-missed=isel 2>&1 | FileCheck %s
; CHECK: FastISel missed call:
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
index 95270ff6b272d5..a60b9673ad8b18 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s
@f1 = common global float 0.000000e+00, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
index fbd5039f20a1a3..1d4d8ed6d27c5b 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@f = global float 0x40147E6B80000000, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
index 67b509938c40a5..57226a94a759fc 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
index 0a414316fa1b74..36a8cbfd558d77 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@d = global double 0x40147E6B74DF0446, align 8
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
index 53783c11785fb2..3cd2f6b43a50d9 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@c = global i32 4, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
index 37e49c2e8a428b..84cdd9456dc821 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
; RUN: < %s -verify-machineinstrs | FileCheck %s
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll
index 66c1f4f30c1535..31ad7df23a96d8 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpi1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
; RUN: < %s -verify-machineinstrs | FileCheck %s
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
index 93865a9b5c12fb..a5c1cec0ea11f2 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
@@ -4,9 +4,9 @@ target triple = "mips--linux-gnu"
@c2 = common global i8 0, align 1
@c1 = common global i8 0, align 1
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@s2 = common global i16 0, align 2
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
index 2a75b808cb7ea1..740aa78459a19a 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32
@b2 = global i8 0, align 1
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
index 66b615bad4dc7d..bc6f2c50a805a9 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
index 494dcd19a5b8a2..90db1fde96fe09 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s
@ub1 = common global i8 0, align 1
@ub2 = common global i8 0, align 1
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll
index 8713e7ef1d9666..d84a10b2b111d1 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/mul1.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic
; The test is just to make sure it is able to allocate
; registers for this example. There was an issue with allocating AC0
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
index 617b9bb07dd9f2..cb71cb426e6409 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
; Function Attrs: nounwind
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
index 2ed6117dd7338f..8f2b8c5ecc7ab0 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@x = common global [128000 x float] zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
index cc0fc47d1b874d..c37278350785c0 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
; RUN: -fast-isel-abort=3 | FileCheck %s
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel-abort=3 | FileCheck %s
@sj = global i32 200, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
index c8023e97d5936d..dcfe84e4d22265 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
@i = global i32 75, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
index 923ccaede29d5e..b49478998a86c8 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 \
; RUN: -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 \
; RUN: -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s
@s1 = global i16 -89, align 2
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
index d029ea4973b416..25df91a6fae92b 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@abcd = external global i32
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
index 1957453f550687..d1a0574a198261 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32
@f = common global float 0.000000e+00, align 4
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
index 2f73d1cb890c02..ee174ddbc25d1f 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
+; RUN: llc -mtriple=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@ijk = external global i32
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll b/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
index f0974d580fe706..0541b8de7f476e 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -fast-isel -frame-pointer=all -relocation-model=pic < %s
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -fast-isel -frame-pointer=all -relocation-model=pic < %s
; Test that negative array access don't crash constant synthesis when fast isel
; generates negative offsets.
diff --git a/llvm/test/CodeGen/Mips/addc.ll b/llvm/test/CodeGen/Mips/addc.ll
index 6877b3b633ce0d..13467ac84c813c 100644
--- a/llvm/test/CodeGen/Mips/addc.ll
+++ b/llvm/test/CodeGen/Mips/addc.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mipsel | FileCheck %s
-; RUN: llc < %s -march=mips | FileCheck %s
+; RUN: llc < %s -mtriple=mipsel | FileCheck %s
+; RUN: llc < %s -mtriple=mips | FileCheck %s
define void @f(i64 %l, ptr nocapture %p) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/address-selection.ll b/llvm/test/CodeGen/Mips/address-selection.ll
index d7b3fc66813c60..8b269aeb83b3fb 100644
--- a/llvm/test/CodeGen/Mips/address-selection.ll
+++ b/llvm/test/CodeGen/Mips/address-selection.ll
@@ -1,9 +1,9 @@
-; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips -relocation-model=pic -mattr=+xgot < %s \
+; RUN: llc -mtriple=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot < %s \
; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MIPS-XGOT
-; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \
+; RUN: llc -mtriple=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \
; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MM-XGOT
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/Mips/addressing-mode.ll b/llvm/test/CodeGen/Mips/addressing-mode.ll
index bd8daf45be2c40..74543f6cdb9fda 100644
--- a/llvm/test/CodeGen/Mips/addressing-mode.ll
+++ b/llvm/test/CodeGen/Mips/addressing-mode.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll b/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll
index c583ff0fdd6cff..821904686a436f 100644
--- a/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll
+++ b/llvm/test/CodeGen/Mips/adjust-callstack-sp.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=M16
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32
-; RUN: llc < %s -march=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64
-; RUN: llc < %s -march=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64
+; RUN: llc < %s -mtriple=mips -mattr=mips16 | FileCheck %s -check-prefix=M16
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64
+; RUN: llc < %s -mtriple=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64
+; RUN: llc < %s -mtriple=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64
declare void @bar(ptr)
diff --git a/llvm/test/CodeGen/Mips/alloca.ll b/llvm/test/CodeGen/Mips/alloca.ll
index 1fd6d859954ad6..e4ac0e46044c61 100644
--- a/llvm/test/CodeGen/Mips/alloca.ll
+++ b/llvm/test/CodeGen/Mips/alloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
define i32 @twoalloca(i32 %size) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/alloca16.ll b/llvm/test/CodeGen/Mips/alloca16.ll
index b6921d59e94c95..f074b2d56936f7 100644
--- a/llvm/test/CodeGen/Mips/alloca16.ll
+++ b/llvm/test/CodeGen/Mips/alloca16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 25, align 4
@jjjj = global i32 35, align 4
diff --git a/llvm/test/CodeGen/Mips/and1.ll b/llvm/test/CodeGen/Mips/and1.ll
index 7b5380fab2fdf2..e3577343dbe77d 100644
--- a/llvm/test/CodeGen/Mips/and1.ll
+++ b/llvm/test/CodeGen/Mips/and1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@x = global i32 65504, align 4
@y = global i32 60929, align 4
diff --git a/llvm/test/CodeGen/Mips/ase_warnings.ll b/llvm/test/CodeGen/Mips/ase_warnings.ll
index ede830c72ebefd..35103b4012a6ec 100644
--- a/llvm/test/CodeGen/Mips/ase_warnings.ll
+++ b/llvm/test/CodeGen/Mips/ase_warnings.ll
@@ -1,61 +1,61 @@
; Check msa warnings.
-; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=MSA_32
-; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+msa < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+msa < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=MSA_64
-; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r5 -mattr=+msa -mattr=+fp64 < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=MSA_32_NO_WARNING
-; RUN: llc -march=mips64 -mattr=+mips64r5 -mattr=+msa < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r5 -mattr=+msa < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=MSA_64_NO_WARNING
; Check dspr2 warnings.
-; RUN: llc -march=mips -mattr=+mips32 -mattr=+dspr2 < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32 -mattr=+dspr2 < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSPR2_32
-; RUN: llc -march=mips64 -mattr=+mips64 -mattr=+dspr2 < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64 -mattr=+dspr2 < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSPR2_64
-; RUN: llc -march=mips64 -mattr=+mips64r3 -mattr=+dspr2 < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r3 -mattr=+dspr2 < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSPR2_64_NO_WARNING
-; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+dspr2 < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+dspr2 < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSPR2_32_NO_WARNING
; Check dsp warnings.
-; RUN: llc -march=mips -mattr=+mips32 -mattr=+dsp < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32 -mattr=+dsp < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSP_32
-; RUN: llc -march=mips64 -mattr=+mips64 -mattr=+dsp < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64 -mattr=+dsp < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSP_64
-; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+dsp < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r5 -mattr=+dsp < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSP_32_NO_WARNING
-; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+dsp < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+dsp < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=DSP_64_NO_WARNING
; Check virt warnings.
-; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+virt < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+virt < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=VIRT_32
-; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+virt < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+virt < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=VIRT_64
-; RUN: llc -march=mips -mattr=+mips32r5 -mattr=+virt < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r5 -mattr=+virt < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=VIRT_32_NO_WARNING
-; RUN: llc -march=mips64 -mattr=+mips64r5 -mattr=+virt < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r5 -mattr=+virt < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=VIRT_64_NO_WARNING
; Check crc warnings.
-; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+crc < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+crc < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=CRC_32
-; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+crc < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+crc < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=CRC_64
-; RUN: llc -march=mips -mattr=+mips32r6 -mattr=+crc < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r6 -mattr=+crc < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=CRC_32_NO_WARNING
-; RUN: llc -march=mips64 -mattr=+mips64r6 -mattr=+crc < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r6 -mattr=+crc < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=CRC_64_NO_WARNING
; Check ginv warnings.
-; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+ginv < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r2 -mattr=+ginv < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=GINV_32
-; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+ginv < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r2 -mattr=+ginv < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=GINV_64
-; RUN: llc -march=mips -mattr=+mips32r6 -mattr=+ginv < %s 2>&1 | \
+; RUN: llc -mtriple=mips -mattr=+mips32r6 -mattr=+ginv < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=GINV_32_NO_WARNING
-; RUN: llc -march=mips64 -mattr=+mips64r6 -mattr=+ginv < %s 2>&1 | \
+; RUN: llc -mtriple=mips64 -mattr=+mips64r6 -mattr=+ginv < %s 2>&1 | \
; RUN: FileCheck %s -check-prefix=GINV_64_NO_WARNING
; MSA_32: warning: the 'msa' ASE requires MIPS32 revision 5 or greater
diff --git a/llvm/test/CodeGen/Mips/asm-large-immediate.ll b/llvm/test/CodeGen/Mips/asm-large-immediate.ll
index c75b9e4ad12be4..848be30839a8a3 100644
--- a/llvm/test/CodeGen/Mips/asm-large-immediate.ll
+++ b/llvm/test/CodeGen/Mips/asm-large-immediate.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -no-integrated-as < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -no-integrated-as < %s | FileCheck %s
define void @test() {
entry:
diff --git a/llvm/test/CodeGen/Mips/assertzext-trunc.ll b/llvm/test/CodeGen/Mips/assertzext-trunc.ll
index 2295727834eb04..a6b9c0a2066a4f 100644
--- a/llvm/test/CodeGen/Mips/assertzext-trunc.ll
+++ b/llvm/test/CodeGen/Mips/assertzext-trunc.ll
@@ -1,16 +1,16 @@
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | \
; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \
; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \
; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \
; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | \
; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | \
; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \
; RUN: FileCheck %s -check-prefixes=ALL,R6
; Check that we don't emit redundant SLLs for sequences of
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll
index 5273f499cedec7..62af633ea8957f 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max-64.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max-64.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
+; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
+; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
define i64 @test_max(ptr nocapture %ptr, i64 signext %val) {
; MIPS-LABEL: test_max:
diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll
index 3d3225509d1ae1..a10db052a4ff26 100644
--- a/llvm/test/CodeGen/Mips/atomic-min-max.ll
+++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
-; RUN: llc -march=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6
-; RUN: llc -march=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL
-; RUN: llc -march=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6
+; RUN: llc -mtriple=mips -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSR6
+; RUN: llc -mtriple=mips -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSEL
+; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPSELR6
+; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMEL
+; RUN: llc -mtriple=mipsel -O0 -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MMELR6
+; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r2 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64EL
+; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r6 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=MIPS64ELR6
define i32 @test_max_32(ptr nocapture %ptr, i32 signext %val) {
; MIPS-LABEL: test_max_32:
diff --git a/llvm/test/CodeGen/Mips/atomicops.ll b/llvm/test/CodeGen/Mips/atomicops.ll
index 14e401e1f09632..906429b14a1810 100644
--- a/llvm/test/CodeGen/Mips/atomicops.ll
+++ b/llvm/test/CodeGen/Mips/atomicops.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/biggot.ll b/llvm/test/CodeGen/Mips/biggot.ll
index 1080922ade8098..50d72b9219c5c1 100644
--- a/llvm/test/CodeGen/Mips/biggot.ll
+++ b/llvm/test/CodeGen/Mips/biggot.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mipsel -mattr=+xgot \
+; RUN: llc -mtriple=mipsel -mattr=+xgot \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+xgot \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+xgot \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64
-; RUN: llc -march=mipsel -mattr=+xgot -fast-isel \
+; RUN: llc -mtriple=mipsel -mattr=+xgot -fast-isel \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+xgot -fast-isel \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+xgot -fast-isel \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64
@v0 = external global i32
diff --git a/llvm/test/CodeGen/Mips/brconeq.ll b/llvm/test/CodeGen/Mips/brconeq.ll
index ba7dc0f8540e6c..468456effd4774 100644
--- a/llvm/test/CodeGen/Mips/brconeq.ll
+++ b/llvm/test/CodeGen/Mips/brconeq.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 5, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconeqk.ll b/llvm/test/CodeGen/Mips/brconeqk.ll
index 4ee2f772ff68e0..d0c6656cb52e10 100644
--- a/llvm/test/CodeGen/Mips/brconeqk.ll
+++ b/llvm/test/CodeGen/Mips/brconeqk.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 5, align 4
@result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brconeqz.ll b/llvm/test/CodeGen/Mips/brconeqz.ll
index b8e7d1d12f9789..c99c5a2e47d6e2 100644
--- a/llvm/test/CodeGen/Mips/brconeqz.ll
+++ b/llvm/test/CodeGen/Mips/brconeqz.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 5, align 4
@result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brconge.ll b/llvm/test/CodeGen/Mips/brconge.ll
index 38e3a7c3706f54..44d7556b5577b0 100644
--- a/llvm/test/CodeGen/Mips/brconge.ll
+++ b/llvm/test/CodeGen/Mips/brconge.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
@i = global i32 5, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brcongt.ll b/llvm/test/CodeGen/Mips/brcongt.ll
index 3231811588fc14..c332820a83a8c2 100644
--- a/llvm/test/CodeGen/Mips/brcongt.ll
+++ b/llvm/test/CodeGen/Mips/brcongt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 5, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconle.ll b/llvm/test/CodeGen/Mips/brconle.ll
index e0ade5df237753..e695f4be18f1fb 100644
--- a/llvm/test/CodeGen/Mips/brconle.ll
+++ b/llvm/test/CodeGen/Mips/brconle.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O2 < %s | FileCheck %s -check-prefix=16
@i = global i32 -5, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconlt.ll b/llvm/test/CodeGen/Mips/brconlt.ll
index f3dbb9607eaffb..6ae8c64b4f09c5 100644
--- a/llvm/test/CodeGen/Mips/brconlt.ll
+++ b/llvm/test/CodeGen/Mips/brconlt.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
@i = global i32 5, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/brconne.ll b/llvm/test/CodeGen/Mips/brconne.ll
index 5c3a0ef3432914..40a15cdefba730 100644
--- a/llvm/test/CodeGen/Mips/brconne.ll
+++ b/llvm/test/CodeGen/Mips/brconne.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 5, align 4
@j = global i32 5, align 4
diff --git a/llvm/test/CodeGen/Mips/brconnek.ll b/llvm/test/CodeGen/Mips/brconnek.ll
index 30c32825da52e4..3b74c777e0c2e3 100644
--- a/llvm/test/CodeGen/Mips/brconnek.ll
+++ b/llvm/test/CodeGen/Mips/brconnek.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@j = global i32 5, align 4
@result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brconnez.ll b/llvm/test/CodeGen/Mips/brconnez.ll
index 5f8b54e9cbb50d..e153964fab40aa 100644
--- a/llvm/test/CodeGen/Mips/brconnez.ll
+++ b/llvm/test/CodeGen/Mips/brconnez.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@j = global i32 0, align 4
@result = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/brind.ll b/llvm/test/CodeGen/Mips/brind.ll
index 8f2954fd2b25e9..1cc7fdd6bef86d 100644
--- a/llvm/test/CodeGen/Mips/brind.ll
+++ b/llvm/test/CodeGen/Mips/brind.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@main.L = internal unnamed_addr constant [5 x ptr] [ptr blockaddress(@main, %L1), ptr blockaddress(@main, %L2), ptr blockaddress(@main, %L3), ptr blockaddress(@main, %L4), ptr null], align 4
@str = private unnamed_addr constant [2 x i8] c"A\00"
diff --git a/llvm/test/CodeGen/Mips/brundef.ll b/llvm/test/CodeGen/Mips/brundef.ll
index d63b587af03955..b353862c6eddcb 100644
--- a/llvm/test/CodeGen/Mips/brundef.ll
+++ b/llvm/test/CodeGen/Mips/brundef.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -o /dev/null < %s
+; RUN: llc -mtriple=mips -mcpu=mips32 -verify-machineinstrs -o /dev/null < %s
; Confirm that MachineInstr branch simplification preserves
; register operand flags, such as the <undef> flag.
diff --git a/llvm/test/CodeGen/Mips/bswap.ll b/llvm/test/CodeGen/Mips/bswap.ll
index ace6c3d6021d2d..fa8cda330ba3a5 100644
--- a/llvm/test/CodeGen/Mips/bswap.ll
+++ b/llvm/test/CodeGen/Mips/bswap.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 \
; RUN: | FileCheck %s -check-prefix=MIPS32
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: | FileCheck %s -check-prefix=MM
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 \
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 \
; RUN: | FileCheck %s -check-prefix=MIPS64
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+mips16 \
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+mips16 \
; RUN: | FileCheck %s -check-prefix=MIPS16
define i32 @bswap32(i32 signext %x) nounwind readnone {
diff --git a/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll b/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
index 95b9ca8caf0296..1c1323b10f0af4 100644
--- a/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
+++ b/llvm/test/CodeGen/Mips/buildpairextractelementf64.ll
@@ -1,9 +1,9 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL
-; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL
-; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL
+; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL
@a = external global i32
diff --git a/llvm/test/CodeGen/Mips/call-optimization.ll b/llvm/test/CodeGen/Mips/call-optimization.ll
index 89fb970ed81784..e48c2911501980 100644
--- a/llvm/test/CodeGen/Mips/call-optimization.ll
+++ b/llvm/test/CodeGen/Mips/call-optimization.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefix=O32
-; RUN: llc -march=mipsel -mips-load-target-from-got=false \
+; RUN: llc -mtriple=mipsel -mips-load-target-from-got=false \
; RUN: -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-LOADTGT
@gd1 = common global double 0.000000e+00, align 8
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll b/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
index f2355049adfaad..533f8b6426bcd8 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB
-; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL
-; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB
-; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL
+; RUN: llc < %s -mtriple=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB
+; RUN: llc < %s -mtriple=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL
+; RUN: llc < %s -mtriple=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB
+; RUN: llc < %s -mtriple=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL
; #include <stdio.h>
;
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
index 0619ebe48cfe64..6f94dce7f8a63a 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-byte.ll
@@ -1,4 +1,4 @@
-; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc --mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s
; Generated from the C program:
;
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
index db066c04751427..485aab499189e8 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-combinations.ll
@@ -1,4 +1,4 @@
-; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc --mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s
; Generated from the C program:
;
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
index 3bddbf9d450abe..0193a90d6e9c14 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs-small-structs-multiple-args.ll
@@ -1,4 +1,4 @@
-; RUN: llc --march=mips64 -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc --mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s
; Generated from the C program:
;
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
index 1a604e7b5e89e5..741d5e3645ca26 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
@@ -1,12 +1,12 @@
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
+; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
+; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
-; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
-; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
-; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
-; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
+; RUN-TODO: llc -mtriple=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN-TODO: llc -mtriple=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN-TODO: llc -mtriple=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
+; RUN-TODO: llc -mtriple=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
define void @fpu_clobber() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
index 1c2f9e2be34117..e4f5564910c321 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx1.ll
@@ -1,13 +1,13 @@
-; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s \
+; RUN: llc -mtriple=mips -mattr=+o32,+fp64,+mips32r2 < %s \
; RUN: | FileCheck --check-prefix=O32-FP64-INV %s
-; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s \
+; RUN: llc -mtriple=mipsel -mattr=+o32,+fp64,+mips32r2 < %s \
; RUN: | FileCheck --check-prefix=O32-FP64-INV %s
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
+; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
+; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
-; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
-; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
+; RUN-TODO: llc -mtriple=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
+; RUN-TODO: llc -mtriple=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=O32-FPXX %s
define void @fpu_clobber() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved.ll
index 8cfd1397ed974a..93808fbcad03d1 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved.ll
@@ -1,33 +1,33 @@
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s \
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s \
; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s \
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s \
; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s \
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s \
; RUN-TODO: | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s \
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s \
; RUN-TODO: | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN: llc -march=mips64 -target-abi n32 < %s \
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi n32 < %s \
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -target-abi n32 < %s \
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N32-INV %s
-; RUN: llc -march=mips64el -target-abi n32 < %s \
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N32-INV %s
-; RUN: llc -march=mips64 -target-abi n64 < %s \
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -target-abi n64 < %s \
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64 -target-abi n64 < %s \
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N64-INV %s
-; RUN: llc -march=mips64el -target-abi n64 < %s \
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N64-INV %s
; Test the callee-saved registers are callee-saved as specified by section
diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
index dae4bfc2260901..42f9d1890cc37c 100644
--- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
+++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
@@ -1,14 +1,14 @@
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
; Test the memory layout for all ABI's and byte orders as specified by section
; 4 of MD00305 (MIPS ABIs Described).
diff --git a/llvm/test/CodeGen/Mips/cconv/pr33883.ll b/llvm/test/CodeGen/Mips/cconv/pr33883.ll
index 54d7286ab8ffff..9fecf09ef3c278 100644
--- a/llvm/test/CodeGen/Mips/cconv/pr33883.ll
+++ b/llvm/test/CodeGen/Mips/cconv/pr33883.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=mips32 < %s -o /dev/null
+; RUN: llc -mtriple=mips -mcpu=mips32 < %s -o /dev/null
; Test that calls to vector intrinsics do not crash SelectionDAGBuilder.
diff --git a/llvm/test/CodeGen/Mips/cconv/reserved-space.ll b/llvm/test/CodeGen/Mips/cconv/reserved-space.ll
index 0a922345ddf3c6..490476961626eb 100644
--- a/llvm/test/CodeGen/Mips/cconv/reserved-space.ll
+++ b/llvm/test/CodeGen/Mips/cconv/reserved-space.ll
@@ -1,14 +1,14 @@
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
; Test that O32 correctly reserved space for the four arguments, even when
; there aren't any as per section 5 of MD00305 (MIPS ABIs Described).
diff --git a/llvm/test/CodeGen/Mips/cconv/roundl-call.ll b/llvm/test/CodeGen/Mips/cconv/roundl-call.ll
index 242b4292e5283f..98bda89546e438 100644
--- a/llvm/test/CodeGen/Mips/cconv/roundl-call.ll
+++ b/llvm/test/CodeGen/Mips/cconv/roundl-call.ll
@@ -1,22 +1,22 @@
-; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \
; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \
; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT
-; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \
; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT
-; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT
-; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \
; RUN: -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,N64,SOFT-FLOAT
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \
; RUN: %s -relocation-model=pic | FileCheck %s \
; RUN: -check-prefixes=ALL,N64,SOFT-FLOAT
diff --git a/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll b/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
index c957e311b1b3a6..9cdb8428b484a5 100644
--- a/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
+++ b/llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
@@ -1,14 +1,14 @@
-; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
+; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
+; RUN: llc -mtriple=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
; Test the stack alignment for all ABI's and byte orders as specified by
; section 5 of MD00305 (MIPS ABIs Described).
diff --git a/llvm/test/CodeGen/Mips/cfi_offset.ll b/llvm/test/CodeGen/Mips/cfi_offset.ll
index 217adda59468a9..f6872125588436 100644
--- a/llvm/test/CodeGen/Mips/cfi_offset.ll
+++ b/llvm/test/CodeGen/Mips/cfi_offset.ll
@@ -1,9 +1,9 @@
-; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
-; RUN: llc -march=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
-; RUN: llc -march=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -mtriple=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -mtriple=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -mtriple=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -mtriple=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
+; RUN: llc -mtriple=mips -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB
+; RUN: llc -mtriple=mipsel -mattr=+o32,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL
@var = global double 0.0
diff --git a/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll b/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll
index cf0fda66ad6260..f22848c1c45cca 100644
--- a/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll
+++ b/llvm/test/CodeGen/Mips/check-adde-redundant-moves.ll
@@ -1,16 +1,16 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL
define i64 @add_i64(i64 %a) {
; GP32-LABEL: add_i64
diff --git a/llvm/test/CodeGen/Mips/check-noat.ll b/llvm/test/CodeGen/Mips/check-noat.ll
index cfcd367e87af23..1e53eda4d63faa 100644
--- a/llvm/test/CodeGen/Mips/check-noat.ll
+++ b/llvm/test/CodeGen/Mips/check-noat.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
define void @f() nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/cins.ll b/llvm/test/CodeGen/Mips/cins.ll
index 4fe25564d1c12d..39d80e3bb36ab8 100644
--- a/llvm/test/CodeGen/Mips/cins.ll
+++ b/llvm/test/CodeGen/Mips/cins.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s
+; RUN: llc -mtriple=mips64 -mcpu=octeon -target-abi=n64 < %s -o - | FileCheck %s
define i64 @cins_zext(i32 signext %n) {
entry:
diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll
index d19c1b1f14c36c..bb3c7c27a122d8 100644
--- a/llvm/test/CodeGen/Mips/cmov.ll
+++ b/llvm/test/CodeGen/Mips/cmov.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
-; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
-; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
-; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP
-; RUN: llc -march=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV
-; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV
-; RUN: llc -march=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP
+; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
+; RUN: llc -mtriple=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global ptr null, align 4
diff --git a/llvm/test/CodeGen/Mips/cmplarge.ll b/llvm/test/CodeGen/Mips/cmplarge.ll
index a64983dfed0233..db7f37a88ac22c 100644
--- a/llvm/test/CodeGen/Mips/cmplarge.ll
+++ b/llvm/test/CodeGen/Mips/cmplarge.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
target triple = "mipsel--linux-gnu"
diff --git a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
index bfdd5cfd8b53d4..de7286611f954b 100644
--- a/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
+++ b/llvm/test/CodeGen/Mips/coalesce-partial-redundant-reguse-terminator.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -o - %s -run-pass=register-coalescer -verify-coalescing | FileCheck %s
+# RUN: llc -mtriple=mips64 -o - %s -run-pass=register-coalescer -verify-coalescing | FileCheck %s
---
name: f
diff --git a/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll b/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
index 13e30676aa6fbc..b0eeadfecf6ed7 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s
-; RUN: llc -march=mips64 -mcpu=mips64r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -O1 -start-after=dwarf-eh-prepare < %s | FileCheck %s
; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
index 33e43ad06f1246..dfaad3a01bb751 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s
+# RUN: llc -mtriple=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s
# Check that MipsHazardSchedule sees through basic blocks with transient instructions.
# The mir code in this file isn't representative of the llvm-ir.
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll
index c819bf59ace6bb..5a206f2d8891df 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll
@@ -1,7 +1,7 @@
; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured.
-; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER
-; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL
-; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS
define i32 @l(i32 signext %a, i32 signext %b) {
entry:
diff --git a/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll b/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
index 1ba80bff8d5af3..a808bec149eae1 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/compact-branches-64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -relocation-model=pic -march=mipsel -mcpu=mips64r6 \
+; RUN: llc -relocation-model=pic -mtriple=mipsel -mcpu=mips64r6 \
; RUN: -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
; Function Attrs: nounwind
diff --git a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
index a2caf5b67aab3e..41f59f535a4c95 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
+++ b/llvm/test/CodeGen/Mips/compactbranches/empty-block.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s
+# RUN: llc -mtriple=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s
# Check that empty blocks in the cfg don't cause the mips hazard scheduler to
# crash and that the nop is inserted correctly.
diff --git a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
index de61515cff9bcb..99efc5e8e4411e 100644
--- a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
+++ b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s
-; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -O0 -mcpu=mips64r6 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64 -O0 -mcpu=mips64r6 < %s | FileCheck %s
@boo = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/constantfp0.ll b/llvm/test/CodeGen/Mips/constantfp0.ll
index 191f31d0131914..dd0ddca036c31f 100644
--- a/llvm/test/CodeGen/Mips/constantfp0.ll
+++ b/llvm/test/CodeGen/Mips/constantfp0.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
define i32 @branch(double %d) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/constraint-c-err.ll b/llvm/test/CodeGen/Mips/constraint-c-err.ll
index 94768f89e9924c..43229d1d38d9f6 100644
--- a/llvm/test/CodeGen/Mips/constraint-c-err.ll
+++ b/llvm/test/CodeGen/Mips/constraint-c-err.ll
@@ -1,5 +1,5 @@
; Check that invalid type for constraint `c` causes an error message.
-; RUN: not llc -march=mips -target-abi o32 < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=mips -target-abi o32 < %s 2>&1 | FileCheck %s
define i32 @main() #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/constraint-c.ll b/llvm/test/CodeGen/Mips/constraint-c.ll
index 31b75b01a5e852..85eda164a1a619 100644
--- a/llvm/test/CodeGen/Mips/constraint-c.ll
+++ b/llvm/test/CodeGen/Mips/constraint-c.ll
@@ -1,5 +1,5 @@
; Check handling of the constraint `c`.
-; RUN: llc -march=mips -target-abi o32 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -target-abi o32 < %s | FileCheck %s
define i32 @main() #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/constraint-empty.ll b/llvm/test/CodeGen/Mips/constraint-empty.ll
index 8541a4fa348e66..ff2b9b8408525f 100644
--- a/llvm/test/CodeGen/Mips/constraint-empty.ll
+++ b/llvm/test/CodeGen/Mips/constraint-empty.ll
@@ -1,5 +1,5 @@
; Check that `getRegForInlineAsmConstraint` does not crash on empty Constraint.
-; RUN: llc -march=mips64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64 < %s | FileCheck %s
define void @foo() {
entry:
diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll
index 264d0486e3b87b..9c512bd3ad383a 100644
--- a/llvm/test/CodeGen/Mips/countleading.ll
+++ b/llvm/test/CodeGen/Mips/countleading.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s
-; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R6 %s
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=MIPS4 %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R6 %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=MIPS4 %s
; Prefixes:
; ALL - All
diff --git a/llvm/test/CodeGen/Mips/cprestore.ll b/llvm/test/CodeGen/Mips/cprestore.ll
index bb27c947d998eb..2bd7591e38abe3 100644
--- a/llvm/test/CodeGen/Mips/cprestore.ll
+++ b/llvm/test/CodeGen/Mips/cprestore.ll
@@ -1,4 +1,4 @@
-; DISABLE: llc -march=mipsel < %s | FileCheck %s
+; DISABLE: llc -mtriple=mipsel < %s | FileCheck %s
; RUN: false
; XFAIL: *
diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll b/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll
index f34c70efa7a800..6a5f65a96095e1 100644
--- a/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll
+++ b/llvm/test/CodeGen/Mips/cstmaterialization/constMaterialization.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=ALL,MIPS
-; RUN: llc -march=mips < %s -mattr=+micromips | FileCheck %s -check-prefixes=ALL,MM
+; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefixes=ALL,MIPS
+; RUN: llc -mtriple=mips < %s -mattr=+micromips | FileCheck %s -check-prefixes=ALL,MM
; Test the patterns used for constant materialization.
diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
index b29115a4f7827f..dc8efae68fda1e 100644
--- a/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
+++ b/llvm/test/CodeGen/Mips/cstmaterialization/isel-materialization.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
; REQUIRES: asserts
diff --git a/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll b/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll
index 78c01d9b7473e4..0e9075aa16880c 100644
--- a/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll
+++ b/llvm/test/CodeGen/Mips/cstmaterialization/stack.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32
-; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
-; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \
+; RUN: llc -mtriple=mipsel -mcpu=mips64 -target-abi n32 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-MIPSN32
; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate
diff --git a/llvm/test/CodeGen/Mips/ctlz-v.ll b/llvm/test/CodeGen/Mips/ctlz-v.ll
index 156c640681b751..280054dac082a1 100644
--- a/llvm/test/CodeGen/Mips/ctlz-v.ll
+++ b/llvm/test/CodeGen/Mips/ctlz-v.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
diff --git a/llvm/test/CodeGen/Mips/cttz-v.ll b/llvm/test/CodeGen/Mips/cttz-v.ll
index dbcde7f5fe5b8e..347466086a68ac 100644
--- a/llvm/test/CodeGen/Mips/cttz-v.ll
+++ b/llvm/test/CodeGen/Mips/cttz-v.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
diff --git a/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll b/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll
index 8c2ac7a7f2ce32..c2376a7b56dfbb 100644
--- a/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll
+++ b/llvm/test/CodeGen/Mips/dagcombine-store-gep-chain-slow.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -o /dev/null
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -o /dev/null
; Test that this file is compiled in a reasonable time period. Without the
; optimization level check in findBetterNeighbors, this test demonstrates
diff --git a/llvm/test/CodeGen/Mips/delay-slot-kill.ll b/llvm/test/CodeGen/Mips/delay-slot-kill.ll
index 57b630303c264f..9d51d72721e948 100644
--- a/llvm/test/CodeGen/Mips/delay-slot-kill.ll
+++ b/llvm/test/CodeGen/Mips/delay-slot-kill.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s
; Currently, the following IR assembly generates a KILL instruction between
; the bitwise-and instruction and the return instruction. We verify that the
diff --git a/llvm/test/CodeGen/Mips/dext.ll b/llvm/test/CodeGen/Mips/dext.ll
index 1794f16b2cd70c..b27d67c7da6a1e 100644
--- a/llvm/test/CodeGen/Mips/dext.ll
+++ b/llvm/test/CodeGen/Mips/dext.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=n64 < %s -o - | FileCheck %s
define i64 @dext_add_zext(i32 signext %n) {
entry:
diff --git a/llvm/test/CodeGen/Mips/dins.ll b/llvm/test/CodeGen/Mips/dins.ll
index 4deb7455a80128..aecc06bc7203ae 100644
--- a/llvm/test/CodeGen/Mips/dins.ll
+++ b/llvm/test/CodeGen/Mips/dins.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64 -mcpu=mips64r2 \
; RUN: -target-abi=n64 < %s -o - | FileCheck %s -check-prefix=MIPS64R2
-; RUN: llc -O2 -verify-machineinstrs -march=mips -mcpu=mips32r2 < %s -o - \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips -mcpu=mips32r2 < %s -o - \
; RUN: | FileCheck %s -check-prefix=MIPS32R2
-; RUN: llc -O2 -verify-machineinstrs -march=mips -mattr=mips16 < %s -o - \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips -mattr=mips16 < %s -o - \
; RUN: | FileCheck %s -check-prefix=MIPS16
-; RUN: llc -O2 -verify-machineinstrs -march=mips64 -mcpu=mips64r2 \
+; RUN: llc -O2 -verify-machineinstrs -mtriple=mips64 -mcpu=mips64r2 \
; RUN: -target-abi=n32 < %s -o - | FileCheck %s -check-prefix=MIPS64R2N32
; #include <stdint.h>
diff --git a/llvm/test/CodeGen/Mips/disable-tail-merge.ll b/llvm/test/CodeGen/Mips/disable-tail-merge.ll
index 188b83b68f5d3d..8e6174c4b3c483 100644
--- a/llvm/test/CodeGen/Mips/disable-tail-merge.ll
+++ b/llvm/test/CodeGen/Mips/disable-tail-merge.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/div.ll b/llvm/test/CodeGen/Mips/div.ll
index 839b2dee6d09ea..0dd3bb47049a1f 100644
--- a/llvm/test/CodeGen/Mips/div.ll
+++ b/llvm/test/CodeGen/Mips/div.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 100, align 4
@jjjj = global i32 -4, align 4
diff --git a/llvm/test/CodeGen/Mips/div_rem.ll b/llvm/test/CodeGen/Mips/div_rem.ll
index c8e22f262fb28a..7485ca2df5e856 100644
--- a/llvm/test/CodeGen/Mips/div_rem.ll
+++ b/llvm/test/CodeGen/Mips/div_rem.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 103, align 4
@jjjj = global i32 -4, align 4
diff --git a/llvm/test/CodeGen/Mips/divrem.ll b/llvm/test/CodeGen/Mips/divrem.ll
index b0dd49a0622174..a29f2793c081fe 100644
--- a/llvm/test/CodeGen/Mips/divrem.ll
+++ b/llvm/test/CodeGen/Mips/divrem.ll
@@ -1,16 +1,16 @@
-; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP
-; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP
-; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP
-; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
-; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
-; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP
-
-; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK
-; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK
-; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK
-; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
-; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
+; RUN: llc -mtriple=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP
+
+; RUN: llc -mtriple=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
; FileCheck Prefixes:
; ALL - All targets
diff --git a/llvm/test/CodeGen/Mips/divu.ll b/llvm/test/CodeGen/Mips/divu.ll
index caa49fd472b370..10348001dd4bcd 100644
--- a/llvm/test/CodeGen/Mips/divu.ll
+++ b/llvm/test/CodeGen/Mips/divu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 100, align 4
@jjjj = global i32 4, align 4
diff --git a/llvm/test/CodeGen/Mips/divu_remu.ll b/llvm/test/CodeGen/Mips/divu_remu.ll
index 820633be119bed..7a435e922f1abb 100644
--- a/llvm/test/CodeGen/Mips/divu_remu.ll
+++ b/llvm/test/CodeGen/Mips/divu_remu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 103, align 4
@jjjj = global i32 4, align 4
diff --git a/llvm/test/CodeGen/Mips/double2int.ll b/llvm/test/CodeGen/Mips/double2int.ll
index f0d8ad28100f65..a5ca8b9f46aab1 100644
--- a/llvm/test/CodeGen/Mips/double2int.ll
+++ b/llvm/test/CodeGen/Mips/double2int.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s
define i32 @f1(double %d) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
index a5fe34c1f684fc..9444fdf32ebd20 100644
--- a/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
+++ b/llvm/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=dsp < %s | FileCheck %s
; CHECK-LABEL: select_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
diff --git a/llvm/test/CodeGen/Mips/dsp-patterns.ll b/llvm/test/CodeGen/Mips/dsp-patterns.ll
index ba6c4d972c56de..0f044f968bdb1d 100644
--- a/llvm/test/CodeGen/Mips/dsp-patterns.ll
+++ b/llvm/test/CodeGen/Mips/dsp-patterns.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=R1
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=R1
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
; R1-LABEL: test_lbux:
; R1: lbux ${{[0-9]+}}
diff --git a/llvm/test/CodeGen/Mips/dsp-r1.ll b/llvm/test/CodeGen/Mips/dsp-r1.ll
index 0ec23b9d7fd770..2b5a0d25aed7f1 100644
--- a/llvm/test/CodeGen/Mips/dsp-r1.ll
+++ b/llvm/test/CodeGen/Mips/dsp-r1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
; RUN: FileCheck %s
define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
diff --git a/llvm/test/CodeGen/Mips/dsp-r2.ll b/llvm/test/CodeGen/Mips/dsp-r2.ll
index 631f9e43c23ac3..584455cf0c5227 100644
--- a/llvm/test/CodeGen/Mips/dsp-r2.ll
+++ b/llvm/test/CodeGen/Mips/dsp-r2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=+dspr2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+dspr2 < %s | FileCheck %s
define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll b/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll
index 2feefcc09879a2..b1d1f9703fc491 100644
--- a/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll
+++ b/llvm/test/CodeGen/Mips/dsp-vec-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=+dsp < %s
+; RUN: llc -mtriple=mipsel -mattr=+dsp < %s
@g1 = common global <2 x i8> zeroinitializer, align 2
@g0 = common global <2 x i8> zeroinitializer, align 2
diff --git a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
index c201c34f96861f..daa0f79af4c358 100644
--- a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
+++ b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
@@ -1,24 +1,24 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP32,GP32-M
-; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP32,GP32-M
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP32,GP32-M
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP32,GP32-MM,GP32-MMR2
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP32,GP32-MM,GP32-MMR6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP64,N64
-; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP64,N64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP64,N64
-; RUN: llc < %s -march=mips64 -mcpu=mips3 -target-abi n32 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -target-abi n32 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP64,N32
-; RUN: llc < %s -march=mips64 -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP64,N32
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -target-abi n32 -relocation-model=pic | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -target-abi n32 -relocation-model=pic | FileCheck %s \
; RUN: --check-prefixes=ALL,GP64,N32
; Check dynamic stack realignment in functions without variable-sized objects.
diff --git a/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll b/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll
index 2377707b8f7283..ce96605572ce5f 100644
--- a/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll
+++ b/llvm/test/CodeGen/Mips/eh-dwarf-cfa.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | \
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | \
; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
declare ptr @llvm.eh.dwarf.cfa(i32) nounwind
diff --git a/llvm/test/CodeGen/Mips/eh-return32.ll b/llvm/test/CodeGen/Mips/eh-return32.ll
index 983fc6f7788c78..50c8b1dca9901f 100644
--- a/llvm/test/CodeGen/Mips/eh-return32.ll
+++ b/llvm/test/CodeGen/Mips/eh-return32.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
declare void @llvm.eh.return.i32(i32, ptr)
declare void @foo(...)
diff --git a/llvm/test/CodeGen/Mips/eh-return64.ll b/llvm/test/CodeGen/Mips/eh-return64.ll
index 9ae2f00d46c1e9..3a2fb2a4868d88 100644
--- a/llvm/test/CodeGen/Mips/eh-return64.ll
+++ b/llvm/test/CodeGen/Mips/eh-return64.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
-; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6
declare void @llvm.eh.return.i64(i64, ptr)
declare void @foo(...)
diff --git a/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
index b1045a08dd3a68..3379322f0bf770 100644
--- a/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
+++ b/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
; Check that register scavenging spill slot is close to $fp.
target triple="mipsel--"
diff --git a/llvm/test/CodeGen/Mips/emit-big-cst.ll b/llvm/test/CodeGen/Mips/emit-big-cst.ll
index cd0666cfd3fc24..5a8852e38e3dfd 100644
--- a/llvm/test/CodeGen/Mips/emit-big-cst.ll
+++ b/llvm/test/CodeGen/Mips/emit-big-cst.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=BE
-; RUN: llc -march=mipsel < %s | FileCheck %s --check-prefix=LE
+; RUN: llc -mtriple=mips < %s | FileCheck %s --check-prefix=BE
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s --check-prefix=LE
; Check assembly printing of odd constants.
; BE-LABEL: bigCst:
diff --git a/llvm/test/CodeGen/Mips/ex2.ll b/llvm/test/CodeGen/Mips/ex2.ll
index 79aabfcbbfc437..bdc676713ad7bd 100644
--- a/llvm/test/CodeGen/Mips/ex2.ll
+++ b/llvm/test/CodeGen/Mips/ex2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
@_ZTIPKc = external constant ptr
diff --git a/llvm/test/CodeGen/Mips/extins.ll b/llvm/test/CodeGen/Mips/extins.ll
index 9989c3c00dc79d..e5c66602450e8f 100644
--- a/llvm/test/CodeGen/Mips/extins.ll
+++ b/llvm/test/CodeGen/Mips/extins.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
-; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=16
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2
+; RUN: llc < %s -mtriple=mips -mattr=mips16 | FileCheck %s -check-prefix=16
define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/fastcc.ll b/llvm/test/CodeGen/Mips/fastcc.ll
index ccdeedce6d235c..e6d12664d83f4e 100644
--- a/llvm/test/CodeGen/Mips/fastcc.ll
+++ b/llvm/test/CodeGen/Mips/fastcc.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=mipsel -relocation-model=pic | FileCheck %s
; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu -relocation-model=pic -mips-tail-calls=1\
; RUN: | FileCheck %s -check-prefix=CHECK-NACL
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic -mips-tail-calls=1| FileCheck %s -check-prefix=NOODDSPREG
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic -mips-tail-calls=1 | FileCheck %s -check-prefix=FP64-NOODDSPREG
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic -mips-tail-calls=1| FileCheck %s -check-prefix=NOODDSPREG
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic -mips-tail-calls=1 | FileCheck %s -check-prefix=FP64-NOODDSPREG
@gi0 = external global i32
diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index 34088beb2246da..c0b34454d62062 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -1,20 +1,20 @@
-; RUN: llc < %s -march=mips -mcpu=mips32 | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | \
; RUN: FileCheck %s -check-prefixes=ALL,32-C
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | \
; RUN: FileCheck %s -check-prefixes=ALL,32-C
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | \
; RUN: FileCheck %s -check-prefixes=ALL,32-CMP
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \
; RUN: FileCheck %s -check-prefixes=ALL,64-C
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \
; RUN: FileCheck %s -check-prefixes=ALL,64-C
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \
; RUN: FileCheck %s -check-prefixes=ALL,64-C
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \
; RUN: FileCheck %s -check-prefixes=ALL,64-CMP
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32R3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6
define i32 @false_f32(float %a, float %b) nounwind {
diff --git a/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll b/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
index 695431a5ab6074..ed6b2e08a9b935 100644
--- a/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
+++ b/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips4 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips4 \
; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64
-; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64 \
; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64
-; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64r2 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64r2 \
; RUN: -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2
declare double @copysign(double, double) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/fcopysign.ll b/llvm/test/CodeGen/Mips/fcopysign.ll
index 810d0f9580861c..7ef9d6376e6dcf 100644
--- a/llvm/test/CodeGen/Mips/fcopysign.ll
+++ b/llvm/test/CodeGen/Mips/fcopysign.ll
@@ -1,12 +1,12 @@
-; RUN: llc < %s -verify-machineinstrs -march=mipsel -mcpu=mips32 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mipsel -mcpu=mips32 \
; RUN: | FileCheck %s -check-prefix=32
-; RUN: llc < %s -verify-machineinstrs -march=mipsel -mcpu=mips32r2 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mipsel -mcpu=mips32r2 \
; RUN: | FileCheck %s -check-prefix=32R2
-; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips4 -target-abi=n64 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips4 -target-abi=n64 \
; RUN: | FileCheck %s -check-prefix=64
-; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64 -target-abi=n64 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64 -target-abi=n64 \
; RUN: | FileCheck %s -check-prefix=64
-; RUN: llc < %s -verify-machineinstrs -march=mips64el -mcpu=mips64r2 -target-abi=n64 \
+; RUN: llc < %s -verify-machineinstrs -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 \
; RUN: | FileCheck %s -check-prefix=64R2
define double @func0(double %d0, double %d1) nounwind readnone {
diff --git a/llvm/test/CodeGen/Mips/fmadd1.ll b/llvm/test/CodeGen/Mips/fmadd1.ll
index 4704387bf289bf..b9380c45ca7862 100644
--- a/llvm/test/CodeGen/Mips/fmadd1.ll
+++ b/llvm/test/CodeGen/Mips/fmadd1.ll
@@ -5,29 +5,29 @@
; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
; available when -enable-no-nans-fp-math is given.
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
-; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
; when +nomadd attribute is specified.
; Output for mips32 and mips64r6 reused since aforementioned instructions are
; not generated in those cases.
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/fp-contract.ll b/llvm/test/CodeGen/Mips/fp-contract.ll
index f25e9f5258c770..c43d2a644bb368 100644
--- a/llvm/test/CodeGen/Mips/fp-contract.ll
+++ b/llvm/test/CodeGen/Mips/fp-contract.ll
@@ -1,11 +1,11 @@
; Test that the compiled does not fuse fmul and fadd into fmadd when no -fp-contract=fast
; option is set (the same applies for fmul, fsub and fmsub).
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -fp-contract=off < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -fp-contract=fast < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK-CONTRACT-FAST
declare <4 x float> @llvm.mips.fmul.w(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/Mips/fp-indexed-ls.ll b/llvm/test/CodeGen/Mips/fp-indexed-ls.ll
index 48052b6e861434..8e20c8229847c9 100644
--- a/llvm/test/CodeGen/Mips/fp-indexed-ls.ll
+++ b/llvm/test/CodeGen/Mips/fp-indexed-ls.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1
-; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2
-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6
-; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
-; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6
; Check that [ls][dwu]xc1 are not emitted for nacl.
; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
diff --git a/llvm/test/CodeGen/Mips/fp-spill-reload.ll b/llvm/test/CodeGen/Mips/fp-spill-reload.ll
index 21a7ed040f0fd3..8a01ec87326411 100644
--- a/llvm/test/CodeGen/Mips/fp-spill-reload.ll
+++ b/llvm/test/CodeGen/Mips/fp-spill-reload.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
; check that $fp is not reserved.
define void @foo0(ptr nocapture %b) nounwind {
diff --git a/llvm/test/CodeGen/Mips/fp64a.ll b/llvm/test/CodeGen/Mips/fp64a.ll
index 317afd7003bba4..392a4f6e4a2df6 100644
--- a/llvm/test/CodeGen/Mips/fp64a.ll
+++ b/llvm/test/CodeGen/Mips/fp64a.ll
@@ -7,16 +7,16 @@
; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit
; FPU) on a 32-bit architecture was added in MIPS32r2.
-; RUN: not llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
-
-; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A
-; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
-; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A
-; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
+; RUN: not llc -mtriple=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A
+
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A
+; RUN: not llc -mtriple=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A
+; RUN: not llc -mtriple=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A
; 32R1-FP64: LLVM ERROR: FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater.
; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI.
diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll
index 251c5392575b2d..9f7baca881fc07 100644
--- a/llvm/test/CodeGen/Mips/fpbr.ll
+++ b/llvm/test/CodeGen/Mips/fpbr.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
-; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
define void @func0(float %f2, float %f3) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/fpxx.ll b/llvm/test/CodeGen/Mips/fpxx.ll
index 6fdb95efe8ecf4..a12aa740635652 100644
--- a/llvm/test/CodeGen/Mips/fpxx.ll
+++ b/llvm/test/CodeGen/Mips/fpxx.ll
@@ -1,20 +1,20 @@
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX
-; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX
-; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX
-; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX
+; RUN: llc -mtriple=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX
+; RUN: not llc -mtriple=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX
-; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX
-; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX
+; RUN: llc -mtriple=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX
+; RUN: not llc -mtriple=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX
-; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX
-; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX
+; RUN-TODO: llc -mtriple=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX
+; RUN-TODO: llc -mtriple=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX
-; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,64-O32-NOFPXX
-; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,64-O32-FPXX
+; RUN-TODO: llc -mtriple=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,64-O32-NOFPXX
+; RUN-TODO: llc -mtriple=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,64-O32-FPXX
declare double @dbl();
diff --git a/llvm/test/CodeGen/Mips/frame-address-err.ll b/llvm/test/CodeGen/Mips/frame-address-err.ll
index 45f20ac8119c0d..9b75d3c66e27e4 100644
--- a/llvm/test/CodeGen/Mips/frame-address-err.ll
+++ b/llvm/test/CodeGen/Mips/frame-address-err.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=mips < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=mips < %s 2>&1 | FileCheck %s
declare ptr @llvm.frameaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/frame-address.ll b/llvm/test/CodeGen/Mips/frame-address.ll
index 685d1fe1f46512..7e92e3e7de6da9 100644
--- a/llvm/test/CodeGen/Mips/frame-address.ll
+++ b/llvm/test/CodeGen/Mips/frame-address.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
declare ptr @llvm.frameaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/frem.ll b/llvm/test/CodeGen/Mips/frem.ll
index be222b2d9172a0..556ca6c2e7e7a3 100644
--- a/llvm/test/CodeGen/Mips/frem.ll
+++ b/llvm/test/CodeGen/Mips/frem.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mipsel
+; RUN: llc < %s -mtriple=mipsel
define float @fmods(float %x, float %y) {
entry:
diff --git a/llvm/test/CodeGen/Mips/global-pointer-reg.ll b/llvm/test/CodeGen/Mips/global-pointer-reg.ll
index 3cb2aaed476696..a616fa3ec2fa4f 100644
--- a/llvm/test/CodeGen/Mips/global-pointer-reg.ll
+++ b/llvm/test/CodeGen/Mips/global-pointer-reg.ll
@@ -1,4 +1,4 @@
-; DISABLED: llc < %s -march=mipsel -mips-fix-global-base-reg=false | FileCheck %s
+; DISABLED: llc < %s -mtriple=mipsel -mips-fix-global-base-reg=false | FileCheck %s
; RUN: false
; XFAIL: *
diff --git a/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll b/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll
index 35cebdf302b5da..ae6627a8c768c1 100644
--- a/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll
+++ b/llvm/test/CodeGen/Mips/gpreg-lazy-binding.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -disable-mips-delay-filler -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s
@g = external global i32
diff --git a/llvm/test/CodeGen/Mips/hf16_1.ll b/llvm/test/CodeGen/Mips/hf16_1.ll
index 327f04f6485982..611e53f4fd2f69 100644
--- a/llvm/test/CodeGen/Mips/hf16_1.ll
+++ b/llvm/test/CodeGen/Mips/hf16_1.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=1
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=2
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=1
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=2
@x = common global float 0.000000e+00, align 4
diff --git a/llvm/test/CodeGen/Mips/i64arg.ll b/llvm/test/CodeGen/Mips/i64arg.ll
index ec26cdc6776c3f..2af16f7d23f3c1 100644
--- a/llvm/test/CodeGen/Mips/i64arg.ll
+++ b/llvm/test/CodeGen/Mips/i64arg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s
define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/imm.ll b/llvm/test/CodeGen/Mips/imm.ll
index eea391e8707e64..bf62df69928240 100644
--- a/llvm/test/CodeGen/Mips/imm.ll
+++ b/llvm/test/CodeGen/Mips/imm.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
define i32 @foo0() nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll b/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
index 759e84b02007ca..cb01e605e9a1fe 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
; Check for the emission of appropriate assembler directives before and
; after the inline assembly code.
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll
index aa75a1d0a9bc4f..f04e64889e0010 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-R.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
@data = global [8193 x i32] zeroinitializer
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
index f3431aa4c82519..fb075c26862671 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT
-; RUN: llc -march=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT
+; RUN: llc -mtriple=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT
@data = global [8193 x i32] zeroinitializer
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
index b05f586b1351b6..6071469e82bded 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6
-; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6
+; RUN: llc -mtriple=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \
; RUN: < %s | FileCheck %s --check-prefixes=ALL,R6
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6
-; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6
+; RUN: llc -mtriple=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
; RUN: < %s | FileCheck %s --check-prefixes=ALL,PRER6
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
index c09108dc07447a..48b754f3a6ca30 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
@@ -2,7 +2,7 @@
;This is a negative test. The constant value given for the constraint
;is greater than 16 bits.
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
index 2b24b0f82c57f1..1239263287f38e 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
@@ -2,7 +2,7 @@
;This is a negative test. The constant value given for the constraint (J)
;is non-zero (3).
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
index 3baf437324acb6..13a41e8dc04e49 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
@@ -2,7 +2,7 @@
;This is a negative test. The constant value given for the constraint (K)
;is greater than 16 bits (0x00100000).
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
index 5edb3e24674e0a..75b42e8c93a0c0 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
@@ -2,7 +2,7 @@
;This is a negative test. The constant value given for the constraint (L)
;is non-zero in the lower 16 bits (0x00100003).
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
index eaa540acdafabc..84121ad8ddd4cc 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
@@ -3,7 +3,7 @@
;immediate in the range of -65535 to -1 (inclusive).
;Our example uses the positive value 3.
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
index 56afbaaa9cd677..e4b760955a650f 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
@@ -3,7 +3,7 @@
;signed 15 bit immediate (+- 16383).
;Our example uses the positive value 16384.
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
index 0a55cb55e5f23e..c240e3457e4871 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
@@ -3,7 +3,7 @@
; A constant in the range of 1 to 655535 inclusive.
; Our example uses the positive value 655536.
;
-; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: not llc -mtriple=mipsel < %s 2> %t
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
index a2a863671d40e9..27be7815c19f03 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
@data = global [8193 x i32] zeroinitializer
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
index 295b93b6f1822d..9ec7f8196cd267 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mips -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips -relocation-model=pic < %s \
; RUN: | FileCheck --check-prefixes=CHECK,EB %s
-; RUN: llc -march=mipsel -relocation-model=pic < %s \
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s \
; RUN: | FileCheck --check-prefixes=CHECK,EL %s
; Simple memory
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll
index 550446deb58164..356c5f41f52708 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-o.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
@data = global [8193 x i32] zeroinitializer
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
index 4d3a288875fa56..19dd3d6b39a6ed 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
@@ -1,7 +1,7 @@
; Positive test for inline register constraints
;
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck %s
define i32 @main() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
index ae0504980cc2a3..661c0cb717f732 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
@@ -4,7 +4,7 @@
; The target is 64 bit.
;
;
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint.ll
index 164d28f733e4f2..fbbe50b133b2c9 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint.ll
@@ -1,6 +1,6 @@
-; RUN: llc -no-integrated-as -march=mipsel < %s | \
+; RUN: llc -no-integrated-as -mtriple=mipsel < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,GAS
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS
define void @constraint_I() nounwind {
; First I with short
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
index 705570f808ce00..6366972e2b4958 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraints-softfloat.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips64 < %s | FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64 < %s | FileCheck %s --check-prefix=MIPS64
define dso_local void @read_double(ptr nocapture noundef readonly %0) local_unnamed_addr #0 {
; MIPS32-LABEL: read_double:
diff --git a/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll b/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll
index e94b608d047e72..3bf1a26641cf60 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-opcode-bad-y.ll
@@ -1,7 +1,7 @@
; Negative test for the 'm' operand code. This operand code is applicable
; for an immediate whic is exact power of 2.
-; RUN: not llc -march=mips < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=mips < %s 2>&1 | FileCheck %s
define i32 @foo() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
index 88e56a89cd7bba..db9edb2974f9e4 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -1,14 +1,14 @@
; Positive test for inline register constraints
;
-; RUN: llc -no-integrated-as -march=mipsel -relocation-model=pic < %s | \
+; RUN: llc -no-integrated-as -mtriple=mipsel -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefixes=ALL,LE32,GAS %s
-; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \
+; RUN: llc -no-integrated-as -mtriple=mips -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefixes=ALL,BE32,GAS %s
; IAS might not print in the same way since it parses the assembly.
-; RUN: llc -march=mipsel -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefixes=ALL,LE32,IAS %s
-; RUN: llc -march=mips -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefixes=ALL,BE32,IAS %s
%union.u_tag = type { i64 }
diff --git a/llvm/test/CodeGen/Mips/ins.ll b/llvm/test/CodeGen/Mips/ins.ll
index 615dc8f3d6ac5a..06e493bcd759cb 100644
--- a/llvm/test/CodeGen/Mips/ins.ll
+++ b/llvm/test/CodeGen/Mips/ins.ll
@@ -1,6 +1,6 @@
; RUN: llc -O3 -mcpu=mips32r2 -mtriple=mipsel-linux-gnu < %s -o - \
; RUN: | FileCheck %s --check-prefixes=MIPS32R2
-; RUN: llc -O3 -mcpu=mips64r2 -march=mips64el < %s \
+; RUN: llc -O3 -mcpu=mips64r2 -mtriple=mips64el < %s \
; RUN: | FileCheck %s --check-prefixes=MIPS64R2
define i32 @or_and_shl(i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
index 02dd9085c31e8d..1574eeb11a3d53 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
index 97cb085eac505f..2e750aade31a53 100644
--- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
index e76af1be9493f1..9a0e9a37282cd7 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
index 2649683824472c..e3862d7d242eaa 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
index fc24a2756c6ab3..74522e991d97a8 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
index 7001221bb0db13..f69f20fcfb7e4d 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
index b9e3b8c169e42d..52e5b6d0f6921d 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
index 6663b96494ab9e..75c1c1e44c6c6c 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK-NOT: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
index 8407a7a836f764..b001b42c2cf3cc 100644
--- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
index d72837850cfbe9..c881d65898ee8f 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
index 71d4242c948c1b..b074b87821947f 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
index 35848a936e5c05..c9a3410aef673c 100644
--- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
index a00d3cf715a79a..0ae16d1d43d6b1 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
index 0bbbdd2322459d..fe622e12e7fe73 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
index c1f5f044bdeea8..2ae4dc7c9f2baa 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
index 9f9953a855658a..34c509a016fc66 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
index 12e999d5d488f5..7ce2c9509f9e74 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
index f204a3373f76f5..9e185cb943f26d 100644
--- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
index c7b16fd50ab0e0..da42bac7140c79 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
index ce2abeb3cdcf41..1762d8942aee12 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
index 57737ea60283d5..42158f63872c27 100644
--- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
index 1e48f1e8a236c6..72d6d690429e4d 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position + Size is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
index c72e6f5a3be30d..c2464d3d94c246 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Position operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
index 92319bd3ff8a63..050e909933efb7 100644
--- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir
+++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir
@@ -1,4 +1,4 @@
-# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
+# RUN: not --crash llc -mtriple=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \
# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
# CHECK: Size operand is out of range!
diff --git a/llvm/test/CodeGen/Mips/int-to-float-conversion.ll b/llvm/test/CodeGen/Mips/int-to-float-conversion.ll
index 6444d1fe855630..84bc6a253595a8 100644
--- a/llvm/test/CodeGen/Mips/int-to-float-conversion.ll
+++ b/llvm/test/CodeGen/Mips/int-to-float-conversion.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global ptr null, align 4
diff --git a/llvm/test/CodeGen/Mips/internalfunc.ll b/llvm/test/CodeGen/Mips/internalfunc.ll
index 7db46f54da5376..34bf5d03d8f989 100644
--- a/llvm/test/CodeGen/Mips/internalfunc.ll
+++ b/llvm/test/CodeGen/Mips/internalfunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=mipsel -relocation-model=pic | FileCheck %s
@caller.sf1 = internal unnamed_addr global ptr null, align 4
@gf1 = external global ptr
diff --git a/llvm/test/CodeGen/Mips/jumptable_labels.ll b/llvm/test/CodeGen/Mips/jumptable_labels.ll
index 8ae22be9dd23ab..fa8180847885aa 100644
--- a/llvm/test/CodeGen/Mips/jumptable_labels.ll
+++ b/llvm/test/CodeGen/Mips/jumptable_labels.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
-; RUN: llc -march=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32
-; RUN: llc -march=mips64 < %s | FileCheck %s -check-prefix=N64
+; RUN: llc -mtriple=mips < %s | FileCheck %s -check-prefix=O32
+; RUN: llc -mtriple=mips64 -target-abi=n32 < %s | FileCheck %s -check-prefix=N32
+; RUN: llc -mtriple=mips64 < %s | FileCheck %s -check-prefix=N64
; We only use the '$' prefix on O32. The others use the ELF convention.
; O32: $JTI0_0
diff --git a/llvm/test/CodeGen/Mips/largeimm1.ll b/llvm/test/CodeGen/Mips/largeimm1.ll
index adef511a4aadd0..5d198794136377 100644
--- a/llvm/test/CodeGen/Mips/largeimm1.ll
+++ b/llvm/test/CodeGen/Mips/largeimm1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
define void @f() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/largeimmprinting.ll b/llvm/test/CodeGen/Mips/largeimmprinting.ll
index eed9e12eac8b03..efa0aa63abf673 100644
--- a/llvm/test/CodeGen/Mips/largeimmprinting.ll
+++ b/llvm/test/CodeGen/Mips/largeimmprinting.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefix=64
%struct.S1 = type { [65536 x i8] }
diff --git a/llvm/test/CodeGen/Mips/lazy-binding.ll b/llvm/test/CodeGen/Mips/lazy-binding.ll
index 4f5c71effe6969..e9860acb91bb4e 100644
--- a/llvm/test/CodeGen/Mips/lazy-binding.ll
+++ b/llvm/test/CodeGen/Mips/lazy-binding.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s
; CHECK-LABEL: foo6:
; CHECK: %while.body
diff --git a/llvm/test/CodeGen/Mips/lb1.ll b/llvm/test/CodeGen/Mips/lb1.ll
index caff4c7fa33a4b..7d93a9076d3c8a 100644
--- a/llvm/test/CodeGen/Mips/lb1.ll
+++ b/llvm/test/CodeGen/Mips/lb1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@c = global i8 -1, align 1
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/lbu1.ll b/llvm/test/CodeGen/Mips/lbu1.ll
index 13fe20af1aef90..c492c0d4784d95 100644
--- a/llvm/test/CodeGen/Mips/lbu1.ll
+++ b/llvm/test/CodeGen/Mips/lbu1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@c = global i8 97, align 1
@.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/lh1.ll b/llvm/test/CodeGen/Mips/lh1.ll
index 4ec8d928cd0630..5d4facc38ce6b5 100644
--- a/llvm/test/CodeGen/Mips/lh1.ll
+++ b/llvm/test/CodeGen/Mips/lh1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@s = global i16 -1, align 2
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/lhu1.ll b/llvm/test/CodeGen/Mips/lhu1.ll
index 1d438b6093de70..561e8461552fed 100644
--- a/llvm/test/CodeGen/Mips/lhu1.ll
+++ b/llvm/test/CodeGen/Mips/lhu1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@s = global i16 255, align 2
diff --git a/llvm/test/CodeGen/Mips/llcarry.ll b/llvm/test/CodeGen/Mips/llcarry.ll
index 4bba047ba1f0be..45e4cbd2a59708 100644
--- a/llvm/test/CodeGen/Mips/llcarry.ll
+++ b/llvm/test/CodeGen/Mips/llcarry.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i64 4294967295, align 8
@j = global i64 15, align 8
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/abs.ll b/llvm/test/CodeGen/Mips/llvm-ir/abs.ll
index c0812977e3a11b..e4dde185b48b57 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/abs.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/abs.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+abs2008,+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define float @abs_s(float %a) {
; MIPS32: {{(ori|ins)}}
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
index 84c4bf677f9455..6a08b294584852 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
@@ -1,32 +1,32 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,PRE4
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,GP32-CMOV
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP32
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR3,MM32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll b/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
index bddbdc667bd6e2..71a9ca80b95fab 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/addrspacecast.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
; Address spaces 1-255 are software defined.
define ptr @cast(ptr %arg) {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
index 33a86bbc5dee62..7b56deae3c0900 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/arith-fp.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define double @add_d(double %a, double %b) {
; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll b/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll
index 2e03ee9868a979..3a1a9bee56c25f 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll
@@ -1,6 +1,6 @@
-; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \
+; RUN: llc -asm-show-inst -mtriple=mipsel -mcpu=mips32r6 < %s | \
; RUN: FileCheck %s -check-prefix=CHK32
-; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \
+; RUN: llc -asm-show-inst -mtriple=mips64el -mcpu=mips64r6 < %s | \
; RUN: FileCheck %s -check-prefix=CHK64
@a = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
index a649234342dd2a..a4a2f920a7d7d1 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/bitcast.ll
@@ -1,12 +1,12 @@
-; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst \
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst \
; RUN: < %s | FileCheck %s --check-prefix=MIPS32R2
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \
; RUN: < %s | FileCheck %s --check-prefix=MIPS32FP64
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \
; RUN: < %s | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \
; RUN: < %s | FileCheck %s --check-prefix=MMFP64
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \
; RUN: < %s | FileCheck %s --check-prefix=MMR6
define double @mthc1(i64 %a) {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/call.ll b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
index a259bdd04c2e4f..a962e1763618a4 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/call.ll
@@ -1,29 +1,29 @@
; Test the 'call' instruction and the tailcall variant.
-; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
-; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
-; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
-; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
-; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
-; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
-; RUN: llc -march=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
-; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
+; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,O32,R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,N64,R6C
+; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -check-prefix=R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=NOT-R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -check-prefix=R6C
declare void @extern_void_void()
declare i32 @extern_i32_void()
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
index 04368f202fa560..0901c8cbfda7f8 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/cvt.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
; TODO: Test for cvt_w_d is missing, could not generate instruction
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
index 4f926cbee0b218..290491a13d7737 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
; This test triggered a bug in the vector splitting where the type legalizer
; attempted to extract the element with by storing the vector, then reading
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
index aebeac9e5bd216..c5176669fec2ee 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
@@ -1,16 +1,16 @@
; Test all important variants of the unconditional 'br' instruction.
-; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C
-; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6
+; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6
define i32 @br(ptr %addr) {
; ALL-LABEL: br:
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll b/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
index 4e434617d39ef7..f38aa78dd587e3 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lh_lhu.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
@us = global i16 0, align 2
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll b/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll
index f401b0a1d6c9ee..16c09003298c2f 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
-; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
+; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,M64
-; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,M64
define i8 @load_i8(ptr %ptr) {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
index 19955e4f9bbd55..00b91d1413cfe6 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -1,30 +1,30 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32
-; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R6
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll b/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll
index 918cda6b38c265..34c7720ecbe034 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/nan-fp-attr.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s --check-prefix=MIPS32R1
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s --check-prefix=MIPS32R2
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s --check-prefix=MIPS32R2
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s --check-prefix=MIPS32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s --check-prefix=MIPS64R1
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s --check-prefix=MIPS64R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R2-ABS2K8
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s --check-prefix=MIPS64R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R6-ABS2K8
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s --check-prefix=MM
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008 | FileCheck %s --check-prefix=MM-ABS2K8
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008,+fp64 | FileCheck %s --check-prefix=MM-ABS2K8
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips,+fp64 | FileCheck %s --check-prefix=MM
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s --check-prefix=MMR6
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s --check-prefix=MIPS32R1
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s --check-prefix=MIPS32R2
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+abs2008,+fp64 | FileCheck %s --check-prefix=MIPS32R2-ABS2K8
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 | FileCheck %s --check-prefix=MIPS32R2
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s --check-prefix=MIPS32R6
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s --check-prefix=MIPS64R1
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s --check-prefix=MIPS64R2
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R2-ABS2K8
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -mattr=+abs2008 | FileCheck %s --check-prefix=MIPS64R6-ABS2K8
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s --check-prefix=MM
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008 | FileCheck %s --check-prefix=MM-ABS2K8
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips,+abs2008,+fp64 | FileCheck %s --check-prefix=MM-ABS2K8
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips,+fp64 | FileCheck %s --check-prefix=MM
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s --check-prefix=MMR6
; Test that the instruction selection for the case of `abs.s` and `abs.d`
; matches the expected behaviour. In the default case with NaNs and no "abs2008"
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/not.ll b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
index 03ba8e562ef052..58ed0e66d5e217 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/not.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
@@ -1,30 +1,30 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP32
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,GP64
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MM,MM32
define signext i1 @not_i1(i1 signext %a) {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
index 7b377843706624..550ee0395ab777 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -7,23 +7,23 @@
; affects it and it's undesirable to repeat the non-pointer returns for each
; relocation model.
-; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
-; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
-; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
-; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled
; as mthc1 has unmodeled side effects. This is an artifact of our backend.
; Force the delay slot filler off to check that the sequence jr $ra; nop is
; turned into jic 0, $ra.
-; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
define void @ret_void() {
; ALL-LABEL: ret_void:
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index 8bf83c5c18ce7c..12728177380fcf 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -1,32 +1,32 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefixes=ALL,M2,M2-M3
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-32
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-32
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-32
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-32
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,SEL,SEL-32
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefixes=ALL,M3,M2-M3
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,SEL,SEL-64
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst | FileCheck %s \
; RUN: -check-prefixes=ALL,MM32R3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32R6
define signext i1 @tst_select_i1_i1(i1 signext %s,
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll
index 05776886dd9473..f4b86257b5b700 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll
@@ -1,11 +1,11 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MIPS32FP64
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MM
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst < %s | FileCheck %s --check-prefix=MMFP64
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst < %s | FileCheck %s --check-prefix=MMR6
define float @sqrt_fn(float %value) #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll b/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll
index 09713805c101c0..b9ffbff0c6bc6e 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
-; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
+; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,M64
-; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,M64
define void @store_i8(ptr %ptr, i8 signext %v) {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
index 51dcccefc84d3a..b465e24d47a059 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -1,32 +1,32 @@
-; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM,PRE4
-; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM
-; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
-; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
-; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
-; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
; RUN: -check-prefixes=MM32,MMR3
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=MM32,MMR6
-; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
+; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll
index 3c3110341df269..3925b73527b432 100644
--- a/llvm/test/CodeGen/Mips/load-store-left-right.ll
+++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll
@@ -1,18 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s
-; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s
-; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s
-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s
-; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s
-; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s
-; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s
-; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s
-; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s
-; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s
+; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EL %s
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32,MIPS32-EB %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EL %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS32R6,MIPS32R6-EB %s
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EL %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64-EB %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EL %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64,MIPS64R2-EB %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=MIPS64R6 %s
%struct.SLL = type { i64 }
%struct.SI = type { i32 }
diff --git a/llvm/test/CodeGen/Mips/long-call-attr.ll b/llvm/test/CodeGen/Mips/long-call-attr.ll
index beda290a9725b4..1c25a36cf12362 100644
--- a/llvm/test/CodeGen/Mips/long-call-attr.ll
+++ b/llvm/test/CodeGen/Mips/long-call-attr.ll
@@ -1,10 +1,10 @@
-; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
+; RUN: llc -mtriple=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=O32 %s
-; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
+; RUN: llc -mtriple=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=O32 %s
-; RUN: llc -march=mips64 -target-abi n64 --mattr=+long-calls,+noabicalls < %s \
+; RUN: llc -mtriple=mips64 -target-abi n64 --mattr=+long-calls,+noabicalls < %s \
; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=N64 %s
-; RUN: llc -march=mips64 -target-abi n64 --mattr=-long-calls,+noabicalls < %s \
+; RUN: llc -mtriple=mips64 -target-abi n64 --mattr=-long-calls,+noabicalls < %s \
; RUN: -mips-jalr-reloc=false | FileCheck -check-prefix=N64 %s
declare void @far() #0
diff --git a/llvm/test/CodeGen/Mips/long-call-mcount.ll b/llvm/test/CodeGen/Mips/long-call-mcount.ll
index 40d3b74ee57976..2e90a47ad0f013 100644
--- a/llvm/test/CodeGen/Mips/long-call-mcount.ll
+++ b/llvm/test/CodeGen/Mips/long-call-mcount.ll
@@ -1,7 +1,7 @@
; Check call to mcount in case of long/short call options.
-; RUN: llc -march=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
+; RUN: llc -mtriple=mips -target-abi o32 --mattr=+long-calls,+noabicalls < %s \
; RUN: -mips-jalr-reloc=false | FileCheck -check-prefixes=CHECK,LONG %s
-; RUN: llc -march=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
+; RUN: llc -mtriple=mips -target-abi o32 --mattr=-long-calls,+noabicalls < %s \
; RUN: -mips-jalr-reloc=false | FileCheck -check-prefixes=CHECK,SHORT %s
define void @foo() {
diff --git a/llvm/test/CodeGen/Mips/long-calls.ll b/llvm/test/CodeGen/Mips/long-calls.ll
index 99fce03cd00593..5ee1ee1ed575e2 100644
--- a/llvm/test/CodeGen/Mips/long-calls.ll
+++ b/llvm/test/CodeGen/Mips/long-calls.ll
@@ -1,19 +1,19 @@
-; RUN: llc -march=mips -mattr=-long-calls %s -o - \
+; RUN: llc -mtriple=mips -mattr=-long-calls %s -o - \
; RUN: | FileCheck -check-prefix=OFF %s
-; RUN: llc -march=mips -mattr=+long-calls,+noabicalls %s -o - \
+; RUN: llc -mtriple=mips -mattr=+long-calls,+noabicalls %s -o - \
; RUN: | FileCheck -check-prefix=ON32 %s
-; RUN: llc -march=mips -mattr=+long-calls,-noabicalls %s -o - \
+; RUN: llc -mtriple=mips -mattr=+long-calls,-noabicalls %s -o - \
; RUN: | FileCheck -check-prefix=OFF %s
-; RUN: llc -march=mips64 -target-abi n32 -mattr=-long-calls %s -o - \
+; RUN: llc -mtriple=mips64 -target-abi n32 -mattr=-long-calls %s -o - \
; RUN: | FileCheck -check-prefix=OFF %s
-; RUN: llc -march=mips64 -target-abi n32 -mattr=+long-calls,+noabicalls %s -o - \
+; RUN: llc -mtriple=mips64 -target-abi n32 -mattr=+long-calls,+noabicalls %s -o - \
; RUN: | FileCheck -check-prefix=ON32 %s
-; RUN: llc -march=mips64 -target-abi n64 -mattr=-long-calls %s -o - \
+; RUN: llc -mtriple=mips64 -target-abi n64 -mattr=-long-calls %s -o - \
; RUN: | FileCheck -check-prefix=OFF %s
-; RUN: llc -march=mips64 -target-abi n64 -mattr=+long-calls,+noabicalls %s -o - \
+; RUN: llc -mtriple=mips64 -target-abi n64 -mattr=+long-calls,+noabicalls %s -o - \
; RUN: | FileCheck -check-prefix=ON64 %s
declare void @callee()
diff --git a/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll b/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
index 709cd477a778e6..3f6ac94801eb30 100644
--- a/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
+++ b/llvm/test/CodeGen/Mips/longbranch/compact-branches-long-branch.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -force-mips-long-branch | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -force-mips-long-branch | FileCheck %s
; Check that when MIPS32R6 with the static relocation model with the usage of
; long branches, that there is a nop between any compact branch and the static
diff --git a/llvm/test/CodeGen/Mips/machineverifier.ll b/llvm/test/CodeGen/Mips/machineverifier.ll
index 39d2a7e4a9360e..73cb2c62ee0553 100644
--- a/llvm/test/CodeGen/Mips/machineverifier.ll
+++ b/llvm/test/CodeGen/Mips/machineverifier.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mipsel -verify-machineinstrs
+; RUN: llc < %s -mtriple=mipsel -verify-machineinstrs
; Make sure machine verifier understands the last instruction of a basic block
; is not the terminator instruction after delay slot filler pass is run.
diff --git a/llvm/test/CodeGen/Mips/madd-msub.ll b/llvm/test/CodeGen/Mips/madd-msub.ll
index 9f7145685ed311..6bb1ea48184f98 100644
--- a/llvm/test/CodeGen/Mips/madd-msub.ll
+++ b/llvm/test/CodeGen/Mips/madd-msub.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=32
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=32
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=32R6
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
-; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=64
-; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=64
-; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=64R6
-; RUN: llc -march=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=16
+; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=32
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=32
+; RUN: llc -mtriple=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=32R6
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
+; RUN: llc -mtriple=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=64
+; RUN: llc -mtriple=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=64
+; RUN: llc -mtriple=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=64R6
+; RUN: llc -mtriple=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=16
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
; 32-LABEL: madd1:
diff --git a/llvm/test/CodeGen/Mips/mcount.ll b/llvm/test/CodeGen/Mips/mcount.ll
index 8a129536d97699..b45b59eedbc9c7 100644
--- a/llvm/test/CodeGen/Mips/mcount.ll
+++ b/llvm/test/CodeGen/Mips/mcount.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -verify-machineinstrs \
+; RUN: llc -mtriple=mips -verify-machineinstrs \
; RUN: < %s | FileCheck %s -check-prefix=MIPS32
-; RUN: llc -march=mips -verify-machineinstrs -relocation-model=pic \
+; RUN: llc -mtriple=mips -verify-machineinstrs -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefix=MIPS32-PIC
-; RUN: llc -march=mips64 -verify-machineinstrs \
+; RUN: llc -mtriple=mips64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s -check-prefix=MIPS64
-; RUN: llc -march=mips64 -verify-machineinstrs -relocation-model=pic \
+; RUN: llc -mtriple=mips64 -verify-machineinstrs -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefix=MIPS64-PIC
-; RUN: llc -march=mips -verify-machineinstrs -mattr=+micromips \
+; RUN: llc -mtriple=mips -verify-machineinstrs -mattr=+micromips \
; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM
-; RUN: llc -march=mips -verify-machineinstrs -relocation-model=pic -mattr=+micromips \
+; RUN: llc -mtriple=mips -verify-machineinstrs -relocation-model=pic -mattr=+micromips \
; RUN: < %s | FileCheck %s -check-prefix=MIPS32-MM-PIC
; Test that checks ABI for _mcount calls.
diff --git a/llvm/test/CodeGen/Mips/memcpy.ll b/llvm/test/CodeGen/Mips/memcpy.ll
index 554452457166de..009a2f99f5ce3b 100644
--- a/llvm/test/CodeGen/Mips/memcpy.ll
+++ b/llvm/test/CodeGen/Mips/memcpy.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
%struct.S1 = type { i32, [41 x i8] }
diff --git a/llvm/test/CodeGen/Mips/micromips-addiu.ll b/llvm/test/CodeGen/Mips/micromips-addiu.ll
index 5165994126a2a1..4129e6f6e0b489 100644
--- a/llvm/test/CodeGen/Mips/micromips-addiu.ll
+++ b/llvm/test/CodeGen/Mips/micromips-addiu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = global i32 65504, align 4
diff --git a/llvm/test/CodeGen/Mips/micromips-addu16.ll b/llvm/test/CodeGen/Mips/micromips-addu16.ll
index 04243fc899f869..75a0f2dd4147e5 100644
--- a/llvm/test/CodeGen/Mips/micromips-addu16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-addu16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
diff --git a/llvm/test/CodeGen/Mips/micromips-and16.ll b/llvm/test/CodeGen/Mips/micromips-and16.ll
index 66cfb0807f9d91..8a4da682442840 100644
--- a/llvm/test/CodeGen/Mips/micromips-and16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-and16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
diff --git a/llvm/test/CodeGen/Mips/micromips-andi.ll b/llvm/test/CodeGen/Mips/micromips-andi.ll
index c84a99fbef4158..8841e402f2b921 100644
--- a/llvm/test/CodeGen/Mips/micromips-andi.ll
+++ b/llvm/test/CodeGen/Mips/micromips-andi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = global i32 65504, align 4
diff --git a/llvm/test/CodeGen/Mips/micromips-attr.ll b/llvm/test/CodeGen/Mips/micromips-attr.ll
index 1ea9b136e1d401..8e70cc616e0b7e 100644
--- a/llvm/test/CodeGen/Mips/micromips-attr.ll
+++ b/llvm/test/CodeGen/Mips/micromips-attr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=mips32 --mattr=-micromips < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32 --mattr=-micromips < %s | FileCheck %s
define void @foo() #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/micromips-compact-branches.ll b/llvm/test/CodeGen/Mips/micromips-compact-branches.ll
index 3b05e9e174f352..fb04f8f5ec6b11 100644
--- a/llvm/test/CodeGen/Mips/micromips-compact-branches.ll
+++ b/llvm/test/CodeGen/Mips/micromips-compact-branches.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm -O3 \
+; RUN: llc %s -mtriple=mipsel -mattr=micromips -filetype=asm -O3 \
; RUN: -disable-mips-delay-filler -relocation-model=pic -o - | FileCheck %s
define void @main() nounwind uwtable {
diff --git a/llvm/test/CodeGen/Mips/micromips-compact-jump.ll b/llvm/test/CodeGen/Mips/micromips-compact-jump.ll
index 70cff84e967f0c..a4c5e5fc492ce9 100644
--- a/llvm/test/CodeGen/Mips/micromips-compact-jump.ll
+++ b/llvm/test/CodeGen/Mips/micromips-compact-jump.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -disable-mips-delay-filler -O3 < %s | FileCheck %s
define i32 @foo(i32 signext %a) #0 {
diff --git a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll
index 95f557770a10d1..ae1a93e884883a 100644
--- a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll
+++ b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@g = external global i32
diff --git a/llvm/test/CodeGen/Mips/micromips-li.ll b/llvm/test/CodeGen/Mips/micromips-li.ll
index bfac23c25ea5b9..ebe7e3c90ac365 100644
--- a/llvm/test/CodeGen/Mips/micromips-li.ll
+++ b/llvm/test/CodeGen/Mips/micromips-li.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@x = external global i32
diff --git a/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll b/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll
index 5215c3a519989f..b41a4080e64ecc 100644
--- a/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll
+++ b/llvm/test/CodeGen/Mips/micromips-load-effective-address.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \
+; RUN: llc %s -mtriple=mipsel -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
define i32 @sum(ptr %x, ptr %y) nounwind uwtable {
diff --git a/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
index 29d46bed4226da..4884d0a22a244d 100644
--- a/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
+++ b/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
; RUN: -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MM32
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
; RUN: -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MM32
diff --git a/llvm/test/CodeGen/Mips/micromips-not16.ll b/llvm/test/CodeGen/Mips/micromips-not16.ll
index 2def472fce40ae..ef1ff01f9b2c7f 100644
--- a/llvm/test/CodeGen/Mips/micromips-not16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-not16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
diff --git a/llvm/test/CodeGen/Mips/micromips-or16.ll b/llvm/test/CodeGen/Mips/micromips-or16.ll
index ae2c53884ef736..d82d3f68fc38e5 100644
--- a/llvm/test/CodeGen/Mips/micromips-or16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-or16.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
-; RUN: llc -O0 -march=mips -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -O0 -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \
; RUN: -asm-show-inst < %s | FileCheck %s
; Branch instruction added to enable FastISel::selectOperator
diff --git a/llvm/test/CodeGen/Mips/micromips-shift.ll b/llvm/test/CodeGen/Mips/micromips-shift.ll
index 11472b8ac99fa4..9d2a5ec075ed2d 100644
--- a/llvm/test/CodeGen/Mips/micromips-shift.ll
+++ b/llvm/test/CodeGen/Mips/micromips-shift.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@a = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
index 216fec6a7f6efa..cadb440cfdab19 100644
--- a/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
+++ b/llvm/test/CodeGen/Mips/micromips-short-delay-slot.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips %s -o - \
+# RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips %s -o - \
# RUN: -start-after=block-placement | FileCheck %s
# Test that the micromips jal instruction is correctly handled by the delay slot
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll
index 8949b19f4ada0c..cedd76ebea009a 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
define i32 @f1() {
entry:
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
index 4cada64548f47f..ca4d6856f87f14 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16-sb16-sh16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
define void @f1(ptr %p) {
; CHECK-LABEL: f1:
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
index 46a963e2373f3d..5d594e27c2fcc1 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: nounwind
define i32 @function1(ptr %f) {
diff --git a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll
index e953df62bf2ad1..3120b1a5b6d662 100644
--- a/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: nounwind readnone
define i1 @fun(i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/Mips/micromips-subu16.ll b/llvm/test/CodeGen/Mips/micromips-subu16.ll
index 874f6dfbcbfa3f..972cca99ba1b8c 100644
--- a/llvm/test/CodeGen/Mips/micromips-subu16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-subu16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
diff --git a/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll b/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll
index c11c817b41651d..890e6d002db51a 100644
--- a/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \
+; RUN: llc %s -mtriple=mipsel -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
; Function Attrs: noinline nounwind
diff --git a/llvm/test/CodeGen/Mips/micromips-xor16.ll b/llvm/test/CodeGen/Mips/micromips-xor16.ll
index a09531bc706cbd..3bf6b8bfbb4c30 100644
--- a/llvm/test/CodeGen/Mips/micromips-xor16.ll
+++ b/llvm/test/CodeGen/Mips/micromips-xor16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
define i32 @main() {
diff --git a/llvm/test/CodeGen/Mips/mips16_32_1.ll b/llvm/test/CodeGen/Mips/mips16_32_1.ll
index bf95c06a49328b..0d020221c5efc5 100644
--- a/llvm/test/CodeGen/Mips/mips16_32_1.ll
+++ b/llvm/test/CodeGen/Mips/mips16_32_1.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s
-; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s
define void @foo() #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips16fpe.ll b/llvm/test/CodeGen/Mips/mips16fpe.ll
index 310213b43b002d..7c6fdd532414c5 100644
--- a/llvm/test/CodeGen/Mips/mips16fpe.ll
+++ b/llvm/test/CodeGen/Mips/mips16fpe.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 \
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=16hf
@x = global float 5.000000e+00, align 4
diff --git a/llvm/test/CodeGen/Mips/mips3-spill-slot.ll b/llvm/test/CodeGen/Mips/mips3-spill-slot.ll
index 4eabbeb867e38e..d1cfce09e67ed2 100644
--- a/llvm/test/CodeGen/Mips/mips3-spill-slot.ll
+++ b/llvm/test/CodeGen/Mips/mips3-spill-slot.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64 -mcpu=mips3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=mips64 -mcpu=mips3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK
; This testcase is from PR35859.
; Check that spill slot has the correct size for mips3 and n64 ABI.
; Previously, this test case would fail during register
diff --git a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll
index 8eac8d4683d151..4e8b588345536f 100644
--- a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll
+++ b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s
-; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 < %s | FileCheck %s
+; RUN: not llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s
; CHECK: foo:
; DSP: MIPS32r6 is not compatible with the DSP ASE
diff --git a/llvm/test/CodeGen/Mips/mips64-f128-call.ll b/llvm/test/CodeGen/Mips/mips64-f128-call.ll
index 879dc902eeb33a..58ea4c424fe205 100644
--- a/llvm/test/CodeGen/Mips/mips64-f128-call.ll
+++ b/llvm/test/CodeGen/Mips/mips64-f128-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s
@gld0 = external global fp128
@gld1 = external global fp128
diff --git a/llvm/test/CodeGen/Mips/mips64-libcall.ll b/llvm/test/CodeGen/Mips/mips64-libcall.ll
index 7c0e5b2bbfdce1..9de35a893f4c53 100644
--- a/llvm/test/CodeGen/Mips/mips64-libcall.ll
+++ b/llvm/test/CodeGen/Mips/mips64-libcall.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 -O3 < %s |\
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -O3 < %s |\
; RUN: FileCheck %s -check-prefix=HARD
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+soft-float < %s |\
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+soft-float < %s |\
; RUN: FileCheck %s -check-prefix=SOFT
; Check that %add is not passed in an integer register.
diff --git a/llvm/test/CodeGen/Mips/mips64-sret.ll b/llvm/test/CodeGen/Mips/mips64-sret.ll
index 9f4bc9ddfcc548..4c05ec097b068e 100644
--- a/llvm/test/CodeGen/Mips/mips64-sret.ll
+++ b/llvm/test/CodeGen/Mips/mips64-sret.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
define void @foo(ptr noalias sret(i32) %agg.result) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64directive.ll b/llvm/test/CodeGen/Mips/mips64directive.ll
index 6d6674496f7d0a..3d5a32f43982e7 100644
--- a/llvm/test/CodeGen/Mips/mips64directive.ll
+++ b/llvm/test/CodeGen/Mips/mips64directive.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
@gl = global i64 1250999896321, align 8
diff --git a/llvm/test/CodeGen/Mips/mips64ext.ll b/llvm/test/CodeGen/Mips/mips64ext.ll
index 9c1243b8f18c62..0e863001973cc1 100644
--- a/llvm/test/CodeGen/Mips/mips64ext.ll
+++ b/llvm/test/CodeGen/Mips/mips64ext.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
define i64 @zext64_32(i32 %a) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64extins.ll b/llvm/test/CodeGen/Mips/mips64extins.ll
index f160603c2507ed..8621938092183e 100644
--- a/llvm/test/CodeGen/Mips/mips64extins.ll
+++ b/llvm/test/CodeGen/Mips/mips64extins.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s
define i64 @dext(i64 %i) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64fpimm0.ll b/llvm/test/CodeGen/Mips/mips64fpimm0.ll
index 0296cb523f98fd..a8d7f432eba461 100644
--- a/llvm/test/CodeGen/Mips/mips64fpimm0.ll
+++ b/llvm/test/CodeGen/Mips/mips64fpimm0.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
define double @foo1() nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64fpldst.ll b/llvm/test/CodeGen/Mips/mips64fpldst.ll
index 7811ed85f3adb2..ad09f78b3184c2 100644
--- a/llvm/test/CodeGen/Mips/mips64fpldst.ll
+++ b/llvm/test/CodeGen/Mips/mips64fpldst.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
@f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8
diff --git a/llvm/test/CodeGen/Mips/mips64imm.ll b/llvm/test/CodeGen/Mips/mips64imm.ll
index 993c7c77e35c16..a78e1dce518ae8 100644
--- a/llvm/test/CodeGen/Mips/mips64imm.ll
+++ b/llvm/test/CodeGen/Mips/mips64imm.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s
define i32 @foo1() nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64instrs.ll b/llvm/test/CodeGen/Mips/mips64instrs.ll
index e8b630b004cb09..2dc88dfffa2558 100644
--- a/llvm/test/CodeGen/Mips/mips64instrs.ll
+++ b/llvm/test/CodeGen/Mips/mips64instrs.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s
-; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s
-; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s
@gll0 = common global i64 0, align 8
@gll1 = common global i64 0, align 8
diff --git a/llvm/test/CodeGen/Mips/mips64intldst.ll b/llvm/test/CodeGen/Mips/mips64intldst.ll
index 89e13247da014d..7df92dd8028ef4 100644
--- a/llvm/test/CodeGen/Mips/mips64intldst.ll
+++ b/llvm/test/CodeGen/Mips/mips64intldst.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
@c = common global i8 0, align 4
@s = common global i16 0, align 4
diff --git a/llvm/test/CodeGen/Mips/mips64lea.ll b/llvm/test/CodeGen/Mips/mips64lea.ll
index 69c07960351663..83f4239930533e 100644
--- a/llvm/test/CodeGen/Mips/mips64lea.ll
+++ b/llvm/test/CodeGen/Mips/mips64lea.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s
define void @foo3() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64muldiv.ll b/llvm/test/CodeGen/Mips/mips64muldiv.ll
index d1292be504e646..89dd5242694910 100644
--- a/llvm/test/CodeGen/Mips/mips64muldiv.ll
+++ b/llvm/test/CodeGen/Mips/mips64muldiv.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC
-; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
; FileCheck prefixes:
; ALL - All targets
diff --git a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll
index 174f4ce1771ad5..6484173e7c3394 100644
--- a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll
+++ b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s
-; RUN: not llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s
+; RUN: llc -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s
+; RUN: not llc -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s
; CHECK: foo:
; DSP: MIPS64r6 is not compatible with the DSP ASE
diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll
index ca09d2f5b2904a..d5b85ea65ce38d 100644
--- a/llvm/test/CodeGen/Mips/mips64shift.ll
+++ b/llvm/test/CodeGen/Mips/mips64shift.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64signextendsesf.ll b/llvm/test/CodeGen/Mips/mips64signextendsesf.ll
index 831469ab062471..6160cd1dcffedb 100644
--- a/llvm/test/CodeGen/Mips/mips64signextendsesf.ll
+++ b/llvm/test/CodeGen/Mips/mips64signextendsesf.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+soft-float -O2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+soft-float -O2 < %s | FileCheck %s
define void @foosf() #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll b/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll
index 12c353d72c56c9..10cc70e34065bf 100644
--- a/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll
+++ b/llvm/test/CodeGen/Mips/mips64sinttofpsf.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+soft-float -O0 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+soft-float -O0 < %s | FileCheck %s
define double @foo() #0 {
diff --git a/llvm/test/CodeGen/Mips/mipslopat.ll b/llvm/test/CodeGen/Mips/mipslopat.ll
index c6143844a8d4d7..109bf5ebb26519 100644
--- a/llvm/test/CodeGen/Mips/mipslopat.ll
+++ b/llvm/test/CodeGen/Mips/mipslopat.ll
@@ -1,5 +1,5 @@
; This test does not check the machine code output.
-; RUN: llc -march=mips < %s
+; RUN: llc -mtriple=mips < %s
@stat_vol_ptr_int = internal global ptr null, align 4
@stat_ptr_vol_int = internal global ptr null, align 4
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
index 6002705965caeb..453a0b1b5e27b4 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
+# RUN: llc -mtriple=mips64 -target-abi n64 -start-before=finalize-isel \
# RUN: -stop-after=finalize-isel -relocation-model=pic -mattr=+xgot \
# RUN: -o /dev/null %s
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
index d9703c74fc5cea..8a20b5354f7c42 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips -start-before=finalize-isel \
+# RUN: llc -mtriple=mips -start-before=finalize-isel \
# RUN: -stop-after=finalize-isel -relocation-model=pic \
# RUN: -o /dev/null %s
diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
index 803a2d701fae49..5151cb1c89029b 100644
--- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
+++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \
+# RUN: llc -mtriple=mips64 -target-abi n64 -start-before=finalize-isel \
# RUN: -stop-after=finalize-isel -relocation-model=pic \
# RUN: -o /dev/null %s
diff --git a/llvm/test/CodeGen/Mips/misha.ll b/llvm/test/CodeGen/Mips/misha.ll
index b8e45c633aaa4a..40a738fc8a5a3b 100644
--- a/llvm/test/CodeGen/Mips/misha.ll
+++ b/llvm/test/CodeGen/Mips/misha.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
define i32 @sumc(ptr nocapture %to, ptr nocapture %from, i32) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/msa/2r.ll b/llvm/test/CodeGen/Mips/msa/2r.ll
index b7ea3fc11c6e37..32a8734a4a170e 100644
--- a/llvm/test/CodeGen/Mips/msa/2r.ll
+++ b/llvm/test/CodeGen/Mips/msa/2r.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
index f369a9ebca384a..615bbbad66ae05 100644
--- a/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
+++ b/llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
@@ -1,13 +1,13 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format and
; convert scalars to vectors.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
@llvm_mips_fill_b_ARG1 = global i32 23, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2rf.ll b/llvm/test/CodeGen/Mips/msa/2rf.ll
index 6cdf5b7b8b4238..4a272e3fa17d13 100644
--- a/llvm/test/CodeGen/Mips/msa/2rf.ll
+++ b/llvm/test/CodeGen/Mips/msa/2rf.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll
index f8bdf866c5f824..cf2e604c2623f9 100644
--- a/llvm/test/CodeGen/Mips/msa/2rf_exup.ll
+++ b/llvm/test/CodeGen/Mips/msa/2rf_exup.ll
@@ -1,8 +1,8 @@
; Test the MSA floating point conversion intrinsics (e.g. float->double) that
; are encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
@llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
index da83b7eb180b7b..b8593a7fb9368f 100644
--- a/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
+++ b/llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
@@ -1,8 +1,8 @@
; Test the MSA integer to floating point conversion intrinsics that are encoded
; with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll
index 2d773bfda17c8e..9a5c9c14b47e81 100644
--- a/llvm/test/CodeGen/Mips/msa/2rf_fq.ll
+++ b/llvm/test/CodeGen/Mips/msa/2rf_fq.ll
@@ -1,8 +1,8 @@
; Test the MSA fixed-point to floating point conversion intrinsics that are
; encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
index eeac8d4495716c..ec700da6f3c061 100644
--- a/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
@@ -2,8 +2,8 @@
; 2RF instruction format. This includes conversions but other instructions such
; as fclass are also here.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll
index 110da067778135..e3fdbecc6b7eb5 100644
--- a/llvm/test/CodeGen/Mips/msa/2rf_tq.ll
+++ b/llvm/test/CodeGen/Mips/msa/2rf_tq.ll
@@ -1,8 +1,8 @@
; Test the MSA floating-point to fixed-point conversion intrinsics that are
; encoded with the 2RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll
index 31646350b6802b..69e862850a4735 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-a.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll
@@ -1,11 +1,11 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'a'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
; It should fail to compile without fp64.
-; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \
+; RUN: not llc -mtriple=mips -mattr=+msa < %s 2>&1 | \
; RUN: FileCheck -check-prefix=FP32ERROR %s
; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode).
diff --git a/llvm/test/CodeGen/Mips/msa/3r-b.ll b/llvm/test/CodeGen/Mips/msa/3r-b.ll
index f824a6527d72dd..f2c5ebb4a580a4 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-b.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-b.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'b'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-c.ll b/llvm/test/CodeGen/Mips/msa/3r-c.ll
index 8af06b3f20bd47..38cb386b5a99b0 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-c.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-c.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'c'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-d.ll b/llvm/test/CodeGen/Mips/msa/3r-d.ll
index b40d2661ee6aa8..116e0ada6de7b7 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-d.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-d.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'd'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-i.ll b/llvm/test/CodeGen/Mips/msa/3r-i.ll
index c06d79a975bf1f..e20064bff84e98 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-i.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-i.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'i'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-m.ll b/llvm/test/CodeGen/Mips/msa/3r-m.ll
index 855ceb3dd88900..580ae4b41c621b 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-m.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-m.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'm'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-p.ll b/llvm/test/CodeGen/Mips/msa/3r-p.ll
index 063da01c29db6c..455ebb4a316163 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-p.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-p.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'p'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll
index 6c673c543bf2f9..6ea52fa856716f 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-s.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 's'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r-v.ll b/llvm/test/CodeGen/Mips/msa/3r-v.ll
index 80828a07907cd6..c71efdc0bb7459 100644
--- a/llvm/test/CodeGen/Mips/msa/3r-v.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-v.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'v'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r.ll b/llvm/test/CodeGen/Mips/msa/3r_4r.ll
index abeaee682fb48f..d32af452c4fee7 100644
--- a/llvm/test/CodeGen/Mips/msa/3r_4r.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r_4r.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format and
; use the result as a third operand.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
index 4b286a0e93cbd8..13546b6bf6fc3a 100644
--- a/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
@@ -2,8 +2,8 @@
; use the result as a third operand and results in wider elements than the
; operands had.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16
@llvm_mips_dpadd_s_h_ARG3 = global <16 x i8> <i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3r_splat.ll b/llvm/test/CodeGen/Mips/msa/3r_splat.ll
index e8d9d23fa9b492..c8c7f0585412c3 100644
--- a/llvm/test/CodeGen/Mips/msa/3r_splat.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r_splat.ll
@@ -1,9 +1,9 @@
; Test the MSA splat intrinsics that are encoded with the 3R instruction
; format.
-; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefix=MIPS32 %s
-; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefix=MIPS32 %s
@llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf.ll b/llvm/test/CodeGen/Mips/msa/3rf.ll
index 9bae9ba530453d..36114fa9094b53 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
index 6142ada9fef91c..94c66715035a3e 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; use the result as a third operand.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
index f397644df39190..049042df39c112 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; use the result as a third operand and perform fixed-point operations.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
index 70da349d0f13e2..b0ee043b8f3717 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
@@ -1,8 +1,8 @@
; Test the MSA floating-point conversion intrinsics that are encoded with the
; 3RF instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
index 4c1328b49be56a..49e31465d84775 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; take an integer as an operand.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
index 7e186beb320507..7c1b2ffd100c34 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; produce an integer as a result.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/3rf_q.ll b/llvm/test/CodeGen/Mips/msa/3rf_q.ll
index 5e3358ccd063a5..fcae0713056e3d 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_q.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_q.ll
@@ -1,8 +1,8 @@
; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
; format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic.ll b/llvm/test/CodeGen/Mips/msa/arithmetic.ll
index 62fd35a69abaa4..a262ce183d74ed 100644
--- a/llvm/test/CodeGen/Mips/msa/arithmetic.ll
+++ b/llvm/test/CodeGen/Mips/msa/arithmetic.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
define void @add_v16i8(ptr %c, ptr %a, ptr %b) nounwind {
; ALL-LABEL: add_v16i8:
diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
index b2ce43171aeb1a..84496e012908a0 100644
--- a/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @add_v4f32(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK: add_v4f32:
diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations.ll b/llvm/test/CodeGen/Mips/msa/basic_operations.ll
index 1f6c430a932e0c..820259d7c7bc25 100644
--- a/llvm/test/CodeGen/Mips/msa/basic_operations.ll
+++ b/llvm/test/CodeGen/Mips/msa/basic_operations.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=O32,O32-BE %s
-; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -relocation-model=pic \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=O32,O32-LE %s
-; RUN: llc -march=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \
; RUN: -relocation-model=pic -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=N32,N32-BE %s
-; RUN: llc -march=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r5 -target-abi n32 -mattr=+msa,+fp64 \
; RUN: -relocation-model=pic -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=N32,N32-LE %s
-; RUN: llc -march=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=N64,N64-BE %s
-; RUN: llc -march=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r5 -mattr=+msa,+fp64 -relocation-model=pic \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=N64,N64-LE %s
diff --git a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
index 83ac551c8dc94b..a1b5215d3ea20d 100644
--- a/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
@@ -1,14 +1,14 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,O32 %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,O32 %s
-; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,N32 %s
-; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,N64 %s
-; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,N64 %s
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
diff --git a/llvm/test/CodeGen/Mips/msa/bit.ll b/llvm/test/CodeGen/Mips/msa/bit.ll
index 1b2012cec5f5a2..cc200eb9158669 100644
--- a/llvm/test/CodeGen/Mips/msa/bit.ll
+++ b/llvm/test/CodeGen/Mips/msa/bit.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the BIT instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/bitcast.ll b/llvm/test/CodeGen/Mips/msa/bitcast.ll
index 11c5a5fb42c799..12b118b0af53c5 100644
--- a/llvm/test/CodeGen/Mips/msa/bitcast.ll
+++ b/llvm/test/CodeGen/Mips/msa/bitcast.ll
@@ -1,7 +1,7 @@
; Test the bitcast operation for big-endian and little-endian.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s
define void @v16i8_to_v16i8(ptr %src, ptr %dst) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/msa/bitwise.ll b/llvm/test/CodeGen/Mips/msa/bitwise.ll
index c7790b71b96364..def77c8c47266f 100644
--- a/llvm/test/CodeGen/Mips/msa/bitwise.ll
+++ b/llvm/test/CodeGen/Mips/msa/bitwise.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPS
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=CHECK,MIPSEL
define void @and_v16i8(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: and_v16i8:
diff --git a/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll b/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
index ab2c36eae67daf..5bc8b27bf33661 100644
--- a/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
+++ b/llvm/test/CodeGen/Mips/msa/bmzi_bmnzi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>, align 16
@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> zeroinitializer, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/compare.ll b/llvm/test/CodeGen/Mips/msa/compare.ll
index a3910bde8cd1c5..5027c45ecf52e5 100644
--- a/llvm/test/CodeGen/Mips/msa/compare.ll
+++ b/llvm/test/CodeGen/Mips/msa/compare.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @ceq_v16i8(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK: ceq_v16i8:
diff --git a/llvm/test/CodeGen/Mips/msa/compare_float.ll b/llvm/test/CodeGen/Mips/msa/compare_float.ll
index cd4924eca44cda..396d8c421d1237 100644
--- a/llvm/test/CodeGen/Mips/msa/compare_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/compare_float.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind
diff --git a/llvm/test/CodeGen/Mips/msa/elm_copy.ll b/llvm/test/CodeGen/Mips/msa/elm_copy.ll
index 6e0ee2da0920ff..232f09fc3a668f 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_copy.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_copy.ll
@@ -1,13 +1,13 @@
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are element extraction operations.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
index 7d44620e25790f..dab5e0c1b93a32 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
@@ -1,8 +1,8 @@
; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
; instruction format).
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -verify-machineinstrs < %s | FileCheck %s
define i32 @msa_ir_cfcmsa_test() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/msa/elm_insv.ll b/llvm/test/CodeGen/Mips/msa/elm_insv.ll
index 6c00483cf65375..b5b22fd8ee0c9f 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_insv.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_insv.ll
@@ -1,13 +1,13 @@
; Test the MSA element insertion intrinsics that are encoded with the ELM
; instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
-; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64
@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/elm_move.ll b/llvm/test/CodeGen/Mips/msa/elm_move.ll
index 4065fc753a55e2..9e13d52f28bc2e 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_move.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_move.ll
@@ -1,8 +1,8 @@
; Test the MSA move intrinsics (which are encoded with the ELM instruction
; format).
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
index 548cdf394ac85d..330da8b04469ee 100644
--- a/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
+++ b/llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are either shifts or slides.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sldi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
index 20894645286618..dcc64f58c56465 100644
--- a/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
+++ b/llvm/test/CodeGen/Mips/msa/emergency-spill.mir
@@ -1,4 +1,4 @@
-# RUN: llc %s -start-after=shrink-wrap -march=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null
+# RUN: llc %s -start-after=shrink-wrap -mtriple=mips64 -mcpu=mips64r6 -mattr=+fp64,+msa -o /dev/null
# Test that estimated size of the stack leads to the creation of an emergency
# spill when MSA is in use. Previously, this test case would fail during
diff --git a/llvm/test/CodeGen/Mips/msa/endian.ll b/llvm/test/CodeGen/Mips/msa/endian.ll
index 63aa3f6e187247..e7ed31d1452707 100644
--- a/llvm/test/CodeGen/Mips/msa/endian.ll
+++ b/llvm/test/CodeGen/Mips/msa/endian.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=BIGENDIAN %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck -check-prefix=LITENDIAN %s
@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
@v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
diff --git a/llvm/test/CodeGen/Mips/msa/fexuprl.ll b/llvm/test/CodeGen/Mips/msa/fexuprl.ll
index abd9d164d7c6b4..e25ae39e7e4eb4 100644
--- a/llvm/test/CodeGen/Mips/msa/fexuprl.ll
+++ b/llvm/test/CodeGen/Mips/msa/fexuprl.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -mattr=+fp64,+msa | FileCheck %s
; Test that fexup[rl].w don't crash LLVM during type legalization.
diff --git a/llvm/test/CodeGen/Mips/msa/frameindex.ll b/llvm/test/CodeGen/Mips/msa/frameindex.ll
index 1ee527bd88a4d2..4d7fc78595f57c 100644
--- a/llvm/test/CodeGen/Mips/msa/frameindex.ll
+++ b/llvm/test/CodeGen/Mips/msa/frameindex.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
define void @loadstore_v16i8_near() nounwind {
; CHECK: loadstore_v16i8_near:
diff --git a/llvm/test/CodeGen/Mips/msa/i10.ll b/llvm/test/CodeGen/Mips/msa/i10.ll
index e130d6df4b90cb..a9f95df0d0e833 100644
--- a/llvm/test/CodeGen/Mips/msa/i10.ll
+++ b/llvm/test/CodeGen/Mips/msa/i10.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I10 instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/i5-a.ll b/llvm/test/CodeGen/Mips/msa/i5-a.ll
index 7fd14da4b5f064..b46d0afcb8304d 100644
--- a/llvm/test/CodeGen/Mips/msa/i5-a.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5-a.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'a'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/i5-b.ll b/llvm/test/CodeGen/Mips/msa/i5-b.ll
index 4a36bfe540d147..1aff85d3327bc4 100644
--- a/llvm/test/CodeGen/Mips/msa/i5-b.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5-b.ll
@@ -2,8 +2,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'b'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/i5-c.ll b/llvm/test/CodeGen/Mips/msa/i5-c.ll
index 96f5e6286276a6..fb4a21bf4ed3c6 100644
--- a/llvm/test/CodeGen/Mips/msa/i5-c.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5-c.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'c'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceqi_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/i5-m.ll b/llvm/test/CodeGen/Mips/msa/i5-m.ll
index 74599185963a6d..60ed8b7c86165e 100644
--- a/llvm/test/CodeGen/Mips/msa/i5-m.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5-m.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'm'
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maxi_s_b_RES1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/i5-s.ll b/llvm/test/CodeGen/Mips/msa/i5-s.ll
index 0ba71fa9acd3fc..754c4c57d75568 100644
--- a/llvm/test/CodeGen/Mips/msa/i5-s.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5-s.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 's'
diff --git a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
index e55799cf176670..66cb32eb88246f 100644
--- a/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format and
; are loads or stores.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/i8.ll b/llvm/test/CodeGen/Mips/msa/i8.ll
index 89f5725c17357d..e4c1affc701fb2 100644
--- a/llvm/test/CodeGen/Mips/msa/i8.ll
+++ b/llvm/test/CodeGen/Mips/msa/i8.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I8 instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll
index bbb76f3b8b6bfd..f8bb5b36c44c8d 100644
--- a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll
+++ b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1
+; RUN: not --crash llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1
; RUN: FileCheck %s < %t1
; Test that the immediate intrinsics with out of range values trigger an error.
diff --git a/llvm/test/CodeGen/Mips/msa/immediates.ll b/llvm/test/CodeGen/Mips/msa/immediates.ll
index 5808643aded1c7..ba1ae74f227b5f 100644
--- a/llvm/test/CodeGen/Mips/msa/immediates.ll
+++ b/llvm/test/CodeGen/Mips/msa/immediates.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck %s -check-prefixes=MSA,MSA32
-; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \
+; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n32 < %s \
; RUN: | FileCheck %s -check-prefix=MSA64N32
-; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \
+; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic -target-abi n64 < %s \
; RUN: | FileCheck %s -check-prefixes=MSA,MSA64N64
; Test that the immediate intrinsics don't crash LLVM.
diff --git a/llvm/test/CodeGen/Mips/msa/inline-asm.ll b/llvm/test/CodeGen/Mips/msa/inline-asm.ll
index f84b11e05387ed..a41f96047ba7af 100644
--- a/llvm/test/CodeGen/Mips/msa/inline-asm.ll
+++ b/llvm/test/CodeGen/Mips/msa/inline-asm.ll
@@ -1,6 +1,6 @@
; A basic inline assembly test
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@v4i32_r = global <4 x i32> zeroinitializer, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/ldr_str.ll b/llvm/test/CodeGen/Mips/msa/ldr_str.ll
index 74f84aa9bbd7a6..ff766491834e58 100644
--- a/llvm/test/CodeGen/Mips/msa/ldr_str.ll
+++ b/llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB
-; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB
-; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL
-; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB
+; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB
+; RUN: llc -mtriple=mipsel -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
; Test intrinsics for 4-byte and 8-byte MSA load and stores.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
index db2b52028a892e..d658dbdce639fe 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1704963983.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; "Unexpected illegal type!" assertion.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
index a220b9887f9019..77fa9f47152119 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s1935737938.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; `Opc && "Cannot copy registers"' assertion.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
index e27ca939d42daf..d4b80c63aea855 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2090927243-simplified.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a "Cannot select ..." error.
; This was because undef's are ignored when checking if a vector constant is a
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
index 91f2ca3d8d5045..cd20c98e2fe42d 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2501752154-simplified.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a "Cannot select ..." error.
; This happened because the legalizer treated undef's in the <4 x float>
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
index d1d2f0db69dcf2..596dc2594c9b14 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s2704903805.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA after dereferencing a null this pointer.
; It should at least successfully build.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
index c3158801bee575..137e7cf4efa6a4 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3861334421.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; "Don't know how to expand this condition!" unreachable.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
index ace3f54b33a37c..c8123e9a8c8e22 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3926023935.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; "Type for zero vector elements is not legal" assertion.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
index d88dfb6bd29ae0..cea8ac8f9fffa0 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s3997499501.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed to select instructions for extract_vector_elt for
; v4f32 on MSA.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
index de3f5a27eb4634..81d6830a19f162 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s449609655-simplified.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test is based on an llvm-stress generated test case with seed=449609655
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
index 0185c8d3eb336a..aad184962c44d5 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed for MSA with a
; `Num < NumOperands && "Invalid child # of SDNode!"' assertion.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
index ae02778783e36f..d3b65b5177e357 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed to select instructions for extract_vector_elt for
; v2f64 on MSA.
diff --git a/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll b/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
index 16900fbf48385b..8fc5de240650de 100644
--- a/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
+++ b/llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s
-; RUN: llc -march=mipsel < %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mips < %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s
+; RUN: llc -mtriple=mipsel < %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s
; This test originally failed to select code for a truncstore of a
; build_vector.
diff --git a/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll b/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll
index 3071a358d6dc19..8deff611f66b29 100644
--- a/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll
+++ b/llvm/test/CodeGen/Mips/msa/msa-nooddspreg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s
; Test that the register allocator honours +nooddspreg and does not pick an odd
; single precision subregister of an MSA register.
diff --git a/llvm/test/CodeGen/Mips/msa/nori.b.ll b/llvm/test/CodeGen/Mips/msa/nori.b.ll
index ea0d2a958a292f..3332dd34d2dec2 100644
--- a/llvm/test/CodeGen/Mips/msa/nori.b.ll
+++ b/llvm/test/CodeGen/Mips/msa/nori.b.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 < %s | FileCheck %s
; Test that simply checks if it will finish when value 255 (-1) appears as
; immediate in 'nori.b' instruction.
diff --git a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll
index 64f976c97a3589..cd52077173dc38 100644
--- a/llvm/test/CodeGen/Mips/msa/remat-ldi.ll
+++ b/llvm/test/CodeGen/Mips/msa/remat-ldi.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 -march=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s
+; RUN: llc -O3 -mtriple=mipsel -mcpu=mips32r6 -mattr=+fp64,+msa %s -o - | FileCheck %s
; Test that checks if spill for ldi can be avoided and instruction will be
; rematerialized.
diff --git a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
index 1f8572751c1a48..3f35a5be849ec2 100644
--- a/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
+++ b/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @ashr_v4i32(ptr %c) nounwind {
; CHECK-LABEL: ashr_v4i32:
diff --git a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
index 9312a05f569605..2636f37a06ae62 100644
--- a/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
+++ b/llvm/test/CodeGen/Mips/msa/shift_constant_pool.ll
@@ -1,13 +1,13 @@
; Test whether the following functions, with vectors featuring negative or values larger than the element
; bit size have their results of operations generated correctly when placed into constant pools
-; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s
-; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,MIPS64 %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefixes=ALL,MIPS32 %s
@llvm_mips_bclr_w_test_const_vec_res = global <4 x i32> zeroinitializer, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/shift_no_and.ll b/llvm/test/CodeGen/Mips/msa/shift_no_and.ll
index d975f43e0c06b2..58d20458afc745 100644
--- a/llvm/test/CodeGen/Mips/msa/shift_no_and.ll
+++ b/llvm/test/CodeGen/Mips/msa/shift_no_and.ll
@@ -1,7 +1,7 @@
; Test the absence of the andi.b / and.v instructions
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/shuffle.ll b/llvm/test/CodeGen/Mips/msa/shuffle.ll
index 61b42f5df441bb..e93bb7cdd11283 100644
--- a/llvm/test/CodeGen/Mips/msa/shuffle.ll
+++ b/llvm/test/CodeGen/Mips/msa/shuffle.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define void @vshf_v16i8_0(ptr %c, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: vshf_v16i8_0:
diff --git a/llvm/test/CodeGen/Mips/msa/special.ll b/llvm/test/CodeGen/Mips/msa/special.ll
index 3e392110cccfec..df19d94eeed327 100644
--- a/llvm/test/CodeGen/Mips/msa/special.ll
+++ b/llvm/test/CodeGen/Mips/msa/special.ll
@@ -1,12 +1,12 @@
; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+msa < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
-; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -mattr=+msa < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
diff --git a/llvm/test/CodeGen/Mips/msa/spill.ll b/llvm/test/CodeGen/Mips/msa/spill.ll
index 29f02920b10c6f..51759f917a32cc 100644
--- a/llvm/test/CodeGen/Mips/msa/spill.ll
+++ b/llvm/test/CodeGen/Mips/msa/spill.ll
@@ -1,8 +1,8 @@
; Test that the correct instruction is chosen for spill and reload by trying
; to have 33 live MSA registers simultaneously
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
define i32 @test_i8(ptr %p0, ptr %q1) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/msa/vec.ll b/llvm/test/CodeGen/Mips/msa/vec.ll
index cc4eba6c95bf1b..8f3a822704fea3 100644
--- a/llvm/test/CodeGen/Mips/msa/vec.ll
+++ b/llvm/test/CodeGen/Mips/msa/vec.ll
@@ -1,8 +1,8 @@
; Test the MSA intrinsics that are encoded with the VEC instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefix=ANYENDIAN %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s \
; RUN: | FileCheck -check-prefix=ANYENDIAN %s
@llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/msa/vecs10.ll b/llvm/test/CodeGen/Mips/msa/vecs10.ll
index ce61efc33f3a40..12da397a5d0186 100644
--- a/llvm/test/CodeGen/Mips/msa/vecs10.ll
+++ b/llvm/test/CodeGen/Mips/msa/vecs10.ll
@@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the VECS10 instruction format.
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
@llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
diff --git a/llvm/test/CodeGen/Mips/mul.ll b/llvm/test/CodeGen/Mips/mul.ll
index 41ea550dbce7a3..f5efed6415dc78 100644
--- a/llvm/test/CodeGen/Mips/mul.ll
+++ b/llvm/test/CodeGen/Mips/mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 5, align 4
@jjjj = global i32 -6, align 4
diff --git a/llvm/test/CodeGen/Mips/mulll.ll b/llvm/test/CodeGen/Mips/mulll.ll
index 08813809bd5f0e..c65c1bbd980c6b 100644
--- a/llvm/test/CodeGen/Mips/mulll.ll
+++ b/llvm/test/CodeGen/Mips/mulll.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i64 5, align 8
@jjjj = global i64 -6, align 8
diff --git a/llvm/test/CodeGen/Mips/mulull.ll b/llvm/test/CodeGen/Mips/mulull.ll
index 749adfa0557291..129054776a03ce 100644
--- a/llvm/test/CodeGen/Mips/mulull.ll
+++ b/llvm/test/CodeGen/Mips/mulull.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i64 5, align 8
@jjjj = global i64 6, align 8
diff --git a/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll b/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
index b3768b08874776..b03418dff6ccc1 100644
--- a/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
+++ b/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -O3 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -O3 < %s | FileCheck %s
; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-NACL
diff --git a/llvm/test/CodeGen/Mips/neg1.ll b/llvm/test/CodeGen/Mips/neg1.ll
index 7f35a9884a10c6..00d76be167bce6 100644
--- a/llvm/test/CodeGen/Mips/neg1.ll
+++ b/llvm/test/CodeGen/Mips/neg1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/nmadd.ll b/llvm/test/CodeGen/Mips/nmadd.ll
index 0fb534fbe3c704..57774b184d8c55 100644
--- a/llvm/test/CodeGen/Mips/nmadd.ll
+++ b/llvm/test/CodeGen/Mips/nmadd.ll
@@ -1,15 +1,15 @@
; Check whether nmadd/nmsub instructions are properly generated
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -enable-no-nans-fp-math -asm-show-inst | FileCheck %s -check-prefixes=ALL,CHECK-NM,CHECK-MM
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM
-; RUN: llc < %s -march=mips64el -mcpu=mips3 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM-64
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM
-; RUN: llc < %s -march=mipsel -mcpu=mips32r3 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=micromips -enable-no-nans-fp-math -asm-show-inst | FileCheck %s -check-prefixes=ALL,CHECK-NM,CHECK-MM
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips4 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM-64
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM
+; RUN: llc < %s -mtriple=mips64el -mcpu=mips3 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM-64
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NOT-NM
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r3 -mattr=micromips -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,CHECK-NM
define float @add1(float %f, float %g, float %h) local_unnamed_addr #0 {
entry:
diff --git a/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll b/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll
index a71a645a401745..7c9f375cbb9ada 100644
--- a/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll
+++ b/llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,-nooddspreg \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,-nooddspreg \
; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,ODDSPREG
-; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg \
+; RUN: llc -mtriple=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg \
; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,NOODDSPREG
diff --git a/llvm/test/CodeGen/Mips/not1.ll b/llvm/test/CodeGen/Mips/not1.ll
index 30b6f45a3b2188..7893cb08f719d1 100644
--- a/llvm/test/CodeGen/Mips/not1.ll
+++ b/llvm/test/CodeGen/Mips/not1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@x = global i32 65504, align 4
@y = global i32 60929, align 4
diff --git a/llvm/test/CodeGen/Mips/null.ll b/llvm/test/CodeGen/Mips/null.ll
index 67e346d959f96f..9f7c6eace93abe 100644
--- a/llvm/test/CodeGen/Mips/null.ll
+++ b/llvm/test/CodeGen/Mips/null.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 < %s | FileCheck %s -check-prefix=16
define i32 @main() nounwind {
diff --git a/llvm/test/CodeGen/Mips/o32_cc.ll b/llvm/test/CodeGen/Mips/o32_cc.ll
index cef1290a75bda0..fb6529ebe14723 100644
--- a/llvm/test/CodeGen/Mips/o32_cc.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=ALL %s
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck -check-prefix=ALL %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s
; $f12, $f14
; ALL-LABEL: testlowercall0:
diff --git a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
index 750457eac5e926..f509f49a341a96 100644
--- a/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -pre-RA-sched=source < %s | FileCheck %s
; All test functions do the same thing - they return the first variable
; argument.
diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll
index 11e93736f5cf03..09a35e05cb4544 100644
--- a/llvm/test/CodeGen/Mips/octeon.ll
+++ b/llvm/test/CodeGen/Mips/octeon.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
-; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
-; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC
+; RUN: llc -O1 < %s -mtriple=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
+; RUN: llc -O1 < %s -mtriple=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
+; RUN: llc -O1 < %s -mtriple=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC
define i64 @addi64(i64 %a, i64 %b) nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/octeon_popcnt.ll b/llvm/test/CodeGen/Mips/octeon_popcnt.ll
index 13488ed59504c1..84fb0bdc5afcd5 100644
--- a/llvm/test/CodeGen/Mips/octeon_popcnt.ll
+++ b/llvm/test/CodeGen/Mips/octeon_popcnt.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O1 -march=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON
-; RUN: llc -O1 -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64
+; RUN: llc -O1 -mtriple=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON
+; RUN: llc -O1 -mtriple=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64
define i8 @cnt8(i8 %x) nounwind readnone {
%cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
diff --git a/llvm/test/CodeGen/Mips/optimize-fp-math.ll b/llvm/test/CodeGen/Mips/optimize-fp-math.ll
index 7886f29f5cef2b..7124013714bb12 100644
--- a/llvm/test/CodeGen/Mips/optimize-fp-math.ll
+++ b/llvm/test/CodeGen/Mips/optimize-fp-math.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
; 32-LABEL: test_sqrtf_float_:
; 32: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
diff --git a/llvm/test/CodeGen/Mips/or1.ll b/llvm/test/CodeGen/Mips/or1.ll
index 94e314491a7c88..2657270bee9477 100644
--- a/llvm/test/CodeGen/Mips/or1.ll
+++ b/llvm/test/CodeGen/Mips/or1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@x = global i32 65504, align 4
@y = global i32 60929, align 4
diff --git a/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll b/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
index 730e01d8f114d2..63a730c1861675 100644
--- a/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
+++ b/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -regalloc=pbqp <%s > %t
+; RUN: llc -mtriple=mips -regalloc=pbqp <%s > %t
; ModuleID = 'bugpoint-reduced-simplified.bc'
; Function Attrs: nounwind
diff --git a/llvm/test/CodeGen/Mips/pr33682.ll b/llvm/test/CodeGen/Mips/pr33682.ll
index 93ef4f900db07f..545b25c18fae85 100644
--- a/llvm/test/CodeGen/Mips/pr33682.ll
+++ b/llvm/test/CodeGen/Mips/pr33682.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,BE
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,LE
+; RUN: llc -mtriple=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,BE
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,LE
; Verify visitTRUNCATE respects endianness when transforming trunc to insert_vector_elt.
diff --git a/llvm/test/CodeGen/Mips/pr33978.ll b/llvm/test/CodeGen/Mips/pr33978.ll
index 921fa543cfda9b..136de5edfd337b 100644
--- a/llvm/test/CodeGen/Mips/pr33978.ll
+++ b/llvm/test/CodeGen/Mips/pr33978.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=mips32r2 < %s -o /dev/null
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s -o /dev/null
; Test that SelectionDAG does not crash during DAGCombine when two pointers
; to the stack match with
diff ering bases and offsets when expanding memcpy.
diff --git a/llvm/test/CodeGen/Mips/prevent-hoisting.ll b/llvm/test/CodeGen/Mips/prevent-hoisting.ll
index e44b895689b498..05b7e964c9ae00 100644
--- a/llvm/test/CodeGen/Mips/prevent-hoisting.ll
+++ b/llvm/test/CodeGen/Mips/prevent-hoisting.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -O3 -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -O3 -relocation-model=pic < %s | FileCheck %s
; MIPS direct branches implicitly define register $at. This test makes sure that
diff --git a/llvm/test/CodeGen/Mips/private.ll b/llvm/test/CodeGen/Mips/private.ll
index e93c2d7fc5d9ee..be936ddde00728 100644
--- a/llvm/test/CodeGen/Mips/private.ll
+++ b/llvm/test/CodeGen/Mips/private.ll
@@ -1,6 +1,6 @@
; Test to make sure that the 'private' is used correctly.
;
-; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -relocation-model=pic < %s | FileCheck %s
define private void @foo() {
; CHECK-LABEL: foo:
diff --git a/llvm/test/CodeGen/Mips/ra-allocatable.ll b/llvm/test/CodeGen/Mips/ra-allocatable.ll
index dcbf90393576a3..52ec4cf77ce447 100644
--- a/llvm/test/CodeGen/Mips/ra-allocatable.ll
+++ b/llvm/test/CodeGen/Mips/ra-allocatable.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=mipsel | FileCheck %s
+; RUN: llc < %s -mtriple=mipsel | FileCheck %s
@a0 = external global i32
@b0 = external global ptr
diff --git a/llvm/test/CodeGen/Mips/rem.ll b/llvm/test/CodeGen/Mips/rem.ll
index 525ab633ca019e..c7b4da98d63e48 100644
--- a/llvm/test/CodeGen/Mips/rem.ll
+++ b/llvm/test/CodeGen/Mips/rem.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 103, align 4
@jjjj = global i32 -4, align 4
diff --git a/llvm/test/CodeGen/Mips/remat-immed-load.ll b/llvm/test/CodeGen/Mips/remat-immed-load.ll
index 3d37b43bbc6305..ec32acb2b78f76 100644
--- a/llvm/test/CodeGen/Mips/remat-immed-load.ll
+++ b/llvm/test/CodeGen/Mips/remat-immed-load.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=64
define void @f0() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/remu.ll b/llvm/test/CodeGen/Mips/remu.ll
index 3d5f5d7629d958..6008d2d06a6404 100644
--- a/llvm/test/CodeGen/Mips/remu.ll
+++ b/llvm/test/CodeGen/Mips/remu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 103, align 4
@jjjj = global i32 4, align 4
diff --git a/llvm/test/CodeGen/Mips/return-vector.ll b/llvm/test/CodeGen/Mips/return-vector.ll
index c59695d18734e4..c4fe4467bdcceb 100644
--- a/llvm/test/CodeGen/Mips/return-vector.ll
+++ b/llvm/test/CodeGen/Mips/return-vector.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
; Check that function accesses vector return value from stack in cases when
diff --git a/llvm/test/CodeGen/Mips/return_address.ll b/llvm/test/CodeGen/Mips/return_address.ll
index 65b4ff5733f434..0d02c1b3a92029 100644
--- a/llvm/test/CodeGen/Mips/return_address.ll
+++ b/llvm/test/CodeGen/Mips/return_address.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -verify-machineinstrs < %s | FileCheck %s
define ptr @f1() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/return_address_err.ll b/llvm/test/CodeGen/Mips/return_address_err.ll
index bf2ab3c1648862..9a8fe1d0545f54 100644
--- a/llvm/test/CodeGen/Mips/return_address_err.ll
+++ b/llvm/test/CodeGen/Mips/return_address_err.ll
@@ -1,4 +1,4 @@
-; RUN: not llc -march=mips < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=mips < %s 2>&1 | FileCheck %s
declare ptr @llvm.returnaddress(i32) nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/rotate.ll b/llvm/test/CodeGen/Mips/rotate.ll
index 77936b7bef9b64..9063cc163891fd 100644
--- a/llvm/test/CodeGen/Mips/rotate.ll
+++ b/llvm/test/CodeGen/Mips/rotate.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \
; RUN: -check-prefix=MM32
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \
; RUN: -check-prefix=MM32
; CHECK: rotrv $2, $4
diff --git a/llvm/test/CodeGen/Mips/sb1.ll b/llvm/test/CodeGen/Mips/sb1.ll
index 8b79f39d2c70f6..daecafc8418e06 100644
--- a/llvm/test/CodeGen/Mips/sb1.ll
+++ b/llvm/test/CodeGen/Mips/sb1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 97, align 4
@c = common global i8 0, align 1
diff --git a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
index a81393b0b08070..6520bcdc0622a1 100644
--- a/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
+++ b/llvm/test/CodeGen/Mips/selTBteqzCmpi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@i = global i32 1, align 4
@j = global i32 2, align 4
diff --git a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
index e703e317a0fb88..9c3089d56ae324 100644
--- a/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
+++ b/llvm/test/CodeGen/Mips/selTBtnezCmpi.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@i = global i32 1, align 4
@j = global i32 2, align 4
diff --git a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll
index 132d5ed7702077..1e32d9f2be1f68 100644
--- a/llvm/test/CodeGen/Mips/selTBtnezSlti.ll
+++ b/llvm/test/CodeGen/Mips/selTBtnezSlti.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@i = global i32 1, align 4
@j = global i32 2, align 4
diff --git a/llvm/test/CodeGen/Mips/selectcc.ll b/llvm/test/CodeGen/Mips/selectcc.ll
index 1bec29e8bcd5f4..532fc006ccd451 100644
--- a/llvm/test/CodeGen/Mips/selectcc.ll
+++ b/llvm/test/CodeGen/Mips/selectcc.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s
-; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED
-; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -relocation-model=pic < %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic < %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED
@gf0 = external global float
@gf1 = external global float
diff --git a/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll b/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll
index 9632eac84419c9..048a362ab1322e 100644
--- a/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll
+++ b/llvm/test/CodeGen/Mips/selectiondag-optlevel.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0
-; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2
+; RUN: llc -mtriple=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0
+; RUN: llc -mtriple=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2
; At -O0, DAGCombine won't try to merge these consecutive loads but it will at
; -O2.
diff --git a/llvm/test/CodeGen/Mips/seleq.ll b/llvm/test/CodeGen/Mips/seleq.ll
index ecbeb2b51e3d73..fcf12202b40ca3 100644
--- a/llvm/test/CodeGen/Mips/seleq.ll
+++ b/llvm/test/CodeGen/Mips/seleq.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/seleqk.ll b/llvm/test/CodeGen/Mips/seleqk.ll
index 911c6f1996b674..62924946717173 100644
--- a/llvm/test/CodeGen/Mips/seleqk.ll
+++ b/llvm/test/CodeGen/Mips/seleqk.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selgek.ll b/llvm/test/CodeGen/Mips/selgek.ll
index a909bb543538b7..9c9e77ae236a7a 100644
--- a/llvm/test/CodeGen/Mips/selgek.ll
+++ b/llvm/test/CodeGen/Mips/selgek.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selgt.ll b/llvm/test/CodeGen/Mips/selgt.ll
index 30d7f8ff3a6950..a59c89f875173c 100644
--- a/llvm/test/CodeGen/Mips/selgt.ll
+++ b/llvm/test/CodeGen/Mips/selgt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selle.ll b/llvm/test/CodeGen/Mips/selle.ll
index bccc3de56705ea..59fe279966183b 100644
--- a/llvm/test/CodeGen/Mips/selle.ll
+++ b/llvm/test/CodeGen/Mips/selle.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selltk.ll b/llvm/test/CodeGen/Mips/selltk.ll
index b070c301b01995..2661ea1dead265 100644
--- a/llvm/test/CodeGen/Mips/selltk.ll
+++ b/llvm/test/CodeGen/Mips/selltk.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selne.ll b/llvm/test/CodeGen/Mips/selne.ll
index 6fe9e482798771..0d117c4d766011 100644
--- a/llvm/test/CodeGen/Mips/selne.ll
+++ b/llvm/test/CodeGen/Mips/selne.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selnek.ll b/llvm/test/CodeGen/Mips/selnek.ll
index f38ab246e60f47..ecc68842cc623a 100644
--- a/llvm/test/CodeGen/Mips/selnek.ll
+++ b/llvm/test/CodeGen/Mips/selnek.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/selpat.ll b/llvm/test/CodeGen/Mips/selpat.ll
index d765acbab33a1a..ad263bb41295b8 100644
--- a/llvm/test/CodeGen/Mips/selpat.ll
+++ b/llvm/test/CodeGen/Mips/selpat.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@t = global i32 10, align 4
@f = global i32 199, align 4
diff --git a/llvm/test/CodeGen/Mips/setcc-se.ll b/llvm/test/CodeGen/Mips/setcc-se.ll
index 0e74db3c67866c..26fd2845f0817a 100644
--- a/llvm/test/CodeGen/Mips/setcc-se.ll
+++ b/llvm/test/CodeGen/Mips/setcc-se.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
@g1 = external global i32
diff --git a/llvm/test/CodeGen/Mips/seteq.ll b/llvm/test/CodeGen/Mips/seteq.ll
index 37fd1634f796aa..8bbde5de812c83 100644
--- a/llvm/test/CodeGen/Mips/seteq.ll
+++ b/llvm/test/CodeGen/Mips/seteq.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/seteqz.ll b/llvm/test/CodeGen/Mips/seteqz.ll
index c71ed1d91f72ba..006752d6e28df8 100644
--- a/llvm/test/CodeGen/Mips/seteqz.ll
+++ b/llvm/test/CodeGen/Mips/seteqz.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 0, align 4
@j = global i32 99, align 4
diff --git a/llvm/test/CodeGen/Mips/setge.ll b/llvm/test/CodeGen/Mips/setge.ll
index 6fb549e24b3fa4..e6021150ab7d45 100644
--- a/llvm/test/CodeGen/Mips/setge.ll
+++ b/llvm/test/CodeGen/Mips/setge.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setgek.ll b/llvm/test/CodeGen/Mips/setgek.ll
index 661a3f160e3259..066b65b8be326c 100644
--- a/llvm/test/CodeGen/Mips/setgek.ll
+++ b/llvm/test/CodeGen/Mips/setgek.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@k = global i32 10, align 4
@r1 = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/setle.ll b/llvm/test/CodeGen/Mips/setle.ll
index 35453b8f5f6afa..ecd779cc04b003 100644
--- a/llvm/test/CodeGen/Mips/setle.ll
+++ b/llvm/test/CodeGen/Mips/setle.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setlt.ll b/llvm/test/CodeGen/Mips/setlt.ll
index fcf9a25be72c01..234d1bc2b3c209 100644
--- a/llvm/test/CodeGen/Mips/setlt.ll
+++ b/llvm/test/CodeGen/Mips/setlt.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setltk.ll b/llvm/test/CodeGen/Mips/setltk.ll
index 95aa9ea07d2455..4be83bb49541e0 100644
--- a/llvm/test/CodeGen/Mips/setltk.ll
+++ b/llvm/test/CodeGen/Mips/setltk.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 -5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setne.ll b/llvm/test/CodeGen/Mips/setne.ll
index d9396b1bf77546..5a37c88ea59b06 100644
--- a/llvm/test/CodeGen/Mips/setne.ll
+++ b/llvm/test/CodeGen/Mips/setne.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@i = global i32 1, align 4
@j = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setuge.ll b/llvm/test/CodeGen/Mips/setuge.ll
index afdd4ef733758a..121daf32724693 100644
--- a/llvm/test/CodeGen/Mips/setuge.ll
+++ b/llvm/test/CodeGen/Mips/setuge.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setugt.ll b/llvm/test/CodeGen/Mips/setugt.ll
index afe4e4b09c7818..2a08d80e0f4264 100644
--- a/llvm/test/CodeGen/Mips/setugt.ll
+++ b/llvm/test/CodeGen/Mips/setugt.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setule.ll b/llvm/test/CodeGen/Mips/setule.ll
index 024e7701fad4dd..63ee5257ec9a93 100644
--- a/llvm/test/CodeGen/Mips/setule.ll
+++ b/llvm/test/CodeGen/Mips/setule.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setult.ll b/llvm/test/CodeGen/Mips/setult.ll
index ef354ec0971e45..0272dd300b1539 100644
--- a/llvm/test/CodeGen/Mips/setult.ll
+++ b/llvm/test/CodeGen/Mips/setult.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/setultk.ll b/llvm/test/CodeGen/Mips/setultk.ll
index 9801d388d22322..8f06fb324b5aa4 100644
--- a/llvm/test/CodeGen/Mips/setultk.ll
+++ b/llvm/test/CodeGen/Mips/setultk.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
@j = global i32 5, align 4
@k = global i32 10, align 4
diff --git a/llvm/test/CodeGen/Mips/sh1.ll b/llvm/test/CodeGen/Mips/sh1.ll
index 6bfa9f56231f5a..d3bdc15eedc3e6 100644
--- a/llvm/test/CodeGen/Mips/sh1.ll
+++ b/llvm/test/CodeGen/Mips/sh1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 97, align 4
@s = common global i16 0, align 2
diff --git a/llvm/test/CodeGen/Mips/shift-parts.ll b/llvm/test/CodeGen/Mips/shift-parts.ll
index 38cbf28108caeb..c77ec0249ae103 100644
--- a/llvm/test/CodeGen/Mips/shift-parts.ll
+++ b/llvm/test/CodeGen/Mips/shift-parts.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
define i64 @shl0(i64 %a, i32 %b) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll b/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
index 4d15f428e44bea..b79d25dfe5ed70 100644
--- a/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
+++ b/llvm/test/CodeGen/Mips/sint-fp-store_pattern.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
@gint_ = external global i32
@gLL_ = external global i64
diff --git a/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll b/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll
index 3e2de21b63cae8..0f406f0695479f 100644
--- a/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll
+++ b/llvm/test/CodeGen/Mips/sitofp-selectcc-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
@foo12.d4 = internal unnamed_addr global double 0.000000e+00, align 8
diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
index 45807b2e48b0db..b87ee412038caf 100644
--- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s
+# RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s
# Test that the 'sll $zero, $zero, 0' is correctly recognized as a real
# instruction rather than some unimplemented opcode for the purposes of
diff --git a/llvm/test/CodeGen/Mips/sll1.ll b/llvm/test/CodeGen/Mips/sll1.ll
index bf36682100d9fb..79b8d4bf70b369 100644
--- a/llvm/test/CodeGen/Mips/sll1.ll
+++ b/llvm/test/CodeGen/Mips/sll1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10, align 4
@j = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/sll2.ll b/llvm/test/CodeGen/Mips/sll2.ll
index 5de0b561cc989c..c3d763f0551fa3 100644
--- a/llvm/test/CodeGen/Mips/sll2.ll
+++ b/llvm/test/CodeGen/Mips/sll2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10, align 4
@j = global i32 4, align 4
diff --git a/llvm/test/CodeGen/Mips/slt.ll b/llvm/test/CodeGen/Mips/slt.ll
index a17f5ab0e57dd7..01dc1299f4f13d 100644
--- a/llvm/test/CodeGen/Mips/slt.ll
+++ b/llvm/test/CodeGen/Mips/slt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
define i32 @slt(i32 signext %a) nounwind readnone {
%1 = icmp slt i32 %a, 7
diff --git a/llvm/test/CodeGen/Mips/spill-copy-acreg.ll b/llvm/test/CodeGen/Mips/spill-copy-acreg.ll
index ea24bebe3e5f98..71aab3832d0bfc 100644
--- a/llvm/test/CodeGen/Mips/spill-copy-acreg.ll
+++ b/llvm/test/CodeGen/Mips/spill-copy-acreg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=+dsp < %s
+; RUN: llc -mtriple=mipsel -mattr=+dsp < %s
@g1 = common global i64 0, align 8
@g2 = common global i64 0, align 8
diff --git a/llvm/test/CodeGen/Mips/sra1.ll b/llvm/test/CodeGen/Mips/sra1.ll
index 08286760d5cdae..ad8382f2387194 100644
--- a/llvm/test/CodeGen/Mips/sra1.ll
+++ b/llvm/test/CodeGen/Mips/sra1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 -354, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/sra2.ll b/llvm/test/CodeGen/Mips/sra2.ll
index 2dd966b0ff8439..50b00c935b9bb2 100644
--- a/llvm/test/CodeGen/Mips/sra2.ll
+++ b/llvm/test/CodeGen/Mips/sra2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 -354, align 4
@j = global i32 3, align 4
diff --git a/llvm/test/CodeGen/Mips/srl1.ll b/llvm/test/CodeGen/Mips/srl1.ll
index 21cdeda4af448a..e9fb916758a774 100644
--- a/llvm/test/CodeGen/Mips/srl1.ll
+++ b/llvm/test/CodeGen/Mips/srl1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10654, align 4
@j = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/srl2.ll b/llvm/test/CodeGen/Mips/srl2.ll
index b433893822dc5a..17895ff85d08d1 100644
--- a/llvm/test/CodeGen/Mips/srl2.ll
+++ b/llvm/test/CodeGen/Mips/srl2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10654, align 4
@j = global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/stack-alignment.ll b/llvm/test/CodeGen/Mips/stack-alignment.ll
index 2ae917f50be104..22275a53f38eda 100644
--- a/llvm/test/CodeGen/Mips/stack-alignment.ll
+++ b/llvm/test/CodeGen/Mips/stack-alignment.ll
@@ -1,12 +1,12 @@
; RUN: split-file %s %t
; RUN: cat %t/main.ll %t/_32.ll > %t/32.ll
-; RUN: llc -march=mipsel < %t/main.ll | FileCheck %s -check-prefix=32
-; RUN: llc -march=mipsel < %t/32.ll | FileCheck %s -check-prefix=A32-32
-; RUN: llc -march=mipsel -mattr=+fp64,+mips32r2 < %t/main.ll | FileCheck %s -check-prefix=32
-; RUN: llc -march=mips64el -mcpu=mips3 < %t/main.ll | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips4 < %t/main.ll | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 < %t/main.ll | FileCheck %s -check-prefix=64
-; RUN: llc -march=mips64el -mcpu=mips64 < %t/32.ll | FileCheck %s -check-prefix=A32-64
+; RUN: llc -mtriple=mipsel < %t/main.ll | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mipsel < %t/32.ll | FileCheck %s -check-prefix=A32-32
+; RUN: llc -mtriple=mipsel -mattr=+fp64,+mips32r2 < %t/main.ll | FileCheck %s -check-prefix=32
+; RUN: llc -mtriple=mips64el -mcpu=mips3 < %t/main.ll | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips4 < %t/main.ll | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %t/main.ll | FileCheck %s -check-prefix=64
+; RUN: llc -mtriple=mips64el -mcpu=mips64 < %t/32.ll | FileCheck %s -check-prefix=A32-64
;--- main.ll
; 32: addiu $sp, $sp, -8
diff --git a/llvm/test/CodeGen/Mips/stackcoloring.ll b/llvm/test/CodeGen/Mips/stackcoloring.ll
index aeedbc8abccd0d..12ccabd52e4767 100644
--- a/llvm/test/CodeGen/Mips/stackcoloring.ll
+++ b/llvm/test/CodeGen/Mips/stackcoloring.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic < %s | FileCheck %s
@g1 = external global ptr
diff --git a/llvm/test/CodeGen/Mips/stchar.ll b/llvm/test/CodeGen/Mips/stchar.ll
index 0a2dfbe1183a60..f9bb1b0c2fb117 100644
--- a/llvm/test/CodeGen/Mips/stchar.ll
+++ b/llvm/test/CodeGen/Mips/stchar.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b
@.str = private unnamed_addr constant [9 x i8] c"%hd %c \0A\00", align 1
@sp = common global ptr null, align 4
diff --git a/llvm/test/CodeGen/Mips/stldst.ll b/llvm/test/CodeGen/Mips/stldst.ll
index 0208d62b4f8ab6..6f1ed4c78f3ba6 100644
--- a/llvm/test/CodeGen/Mips/stldst.ll
+++ b/llvm/test/CodeGen/Mips/stldst.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@kkkk = global i32 67, align 4
@llll = global i32 33, align 4
diff --git a/llvm/test/CodeGen/Mips/sub1.ll b/llvm/test/CodeGen/Mips/sub1.ll
index 8e30a1732ce4ea..8f1e941b99d5be 100644
--- a/llvm/test/CodeGen/Mips/sub1.ll
+++ b/llvm/test/CodeGen/Mips/sub1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10, align 4
@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
diff --git a/llvm/test/CodeGen/Mips/sub2.ll b/llvm/test/CodeGen/Mips/sub2.ll
index 5d6296d279e464..c2a404dbc5c382 100644
--- a/llvm/test/CodeGen/Mips/sub2.ll
+++ b/llvm/test/CodeGen/Mips/sub2.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@i = global i32 10, align 4
@j = global i32 20, align 4
diff --git a/llvm/test/CodeGen/Mips/swzero.ll b/llvm/test/CodeGen/Mips/swzero.ll
index cc17a1559db96f..6059839e2de180 100644
--- a/llvm/test/CodeGen/Mips/swzero.ll
+++ b/llvm/test/CodeGen/Mips/swzero.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
%struct.unaligned = type <{ i32 }>
diff --git a/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll b/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll
index dda24a2ca163fd..c7ad22cf427b5f 100644
--- a/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll
+++ b/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll
@@ -1,8 +1,8 @@
-; RUN: llc -march=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \
+; RUN: llc -mtriple=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \
; RUN: %s -check-prefix=MIPS32
-; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64
-; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64
diff --git a/llvm/test/CodeGen/Mips/thread-pointer.ll b/llvm/test/CodeGen/Mips/thread-pointer.ll
index b460d6dd0a18b3..30d3c9385b9800 100644
--- a/llvm/test/CodeGen/Mips/thread-pointer.ll
+++ b/llvm/test/CodeGen/Mips/thread-pointer.ll
@@ -1,7 +1,7 @@
-; RUN: llc -march=mips < %s | FileCheck %s
-; RUN: llc -march=mips64 < %s | FileCheck %s
-; RUN: llc -march=mipsel < %s | FileCheck %s
-; RUN: llc -march=mips64el < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips64 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck %s
+; RUN: llc -mtriple=mips64el < %s | FileCheck %s
declare ptr @llvm.thread.pointer() nounwind readnone
diff --git a/llvm/test/CodeGen/Mips/tls-alias.ll b/llvm/test/CodeGen/Mips/tls-alias.ll
index 18428308807780..a2ba2250995f8c 100644
--- a/llvm/test/CodeGen/Mips/tls-alias.ll
+++ b/llvm/test/CodeGen/Mips/tls-alias.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -relocation-model=pic -disable-mips-delay-filler < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -relocation-model=pic -disable-mips-delay-filler < %s | FileCheck %s
@foo = thread_local global i32 42
@bar = hidden thread_local alias i32, ptr @foo
diff --git a/llvm/test/CodeGen/Mips/tnaked.ll b/llvm/test/CodeGen/Mips/tnaked.ll
index 803fef965bb171..ac54f2faae3f51 100644
--- a/llvm/test/CodeGen/Mips/tnaked.ll
+++ b/llvm/test/CodeGen/Mips/tnaked.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple=mipsel < %s -verify-machineinstrs | FileCheck %s
define void @tnaked() #0 {
diff --git a/llvm/test/CodeGen/Mips/trap.ll b/llvm/test/CodeGen/Mips/trap.ll
index beb4b894632b8e..e824d01d5f7c68 100644
--- a/llvm/test/CodeGen/Mips/trap.ll
+++ b/llvm/test/CodeGen/Mips/trap.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck %s
declare void @llvm.trap()
diff --git a/llvm/test/CodeGen/Mips/uitofp.ll b/llvm/test/CodeGen/Mips/uitofp.ll
index 08cd692deb3ca7..1682a627155ace 100644
--- a/llvm/test/CodeGen/Mips/uitofp.ll
+++ b/llvm/test/CodeGen/Mips/uitofp.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+single-float < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mattr=+single-float < %s | FileCheck %s
define void @f0() nounwind {
; CHECK-LABEL: f0:
diff --git a/llvm/test/CodeGen/Mips/ul1.ll b/llvm/test/CodeGen/Mips/ul1.ll
index 5e3fc20dd39f8d..f21050aec11f16 100644
--- a/llvm/test/CodeGen/Mips/ul1.ll
+++ b/llvm/test/CodeGen/Mips/ul1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
%struct.ua = type <{ i16, i32 }>
@foo = common global %struct.ua zeroinitializer, align 1
diff --git a/llvm/test/CodeGen/Mips/unaligned-memops.ll b/llvm/test/CodeGen/Mips/unaligned-memops.ll
index 58475a216d6ccc..caaa212a40cd50 100644
--- a/llvm/test/CodeGen/Mips/unaligned-memops.ll
+++ b/llvm/test/CodeGen/Mips/unaligned-memops.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS
+; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS
; Test that the correct ISA version of the unaligned memory operations is
; selected up front.
diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll
index da57b92e8f6df8..030c6405227521 100644
--- a/llvm/test/CodeGen/Mips/unalignedload.ll
+++ b/llvm/test/CodeGen/Mips/unalignedload.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL
-; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL
+; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EL
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32-EB
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EL
+; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=MIPS32R6-EB
%struct.S2 = type { %struct.S1, %struct.S1 }
%struct.S1 = type { i8, i8 }
diff --git a/llvm/test/CodeGen/Mips/vector-load-store.ll b/llvm/test/CodeGen/Mips/vector-load-store.ll
index 142f383b72c7a5..daa40229121622 100644
--- a/llvm/test/CodeGen/Mips/vector-load-store.ll
+++ b/llvm/test/CodeGen/Mips/vector-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=+dsp < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel -mattr=+dsp < %s | FileCheck %s
@g1 = common global <2 x i16> zeroinitializer, align 4
@g0 = common global <2 x i16> zeroinitializer, align 4
diff --git a/llvm/test/CodeGen/Mips/vector-setcc.ll b/llvm/test/CodeGen/Mips/vector-setcc.ll
index f8e6d5e675202d..57787c937a04f9 100644
--- a/llvm/test/CodeGen/Mips/vector-setcc.ll
+++ b/llvm/test/CodeGen/Mips/vector-setcc.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel < %s
+; RUN: llc -mtriple=mipsel < %s
@a = common global <4 x i32> zeroinitializer, align 16
@b = common global <4 x i32> zeroinitializer, align 16
diff --git a/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll b/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
index c3f15fb6afa66a..e86097633b7fa1 100644
--- a/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
+++ b/llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: nounwind
define dso_local void @fun_s(float %a) local_unnamed_addr #0 {
diff --git a/llvm/test/CodeGen/Mips/vr4300-mulmul.ll b/llvm/test/CodeGen/Mips/vr4300-mulmul.ll
index 33d909c7b43696..823b7d0a2abf3b 100644
--- a/llvm/test/CodeGen/Mips/vr4300-mulmul.ll
+++ b/llvm/test/CodeGen/Mips/vr4300-mulmul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s
; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
define dso_local float @fun_s(float %x) local_unnamed_addr !dbg !7 {
diff --git a/llvm/test/CodeGen/Mips/weak.ll b/llvm/test/CodeGen/Mips/weak.ll
index fdc0a1d8854134..021cc6b9d72651 100644
--- a/llvm/test/CodeGen/Mips/weak.ll
+++ b/llvm/test/CodeGen/Mips/weak.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips < %s | FileCheck %s
+; RUN: llc -mtriple=mips < %s | FileCheck %s
@t = common global ptr null, align 4
diff --git a/llvm/test/CodeGen/Mips/whitespace.ll b/llvm/test/CodeGen/Mips/whitespace.ll
index 6710b73acbf1c4..51dd13231fd0ac 100644
--- a/llvm/test/CodeGen/Mips/whitespace.ll
+++ b/llvm/test/CodeGen/Mips/whitespace.ll
@@ -1,6 +1,6 @@
; Test that the instructions have the correct whitespace.
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck -strict-whitespace %s -check-prefix=16
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -strict-whitespace -check-prefix=32R2
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck -strict-whitespace %s -check-prefix=16
+; RUN: llc -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -strict-whitespace -check-prefix=32R2
@main.L = internal unnamed_addr constant [5 x ptr] [ptr blockaddress(@main, %L1), ptr blockaddress(@main, %L2), ptr blockaddress(@main, %L3), ptr blockaddress(@main, %L4), ptr null], align 4
@str = private unnamed_addr constant [2 x i8] c"A\00"
diff --git a/llvm/test/CodeGen/Mips/xor1.ll b/llvm/test/CodeGen/Mips/xor1.ll
index dcdfbf538ffd53..3dca266bf93d28 100644
--- a/llvm/test/CodeGen/Mips/xor1.ll
+++ b/llvm/test/CodeGen/Mips/xor1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@x = global i32 65504, align 4
@y = global i32 60929, align 4
diff --git a/llvm/test/CodeGen/Mips/zeroreg.ll b/llvm/test/CodeGen/Mips/zeroreg.ll
index f2abdb61503c5b..91705489b7319d 100644
--- a/llvm/test/CodeGen/Mips/zeroreg.ll
+++ b/llvm/test/CodeGen/Mips/zeroreg.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6
-; RUN: llc < %s -march=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV
-; RUN: llc < %s -march=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV
-; RUN: llc < %s -march=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV
-; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV
+; RUN: llc < %s -mtriple=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6
@g1 = external global i32
diff --git a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
index 97ff7c4589b448..b8628ac6ae87d3 100644
--- a/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
+++ b/llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=livedebugvalues -march=mips -o - %s | FileCheck %s
+# RUN: llc -run-pass=livedebugvalues -mtriple=mips -o - %s | FileCheck %s
#
#"last-instr-bundled.c"
#extern void set_cond(int, int*);
diff --git a/llvm/test/DebugInfo/Mips/tls.ll b/llvm/test/DebugInfo/Mips/tls.ll
index baf346fe035ba2..927966d5140783 100644
--- a/llvm/test/DebugInfo/Mips/tls.ll
+++ b/llvm/test/DebugInfo/Mips/tls.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -march=mips -mcpu=mips32r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-WORD
-; RUN: llc -O0 -march=mips64 -mcpu=mips64r2 -filetype=asm < %s | FileCheck %s -check-prefix=CHECK-DWORD
+; RUN: llc -O0 -mtriple=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-WORD
+; RUN: llc -O0 -mtriple=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=CHECK-DWORD
@x = thread_local global i32 5, align 4, !dbg !0
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