[llvm] [RISCV] Merge shuffle sources if lanes are disjoint (PR #119401)

[Philip Reames via llvm-commits]

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@@ -183,406 +183,499 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    csrr a2, vlenb
-; RV32-NEXT:    slli a3, a2, 6
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preames wrote:

Just for the record, this test is a real regression.  The new lower appears to increase register pressure.

I'm not worried about this case because:
1) This test case is really stressing legalization, and isn't representative of real code.
2) The two argument shuffle could have been a vcompress to start with.
3) The "right" lowering probably would have been multiple seg6 loads with offset addresses, and vslideups on the results, but that's well beyond anything worth bothering with.  

https://github.com/llvm/llvm-project/pull/119401