[llvm] Reapply [AMDGPU] prevent shrinking udiv/urem if either operand exceeds signed max (PR #119325)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 10 15:24:12 PST 2024
https://github.com/choikwa updated https://github.com/llvm/llvm-project/pull/119325
>From 5165138a430f6ca80a4d942e8bb5cad7e1674243 Mon Sep 17 00:00:00 2001
From: choikwa <code.kchoi at gmail.com>
Date: Mon, 9 Dec 2024 14:49:21 -0500
Subject: [PATCH] Reapply [AMDGPU] prevent shrinking udiv/urem if either
operand exceeds signed max
This reverts commit 254d206ee2a337cb38ba347c896f7c6a14c7f218.
+Added a fix in ExpandDivRem24 to disqualify if DivNumBits exceed 24.
+Reworked getDivNumBits API to return unsigned and change from AtLeast(SignBits)
to MaxDivBits hint.
+Used hint for unsigned case.
Original commit & msg:
ce6e955ac374f2b86cbbb73b2f32174dffd85f25.
Handle signed and unsigned path differently in getDivNumBits.
Using computeKnownBits, this rejects shrinking unsigned div/rem if
operands exceed signed max since we know NumSignBits will be always 0.
---
.../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 76 ++++--
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 97 +++++++
llvm/test/CodeGen/AMDGPU/bypass-div.ll | 119 ++++++++-
llvm/test/CodeGen/AMDGPU/sdiv64.ll | 117 ++-------
llvm/test/CodeGen/AMDGPU/srem64.ll | 132 +++-------
llvm/test/CodeGen/AMDGPU/udiv64.ll | 237 ++++--------------
llvm/test/CodeGen/AMDGPU/urem64.ll | 126 +++++-----
7 files changed, 429 insertions(+), 475 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index 75e20c79301681..9b9ec8c5674f61 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -254,9 +254,8 @@ class AMDGPUCodeGenPrepareImpl
bool divHasSpecialOptimization(BinaryOperator &I,
Value *Num, Value *Den) const;
- int getDivNumBits(BinaryOperator &I,
- Value *Num, Value *Den,
- unsigned AtLeast, bool Signed) const;
+ unsigned getDivNumBits(BinaryOperator &I, Value *Num, Value *Den,
+ unsigned AtLeast, bool Signed) const;
/// Expands 24 bit div or rem.
Value* expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I,
@@ -1189,24 +1188,54 @@ static Value* getMulHu(IRBuilder<> &Builder, Value *LHS, Value *RHS) {
return getMul64(Builder, LHS, RHS).second;
}
-/// Figure out how many bits are really needed for this division. \p AtLeast is
-/// an optimization hint to bypass the second ComputeNumSignBits call if we the
-/// first one is insufficient. Returns -1 on failure.
-int AMDGPUCodeGenPrepareImpl::getDivNumBits(BinaryOperator &I, Value *Num,
- Value *Den, unsigned AtLeast,
- bool IsSigned) const {
- unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
- if (LHSSignBits < AtLeast)
- return -1;
+/// Figure out how many bits are really needed for this division.
+/// \p MaxDivBits is an optimization hint to bypass the second
+/// ComputeNumSignBits/computeKnownBits call if we the first one is
+/// insufficient.
+unsigned AMDGPUCodeGenPrepareImpl::getDivNumBits(BinaryOperator &I, Value *Num,
+ Value *Den,
+ unsigned MaxDivBits,
+ bool IsSigned) const {
+ assert(Num->getType()->getScalarSizeInBits() ==
+ Den->getType()->getScalarSizeInBits());
+ unsigned SSBits = Num->getType()->getScalarSizeInBits();
+ if (IsSigned) {
+ unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
+ // a SignBit needs to be reserved for shrinking
+ unsigned DivBits = SSBits - RHSSignBits + 1;
+ if (DivBits > MaxDivBits)
+ return DivBits;
+
+ unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
+ DivBits = SSBits - LHSSignBits + 1;
+ if (DivBits > MaxDivBits)
+ return DivBits;
+
+ unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
+ DivBits = SSBits - SignBits + 1;
+ return DivBits;
+ }
- unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
- if (RHSSignBits < AtLeast)
- return -1;
+ // All bits are used for unsigned division for Num or Den in range
+ // (SignedMax, UnsignedMax].
+ KnownBits Known = computeKnownBits(Den, DL, 0, AC, &I);
+ if (Known.isNegative() || !Known.isNonNegative())
+ return SSBits;
+ unsigned RHSSignBits = Known.countMinLeadingZeros();
+ unsigned DivBits = SSBits - RHSSignBits;
+ if (DivBits > MaxDivBits)
+ return DivBits;
+
+ Known = computeKnownBits(Num, DL, 0, AC, &I);
+ if (Known.isNegative() || !Known.isNonNegative())
+ return SSBits;
+ unsigned LHSSignBits = Known.countMinLeadingZeros();
+ DivBits = SSBits - LHSSignBits;
+ if (DivBits > MaxDivBits)
+ return DivBits;
unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
- unsigned DivBits = Num->getType()->getScalarSizeInBits() - SignBits;
- if (IsSigned)
- ++DivBits;
+ DivBits = SSBits - SignBits;
return DivBits;
}
@@ -1216,11 +1245,8 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder,
BinaryOperator &I, Value *Num,
Value *Den, bool IsDiv,
bool IsSigned) const {
- unsigned SSBits = Num->getType()->getScalarSizeInBits();
- // If Num bits <= 24, assume 0 signbits.
- unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24 + IsSigned);
- int DivBits = getDivNumBits(I, Num, Den, AtLeast, IsSigned);
- if (DivBits == -1)
+ unsigned DivBits = getDivNumBits(I, Num, Den, 24, IsSigned);
+ if (DivBits > 24)
return nullptr;
return expandDivRem24Impl(Builder, I, Num, Den, DivBits, IsDiv, IsSigned);
}
@@ -1504,8 +1530,8 @@ Value *AMDGPUCodeGenPrepareImpl::shrinkDivRem64(IRBuilder<> &Builder,
bool IsDiv = Opc == Instruction::SDiv || Opc == Instruction::UDiv;
bool IsSigned = Opc == Instruction::SDiv || Opc == Instruction::SRem;
- int NumDivBits = getDivNumBits(I, Num, Den, 32, IsSigned);
- if (NumDivBits == -1)
+ unsigned NumDivBits = getDivNumBits(I, Num, Den, 32, IsSigned);
+ if (NumDivBits > 32)
return nullptr;
Value *Narrowed = nullptr;
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index b7436aeb1d5302..4f04c15b3d44ab 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -9999,3 +9999,100 @@ define <2 x i64> @v_udiv_i64_exact(<2 x i64> %num) {
%result = udiv exact <2 x i64> %num, <i64 4096, i64 1024>
ret <2 x i64> %result
}
+
+define i64 @udiv_i64_gt_smax(i8 %size) {
+; GFX6-LABEL: udiv_i64_gt_smax:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: v_not_b32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s4, 0xcccccccd
+; GFX6-NEXT: v_mul_lo_u32 v3, v1, s4
+; GFX6-NEXT: v_mul_hi_u32 v4, v0, s4
+; GFX6-NEXT: s_mov_b32 s6, 0xcccccccc
+; GFX6-NEXT: v_mul_hi_u32 v5, v1, s4
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
+; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
+; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, s6
+; GFX6-NEXT: v_mul_hi_u32 v1, v1, s6
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0
+; GFX6-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
+; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 3
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 3, v1
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: udiv_i64_gt_smax:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, 31
+; GFX9-NEXT: v_not_b32_sdwa v4, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+; GFX9-NEXT: s_mov_b32 s4, 0xcccccccd
+; GFX9-NEXT: v_ashrrev_i32_sdwa v1, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_mul_hi_u32 v0, v4, s4
+; GFX9-NEXT: v_not_b32_e32 v5, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: s_mov_b32 s6, 0xcccccccc
+; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, s4, v[0:1]
+; GFX9-NEXT: v_mov_b32_e32 v6, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, s6, v[2:3]
+; GFX9-NEXT: v_mov_b32_e32 v0, v1
+; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v0
+; GFX9-NEXT: v_addc_co_u32_e64 v1, s[4:5], 0, 0, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, s6, v[0:1]
+; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 3
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 3, v1
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %esize = sext i8 %size to i64
+ %minus = sub nuw nsw i64 -1, %esize
+ %div = udiv i64 %minus, 10
+ ret i64 %div
+}
+
+define i64 @udiv_i64_9divbits(i8 %size) {
+; GFX6-LABEL: udiv_i64_9divbits:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v0
+; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX6-NEXT: s_mov_b32 s4, 0x41200000
+; GFX6-NEXT: v_mul_f32_e32 v1, 0x3dcccccd, v0
+; GFX6-NEXT: v_trunc_f32_e32 v1, v1
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX6-NEXT: v_mad_f32 v0, -v1, s4, v0
+; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT: v_and_b32_e32 v0, 0x1ff, v0
+; GFX6-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: udiv_i64_9divbits:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, 1
+; GFX9-NEXT: v_add_u32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX9-NEXT: s_mov_b32 s4, 0x41200000
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x3dcccccd, v0
+; GFX9-NEXT: v_trunc_f32_e32 v1, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
+; GFX9-NEXT: v_mad_f32 v0, -v1, s4, v0
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v2, vcc
+; GFX9-NEXT: v_and_b32_e32 v0, 0x1ff, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %zextend = zext i8 %size to i64
+ %num = add nuw nsw i64 1, %zextend
+ %div = udiv i64 %num, 10
+ ret i64 %div
+}
diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
index 5bbea7ecf3f2d5..5dde193528aa4e 100644
--- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll
+++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
@@ -1021,8 +1021,116 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) {
; GFX9-LABEL: sdiv64_known32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
+; GFX9-NEXT: v_or_b32_e32 v5, v2, v0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v7, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, v3
+; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-NEXT: s_cbranch_execz .LBB10_2
+; GFX9-NEXT: ; %bb.1:
+; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v6
+; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0
+; GFX9-NEXT: v_sub_co_u32_e32 v11, vcc, 0, v6
+; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, 0, v0, vcc
+; GFX9-NEXT: v_madmk_f32 v1, v3, 0x4f800000, v1
+; GFX9-NEXT: v_rcp_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
+; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_madmk_f32 v1, v3, 0xcf800000, v1
+; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_mul_lo_u32 v5, v11, v10
+; GFX9-NEXT: v_mul_lo_u32 v8, v12, v1
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v1, 0
+; GFX9-NEXT: v_add3_u32 v8, v4, v5, v8
+; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v8, 0
+; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v9, v4
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v10, v3, 0
+; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v8, 0
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v13, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v9, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v10, v4, vcc
+; GFX9-NEXT: v_mul_lo_u32 v5, v11, v13
+; GFX9-NEXT: v_mul_lo_u32 v8, v12, v1
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v1, 0
+; GFX9-NEXT: v_add3_u32 v8, v4, v5, v8
+; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v13, v8, 0
+; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v1, v8, 0
+; GFX9-NEXT: v_mul_hi_u32 v12, v1, v3
+; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v13, v3, 0
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v12, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v10
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v11, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
+; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v4, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v7, v5, 0
+; GFX9-NEXT: v_mul_hi_u32 v8, v7, v1
+; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v8, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v4, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v2, v1, 0
+; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v2, v5, 0
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v10, v3
+; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v9, vcc
+; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v8
+; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v8, v0, v1
+; GFX9-NEXT: v_mul_lo_u32 v9, v6, v5
+; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v1, 0
+; GFX9-NEXT: v_add3_u32 v4, v4, v9, v8
+; GFX9-NEXT: v_sub_u32_e32 v8, v2, v4
+; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT: v_subb_co_u32_e64 v7, s[4:5], v8, v0, vcc
+; GFX9-NEXT: v_sub_co_u32_e64 v8, s[4:5], v3, v6
+; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[4:5], 0, v7, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5]
+; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], 2, v1
+; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v5, s[4:5]
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
+; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6
+; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v5, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v0
+; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5]
+; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc
+; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
+; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX9-NEXT: .LBB10_2: ; %Flow
+; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
+; GFX9-NEXT: s_cbranch_execz .LBB10_4
+; GFX9-NEXT: ; %bb.3:
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v3
; GFX9-NEXT: v_sub_u32_e32 v2, 0, v3
+; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -1033,14 +1141,17 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) {
; GFX9-NEXT: v_mul_lo_u32 v2, v0, v3
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2
-; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GFX9-NEXT: v_sub_u32_e32 v2, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc
+; GFX9-NEXT: .LBB10_4:
+; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_mov_b32_e32 v1, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
%a.ext = ashr i64 %a, 32
%b.ext = ashr i64 %b, 32
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
index 3e8768c98b5c9a..96dd6276f7e382 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -1065,100 +1065,37 @@ define amdgpu_kernel void @s_test_sdiv24_48(ptr addrspace(1) %out, i48 %x, i48 %
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_sdiv24_48:
-; GCN-IR: ; %bb.0: ; %_udiv-special-cases
-; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
-; GCN-IR-NEXT: s_mov_b32 s15, 0
-; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_sext_i32_i16 s1, s1
-; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 24
-; GCN-IR-NEXT: s_sext_i32_i16 s3, s3
-; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 24
-; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[0:1], 16
-; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31
-; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
-; GCN-IR-NEXT: s_mov_b32 s1, s0
-; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[2:3], 16
-; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
-; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1]
-; GCN-IR-NEXT: s_mov_b32 s3, s2
-; GCN-IR-NEXT: s_sub_u32 s12, s6, s0
-; GCN-IR-NEXT: s_subb_u32 s13, s7, s0
-; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3]
-; GCN-IR-NEXT: s_sub_u32 s6, s6, s2
-; GCN-IR-NEXT: s_subb_u32 s7, s7, s2
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[12:13], 0
-; GCN-IR-NEXT: s_flbit_i32_b64 s14, s[6:7]
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
-; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[12:13]
-; GCN-IR-NEXT: s_sub_u32 s16, s14, s20
-; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
-; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63
-; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19]
-; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec
-; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13
-; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12
-; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23]
-; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
-; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19]
-; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
-; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
-; GCN-IR-NEXT: s_add_u32 s18, s16, 1
-; GCN-IR-NEXT: s_addc_u32 s19, s17, 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0
-; GCN-IR-NEXT: s_sub_i32 s16, 63, s16
-; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
-; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16
-; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
-; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s18
-; GCN-IR-NEXT: s_add_u32 s18, s6, -1
-; GCN-IR-NEXT: s_addc_u32 s19, s7, -1
-; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
-; GCN-IR-NEXT: s_add_u32 s12, s8, s20
-; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
-; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
-; GCN-IR-NEXT: s_mov_b32 s9, 0
-; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
-; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
-; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
-; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
-; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11]
-; GCN-IR-NEXT: s_sub_u32 s8, s18, s16
-; GCN-IR-NEXT: s_subb_u32 s8, s19, s17
-; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
-; GCN-IR-NEXT: s_mov_b32 s15, s14
-; GCN-IR-NEXT: s_and_b32 s8, s14, 1
-; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7]
-; GCN-IR-NEXT: s_sub_u32 s16, s16, s14
-; GCN-IR-NEXT: s_subb_u32 s17, s17, s15
-; GCN-IR-NEXT: s_add_u32 s12, s12, 1
-; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
-; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
-; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
-; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
-; GCN-IR-NEXT: .LBB9_4: ; %Flow4
-; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7]
-; GCN-IR-NEXT: .LBB9_5: ; %udiv-end
-; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
-; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1]
-; GCN-IR-NEXT: s_sub_u32 s0, s2, s0
-; GCN-IR-NEXT: s_subb_u32 s1, s3, s1
+; GCN-IR: ; %bb.0:
+; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4
-; GCN-IR-NEXT: s_waitcnt expcnt(0)
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
+; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: s_sext_i32_i16 s1, s9
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
+; GCN-IR-NEXT: v_alignbit_b32 v0, s1, v0, 24
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: s_sext_i32_i16 s0, s3
+; GCN-IR-NEXT: v_mov_b32_e32 v2, s2
+; GCN-IR-NEXT: v_alignbit_b32 v2, s0, v2, 24
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1
+; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0
+; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v4
+; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, v3
+; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-IR-NEXT: s_endpgm
%1 = ashr i48 %x, 24
%2 = ashr i48 %y, 24
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index cb8f82db92bbf8..23364e860d1542 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -1188,109 +1188,39 @@ define amdgpu_kernel void @s_test_srem24_48(ptr addrspace(1) %out, i48 %x, i48 %
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_srem24_48:
-; GCN-IR: ; %bb.0: ; %_udiv-special-cases
-; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
-; GCN-IR-NEXT: s_mov_b32 s13, 0
+; GCN-IR: ; %bb.0:
+; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
+; GCN-IR-NEXT: s_mov_b32 s6, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_sext_i32_i16 s1, s1
; GCN-IR-NEXT: s_sext_i32_i16 s3, s3
-; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 24
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 24
-; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
-; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], 16
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[0:1], 16
-; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31
-; GCN-IR-NEXT: s_mov_b32 s1, s0
-; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 16
-; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1]
-; GCN-IR-NEXT: s_sub_u32 s2, s2, s0
-; GCN-IR-NEXT: s_subb_u32 s3, s3, s0
-; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31
-; GCN-IR-NEXT: s_mov_b32 s11, s10
-; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[10:11]
-; GCN-IR-NEXT: s_sub_u32 s6, s6, s10
-; GCN-IR-NEXT: s_subb_u32 s7, s7, s10
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
-; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[6:7]
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
-; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[2:3]
-; GCN-IR-NEXT: s_sub_u32 s14, s12, s20
-; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
-; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63
-; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17]
-; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec
-; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3
-; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2
-; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
-; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
-; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17]
-; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
-; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
-; GCN-IR-NEXT: s_add_u32 s16, s14, 1
-; GCN-IR-NEXT: s_addc_u32 s17, s15, 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[16:17], 0
-; GCN-IR-NEXT: s_sub_i32 s14, 63, s14
-; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
-; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s14
-; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
-; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s16
-; GCN-IR-NEXT: s_add_u32 s18, s6, -1
-; GCN-IR-NEXT: s_addc_u32 s19, s7, -1
-; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13]
-; GCN-IR-NEXT: s_add_u32 s12, s8, s20
-; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
-; GCN-IR-NEXT: s_mov_b64 s[16:17], 0
-; GCN-IR-NEXT: s_mov_b32 s9, 0
-; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
-; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
-; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
-; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
-; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[8:9]
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[16:17], s[10:11]
-; GCN-IR-NEXT: s_sub_u32 s8, s18, s14
-; GCN-IR-NEXT: s_subb_u32 s8, s19, s15
-; GCN-IR-NEXT: s_ashr_i32 s16, s8, 31
-; GCN-IR-NEXT: s_mov_b32 s17, s16
-; GCN-IR-NEXT: s_and_b32 s8, s16, 1
-; GCN-IR-NEXT: s_and_b64 s[16:17], s[16:17], s[6:7]
-; GCN-IR-NEXT: s_sub_u32 s14, s14, s16
-; GCN-IR-NEXT: s_subb_u32 s15, s15, s17
-; GCN-IR-NEXT: s_add_u32 s12, s12, 1
-; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
-; GCN-IR-NEXT: s_mov_b64 s[16:17], s[8:9]
-; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
-; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
-; GCN-IR-NEXT: .LBB9_4: ; %Flow4
-; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
-; GCN-IR-NEXT: .LBB9_5: ; %udiv-end
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s10
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, v0
-; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x9
-; GCN-IR-NEXT: s_mul_i32 s4, s6, s11
-; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v0
-; GCN-IR-NEXT: s_mul_i32 s4, s7, s10
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v0
-; GCN-IR-NEXT: s_mul_i32 s4, s6, s10
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s4
-; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s2, v1
-; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc
-; GCN-IR-NEXT: v_xor_b32_e32 v1, s0, v1
-; GCN-IR-NEXT: v_xor_b32_e32 v0, s1, v0
-; GCN-IR-NEXT: v_mov_b32_e32 v2, s1
-; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1
-; GCN-IR-NEXT: s_mov_b32 s15, 0xf000
-; GCN-IR-NEXT: s_mov_b32 s14, -1
-; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v0, v2, vcc
-; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: buffer_store_short v0, off, s[12:15], 0 offset:4
-; GCN-IR-NEXT: buffer_store_dword v1, off, s[12:15], 0
+; GCN-IR-NEXT: s_sext_i32_i16 s5, s5
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
+; GCN-IR-NEXT: v_alignbit_b32 v0, s5, v0, 24
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GCN-IR-NEXT: v_mov_b32_e32 v2, s2
+; GCN-IR-NEXT: v_alignbit_b32 v2, s3, v2, 24
+; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1
+; GCN-IR-NEXT: v_xor_b32_e32 v5, v2, v0
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 30, v5
+; GCN-IR-NEXT: v_or_b32_e32 v5, 1, v5
+; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4
+; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-IR-NEXT: v_mad_f32 v3, -v4, v1, v3
+; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
+; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v4
+; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
+; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, v0, v2
+; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
+; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
; GCN-IR-NEXT: s_endpgm
%1 = ashr i48 %x, 24
%2 = ashr i48 %y, 24
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
index a77e3c226ad267..db7d816386a70d 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -716,199 +716,66 @@ define amdgpu_kernel void @s_test_udiv23_i64(ptr addrspace(1) %out, i64 %x, i64
define amdgpu_kernel void @s_test_udiv24_i48(ptr addrspace(1) %out, i48 %x, i48 %y) {
; GCN-LABEL: s_test_udiv24_i48:
; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
-; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
-; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, -1
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_and_b32 s0, s0, 0xff000000
-; GCN-NEXT: s_and_b32 s1, s1, 0xffff
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: v_alignbit_b32 v0, s1, v0, 24
-; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
-; GCN-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NEXT: s_and_b32 s6, s6, 0xff000000
-; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 24
-; GCN-NEXT: v_mac_f32_e32 v1, 0, v2
-; GCN-NEXT: v_rcp_f32_e32 v1, v1
-; GCN-NEXT: s_sub_u32 s8, 0, s0
-; GCN-NEXT: s_subb_u32 s9, 0, s1
-; GCN-NEXT: s_mov_b32 s0, s4
-; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
-; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
+; GCN-NEXT: s_and_b32 s2, s2, 0xff000000
+; GCN-NEXT: s_and_b32 s4, s4, 0xff000000
+; GCN-NEXT: s_and_b32 s5, s5, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_alignbit_b32 v0, s5, v0, 24
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GCN-NEXT: s_and_b32 s3, s3, 0xffff
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_alignbit_b32 v1, s3, v1, 24
+; GCN-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
; GCN-NEXT: v_trunc_f32_e32 v2, v2
-; GCN-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v1
+; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: s_mov_b32 s1, s5
-; GCN-NEXT: v_mul_lo_u32 v3, s8, v2
-; GCN-NEXT: v_mul_hi_u32 v4, s8, v1
-; GCN-NEXT: v_mul_lo_u32 v5, s9, v1
-; GCN-NEXT: v_mul_lo_u32 v6, s8, v1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_mul_lo_u32 v4, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v5, v1, v6
-; GCN-NEXT: v_mul_hi_u32 v7, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v8, v2, v3
-; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
-; GCN-NEXT: v_mul_lo_u32 v7, v2, v6
-; GCN-NEXT: v_mul_hi_u32 v6, v2, v6
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v6, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v8, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, s8, v2
-; GCN-NEXT: v_mul_hi_u32 v4, s8, v1
-; GCN-NEXT: v_mul_lo_u32 v5, s9, v1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
-; GCN-NEXT: v_mul_lo_u32 v4, s8, v1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT: v_mul_lo_u32 v7, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v8, v1, v4
-; GCN-NEXT: v_mul_hi_u32 v9, v1, v3
-; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
-; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
-; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
-; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
-; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT: v_mov_b32_e32 v3, s6
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
-; GCN-NEXT: v_alignbit_b32 v3, s7, v3, 24
-; GCN-NEXT: v_mul_lo_u32 v4, v3, v2
-; GCN-NEXT: v_mul_hi_u32 v1, v3, v1
-; GCN-NEXT: v_mul_hi_u32 v2, v3, v2
-; GCN-NEXT: v_mov_b32_e32 v5, 0
-; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1
-; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
-; GCN-NEXT: v_mul_hi_u32 v7, v0, v1
-; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v1
-; GCN-NEXT: v_mul_lo_u32 v10, v0, v1
-; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
-; GCN-NEXT: v_add_i32_e32 v8, vcc, 2, v1
-; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
-; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v10
-; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v6, vcc
-; GCN-NEXT: v_sub_i32_e32 v7, vcc, v3, v0
-; GCN-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v6, vcc
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
-; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
-; GCN-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
-; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v0
-; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6
-; GCN-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
-; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
-; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
-; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GCN-NEXT: buffer_store_short v3, off, s[4:7], 0 offset:4
+; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
; GCN-IR-LABEL: s_test_udiv24_i48:
-; GCN-IR: ; %bb.0: ; %_udiv-special-cases
-; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
-; GCN-IR-NEXT: s_mov_b32 s11, 0
+; GCN-IR: ; %bb.0:
+; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
+; GCN-IR-NEXT: s_mov_b32 s6, -1
+; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_and_b32 s1, s1, 0xffff
-; GCN-IR-NEXT: s_and_b32 s0, s0, 0xff000000
-; GCN-IR-NEXT: s_and_b32 s3, s3, 0xffff
; GCN-IR-NEXT: s_and_b32 s2, s2, 0xff000000
-; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[0:1], 24
-; GCN-IR-NEXT: s_lshr_b64 s[0:1], s[2:3], 24
-; GCN-IR-NEXT: s_and_b32 s9, s9, 0xffff
-; GCN-IR-NEXT: s_and_b32 s1, s1, 0xffff
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[0:1], 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
-; GCN-IR-NEXT: s_flbit_i32_b64 s10, s[0:1]
-; GCN-IR-NEXT: s_or_b64 s[6:7], s[2:3], s[6:7]
-; GCN-IR-NEXT: s_flbit_i32_b64 s16, s[8:9]
-; GCN-IR-NEXT: s_sub_u32 s12, s10, s16
-; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
-; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63
-; GCN-IR-NEXT: s_or_b64 s[14:15], s[6:7], s[14:15]
-; GCN-IR-NEXT: s_and_b64 s[6:7], s[14:15], exec
-; GCN-IR-NEXT: s_cselect_b32 s7, 0, s9
-; GCN-IR-NEXT: s_cselect_b32 s6, 0, s8
-; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
-; GCN-IR-NEXT: s_mov_b64 s[2:3], 0
-; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
-; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
-; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
-; GCN-IR-NEXT: s_add_u32 s14, s12, 1
-; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[14:15], 0
-; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
-; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
-; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], s12
-; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
-; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
-; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[8:9], s14
-; GCN-IR-NEXT: s_add_u32 s14, s0, -1
-; GCN-IR-NEXT: s_addc_u32 s15, s1, -1
-; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11]
-; GCN-IR-NEXT: s_add_u32 s8, s2, s16
-; GCN-IR-NEXT: s_addc_u32 s9, s3, 0
-; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
-; GCN-IR-NEXT: s_mov_b32 s3, 0
-; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
-; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
-; GCN-IR-NEXT: s_lshr_b32 s2, s7, 31
-; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
-; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[2:3]
-; GCN-IR-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
-; GCN-IR-NEXT: s_sub_u32 s2, s14, s12
-; GCN-IR-NEXT: s_subb_u32 s2, s15, s13
-; GCN-IR-NEXT: s_ashr_i32 s10, s2, 31
-; GCN-IR-NEXT: s_mov_b32 s11, s10
-; GCN-IR-NEXT: s_and_b32 s2, s10, 1
-; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[0:1]
-; GCN-IR-NEXT: s_sub_u32 s12, s12, s10
-; GCN-IR-NEXT: s_subb_u32 s13, s13, s11
-; GCN-IR-NEXT: s_add_u32 s8, s8, 1
-; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
-; GCN-IR-NEXT: s_mov_b64 s[10:11], s[2:3]
-; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
-; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
-; GCN-IR-NEXT: .LBB7_4: ; %Flow4
-; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[6:7], 1
-; GCN-IR-NEXT: s_or_b64 s[6:7], s[2:3], s[0:1]
-; GCN-IR-NEXT: .LBB7_5: ; %udiv-end
-; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
-; GCN-IR-NEXT: v_mov_b32_e32 v1, s6
-; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
-; GCN-IR-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GCN-IR-NEXT: s_and_b32 s4, s4, 0xff000000
+; GCN-IR-NEXT: s_and_b32 s5, s5, 0xffff
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
+; GCN-IR-NEXT: v_alignbit_b32 v0, s5, v0, 24
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GCN-IR-NEXT: s_and_b32 s3, s3, 0xffff
+; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
+; GCN-IR-NEXT: v_alignbit_b32 v1, s3, v1, 24
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT: s_mov_b32 s4, s0
+; GCN-IR-NEXT: s_mov_b32 s5, s1
+; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
+; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GCN-IR-NEXT: buffer_store_short v3, off, s[4:7], 0 offset:4
+; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-IR-NEXT: s_endpgm
%1 = lshr i48 %x, 24
%2 = lshr i48 %y, 24
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
index b4f977db804392..a794d139063d5f 100644
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -665,54 +665,47 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6
; GCN-LABEL: s_test_urem23_64_v2i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
+; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s3, 0xf000
+; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_lshr_b32 s0, s13, 1
-; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT: s_sub_i32 s1, 0, s0
-; GCN-NEXT: s_lshr_b32 s6, s15, 9
-; GCN-NEXT: v_cvt_f32_u32_e32 v2, s6
-; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: s_lshr_b32 s6, s13, 1
+; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GCN-NEXT: s_lshr_b32 s0, s15, 9
+; GCN-NEXT: v_cvt_f32_u32_e32 v2, s0
; GCN-NEXT: s_lshr_b32 s7, s11, 9
-; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-NEXT: v_cvt_f32_u32_e32 v3, s7
+; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GCN-NEXT: s_sub_i32 s1, 0, s6
; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT: v_mul_lo_u32 v1, s1, v0
-; GCN-NEXT: s_lshr_b32 s1, s9, 1
-; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-NEXT: s_mul_i32 s2, s2, s0
-; GCN-NEXT: s_sub_i32 s1, s1, s2
-; GCN-NEXT: s_sub_i32 s2, s1, s0
-; GCN-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-NEXT: s_sub_i32 s2, s1, s0
-; GCN-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-NEXT: s_cselect_b32 s8, s2, s1
-; GCN-NEXT: s_sub_i32 s0, 0, s6
-; GCN-NEXT: v_mul_lo_u32 v0, s0, v1
+; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
+; GCN-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GCN-NEXT: s_lshr_b32 s8, s9, 1
+; GCN-NEXT: v_mul_hi_u32 v5, v0, v5
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT: v_mul_lo_u32 v2, v2, s0
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-NEXT: v_mul_hi_u32 v0, s8, v0
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-NEXT: s_mov_b32 s2, -1
-; GCN-NEXT: v_mul_hi_u32 v0, v1, v0
-; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT: v_mul_hi_u32 v2, s7, v0
-; GCN-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NEXT: v_mov_b32_e32 v0, s8
-; GCN-NEXT: v_mov_b32_e32 v3, v1
-; GCN-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
+; GCN-NEXT: v_readfirstlane_b32 s4, v0
; GCN-NEXT: s_mul_i32 s4, s4, s6
-; GCN-NEXT: s_sub_i32 s4, s7, s4
+; GCN-NEXT: s_sub_i32 s4, s8, s4
; GCN-NEXT: s_sub_i32 s5, s4, s6
; GCN-NEXT: s_cmp_ge_u32 s4, s6
; GCN-NEXT: s_cselect_b32 s4, s5, s4
; GCN-NEXT: s_sub_i32 s5, s4, s6
; GCN-NEXT: s_cmp_ge_u32 s4, s6
; GCN-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NEXT: v_and_b32_e32 v2, 0x7fffff, v2
+; GCN-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NEXT: v_mov_b32_e32 v3, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-NEXT: s_endpgm
@@ -720,54 +713,47 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6
; GCN-IR-LABEL: s_test_urem23_64_v2i64:
; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
+; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_lshr_b32 s0, s13, 1
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT: s_sub_i32 s1, 0, s0
-; GCN-IR-NEXT: s_lshr_b32 s6, s15, 9
-; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s6
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-IR-NEXT: s_lshr_b32 s6, s13, 1
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6
+; GCN-IR-NEXT: s_lshr_b32 s0, s15, 9
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s0
; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9
-; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s7
+; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2
+; GCN-IR-NEXT: s_sub_i32 s1, 0, s6
; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GCN-IR-NEXT: v_mul_lo_u32 v1, s1, v0
-; GCN-IR-NEXT: s_lshr_b32 s1, s9, 1
-; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, s1, v0
-; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
-; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
-; GCN-IR-NEXT: s_mul_i32 s2, s2, s0
-; GCN-IR-NEXT: s_sub_i32 s1, s1, s2
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
-; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
-; GCN-IR-NEXT: s_cselect_b32 s8, s2, s1
-; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
-; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v1
+; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4
+; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
+; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3
+; GCN-IR-NEXT: v_mul_lo_u32 v5, s1, v0
+; GCN-IR-NEXT: v_cvt_u32_f32_e32 v4, v4
+; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GCN-IR-NEXT: s_lshr_b32 s8, s9, 1
+; GCN-IR-NEXT: v_mul_hi_u32 v5, v0, v5
+; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s0
+; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v5
+; GCN-IR-NEXT: v_mul_hi_u32 v0, s8, v0
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-IR-NEXT: s_mov_b32 s2, -1
-; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0
-; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0
-; GCN-IR-NEXT: v_mul_hi_u32 v2, s7, v0
-; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
-; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
-; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
-; GCN-IR-NEXT: v_readfirstlane_b32 s4, v2
+; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v2
+; GCN-IR-NEXT: v_readfirstlane_b32 s4, v0
; GCN-IR-NEXT: s_mul_i32 s4, s4, s6
-; GCN-IR-NEXT: s_sub_i32 s4, s7, s4
+; GCN-IR-NEXT: s_sub_i32 s4, s8, s4
; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
-; GCN-IR-NEXT: v_mov_b32_e32 v2, s4
+; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffff, v2
+; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
+; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm
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