[llvm] CodeGen: Eliminate dynamic relocations in the register superclass tables. (PR #119122)

[Owen Anderson via llvm-commits]

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@@ -431,8 +431,9 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
       return WSub[GenIdx];
   }
 
-  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
-    return getHexagonSubRegIndex(*SuperRC, GenIdx);
+  unsigned SuperID = *RC.superclasses().begin();
+  if (SuperID != ~0U)
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resistor wrote:

Done. Seems unfortunate that no Hexxagon tests expose this...

https://github.com/llvm/llvm-project/pull/119122