[llvm] [RISCV][GISel] Port TrailingOnesMask PatLeaf. (PR #119427)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 10 10:11:32 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
---
Patch is 38.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119427.diff
17 Files Affected:
- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+10)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+13-1)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll (+16-18)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll (+8-12)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll (+17-21)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll (+14-16)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll (+8-12)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll (+111-129)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll (+9-11)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir (+3-4)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll (+2-3)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll (+4-6)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll (+10-15)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zba.ll (+4-6)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll (+2-3)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll (+4-6)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll (+13-20)
``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index d525834ce76c2c..985264c591e105 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -134,6 +134,8 @@ class RISCVInstructionSelector : public InstructionSelector {
void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
+ void renderXLenSubTrailingOnes(MachineInstrBuilder &MIB,
+ const MachineInstr &MI, int OpIdx) const;
const RISCVSubtarget &STI;
const RISCVInstrInfo &TII;
@@ -861,6 +863,14 @@ void RISCVInstructionSelector::renderTrailingZeros(MachineInstrBuilder &MIB,
MIB.addImm(llvm::countr_zero(C));
}
+void RISCVInstructionSelector::renderXLenSubTrailingOnes(
+ MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
+ assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
+ "Expected G_CONSTANT");
+ uint64_t C = MI.getOperand(1).getCImm()->getZExtValue();
+ MIB.addImm(Subtarget->getXLen() - llvm::countr_one(C));
+}
+
const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
LLT Ty, const RegisterBank &RB) const {
if (RB.getID() == RISCV::GPRBRegBankID) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 14b571cebe1fec..7cae93e53d7700 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -476,6 +476,8 @@ def XLenSubTrailingOnes : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(XLen - TrailingOnes, SDLoc(N),
N->getValueType(0));
}]>;
+def GIXLenSubTrailingOnes : GICustomOperandRenderer<"renderXLenSubTrailingOnes">,
+ GISDNodeXFormEquiv<XLenSubTrailingOnes>;
// Checks if this mask is a non-empty sequence of ones starting at the
// most/least significant bit with the remainder zero and exceeds simm32/simm12.
@@ -489,7 +491,17 @@ def TrailingOnesMask : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
return !isInt<12>(N->getSExtValue()) && isMask_64(N->getZExtValue());
-}], XLenSubTrailingOnes>;
+}], XLenSubTrailingOnes> {
+ let GISelPredicateCode = [{
+ if (!MRI.hasOneNonDBGUse(MI.getOperand(0).getReg()))
+ return false;
+ const auto &MO = MI.getOperand(1);
+ if (!MO.isCImm())
+ return false;
+ return !isInt<12>(MO.getCImm()->getSExtValue()) &&
+ isMask_64(MO.getCImm()->getZExtValue());
+ }];
+}
// Similar to LeadingOnesMask, but only consider leading ones in the lower 32
// bits.
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
index 828c6053c8ff72..534fec21ce7c47 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
@@ -161,8 +161,8 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; RV32I-LABEL: fsgnj_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
@@ -170,10 +170,10 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; RV64I-LABEL: fsgnj_d:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, -1
-; RV64I-NEXT: slli a3, a2, 63
-; RV64I-NEXT: srli a2, a2, 1
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: slli a2, a2, 63
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
@@ -241,9 +241,9 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; RV32I-LABEL: fsgnjn_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
+; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: xor a3, a3, a2
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
@@ -251,11 +251,11 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; RV64I-LABEL: fsgnjn_d:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, -1
-; RV64I-NEXT: slli a3, a2, 63
-; RV64I-NEXT: srli a2, a2, 1
-; RV64I-NEXT: xor a1, a1, a3
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: slli a2, a2, 63
+; RV64I-NEXT: xor a1, a1, a2
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = fneg double %b
@@ -281,9 +281,8 @@ define double @fabs_d(double %a, double %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __adddf3
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: lui a1, 524288
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a1, a3, a1
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: call __adddf3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -296,9 +295,8 @@ define double @fabs_d(double %a, double %b) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
-; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
index 6b623fd6867a2d..81d3381449bc87 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
@@ -787,17 +787,15 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_s_i16:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV32IFD-NEXT: lui a1, 16
-; RV32IFD-NEXT: addi a1, a1, -1
-; RV32IFD-NEXT: and a0, a0, a1
+; RV32IFD-NEXT: slli a0, a0, 16
+; RV32IFD-NEXT: srli a0, a0, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_s_i16:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
-; RV64IFD-NEXT: lui a1, 16
-; RV64IFD-NEXT: addiw a1, a1, -1
-; RV64IFD-NEXT: and a0, a0, a1
+; RV64IFD-NEXT: slli a0, a0, 48
+; RV64IFD-NEXT: srli a0, a0, 48
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_i16:
@@ -805,9 +803,8 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __fixunsdfsi
-; RV32I-NEXT: lui a1, 16
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -817,9 +814,8 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi
-; RV64I-NEXT: lui a1, 16
-; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
index 04bfbbb6e694f4..8d77d41ab6b455 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
@@ -631,16 +631,14 @@ define double @fabs_f64(double %a) nounwind {
;
; RV32I-LABEL: fabs_f64:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a2, 524288
-; RV32I-NEXT: addi a2, a2, -1
-; RV32I-NEXT: and a1, a1, a2
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fabs_f64:
; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, -1
-; RV64I-NEXT: srli a1, a1, 1
-; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%1 = call double @llvm.fabs.f64(double %a)
ret double %1
@@ -715,8 +713,8 @@ define double @copysign_f64(double %a, double %b) nounwind {
; RV32I-LABEL: copysign_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
-; RV32I-NEXT: addi a4, a2, -1
-; RV32I-NEXT: and a1, a1, a4
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
@@ -724,10 +722,10 @@ define double @copysign_f64(double %a, double %b) nounwind {
; RV64I-LABEL: copysign_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, -1
-; RV64I-NEXT: slli a3, a2, 63
-; RV64I-NEXT: srli a2, a2, 1
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: and a1, a1, a3
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: slli a2, a2, 63
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
@@ -1039,10 +1037,9 @@ define i1 @isnan_d_fpclass(double %x) {
;
; RV32I-LABEL: isnan_d_fpclass:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a2, 524288
-; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: lui a2, 524032
-; RV32I-NEXT: and a1, a1, a3
+; RV32I-NEXT: slli a1, a1, 1
+; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: beq a1, a2, .LBB25_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a2, a1
@@ -1053,12 +1050,11 @@ define i1 @isnan_d_fpclass(double %x) {
;
; RV64I-LABEL: isnan_d_fpclass:
; RV64I: # %bb.0:
-; RV64I-NEXT: li a1, -1
-; RV64I-NEXT: li a2, 2047
-; RV64I-NEXT: srli a1, a1, 1
-; RV64I-NEXT: slli a2, a2, 52
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: sltu a0, a2, a0
+; RV64I-NEXT: li a1, 2047
+; RV64I-NEXT: slli a0, a0, 1
+; RV64I-NEXT: slli a1, a1, 52
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
ret i1 %1
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
index f5272989161509..3a60856665742a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
@@ -161,8 +161,8 @@ define float @fsgnj_s(float %a, float %b) nounwind {
; RV32I-LABEL: fsgnj_s:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
-; RV32I-NEXT: addi a3, a2, -1
-; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
@@ -170,8 +170,8 @@ define float @fsgnj_s(float %a, float %b) nounwind {
; RV64I-LABEL: fsgnj_s:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 524288
-; RV64I-NEXT: addiw a3, a2, -1
-; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
@@ -238,11 +238,11 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: lui a1, 524288
+; RV32I-NEXT: slli s0, s0, 1
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: addi a2, a1, -1
-; RV32I-NEXT: and a2, s0, a2
+; RV32I-NEXT: srli s0, s0, 1
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: or a0, s0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -256,11 +256,11 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: slli s0, s0, 33
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: addiw a2, a1, -1
-; RV64I-NEXT: and a2, s0, a2
+; RV64I-NEXT: srli s0, s0, 33
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: or a0, a2, a0
+; RV64I-NEXT: or a0, s0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -287,9 +287,8 @@ define float @fabs_s(float %a, float %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: lui a0, 524288
-; RV32I-NEXT: addi a0, a0, -1
-; RV32I-NEXT: and a0, a1, a0
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -301,9 +300,8 @@ define float @fabs_s(float %a, float %b) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: lui a0, 524288
-; RV64I-NEXT: addiw a0, a0, -1
-; RV64I-NEXT: and a0, a1, a0
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
index c310ee8e316717..51df36f5eee05d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
@@ -722,17 +722,15 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s_i16:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV32IF-NEXT: lui a1, 16
-; RV32IF-NEXT: addi a1, a1, -1
-; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: slli a0, a0, 16
+; RV32IF-NEXT: srli a0, a0, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_i16:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
-; RV64IF-NEXT: lui a1, 16
-; RV64IF-NEXT: addiw a1, a1, -1
-; RV64IF-NEXT: and a0, a0, a1
+; RV64IF-NEXT: slli a0, a0, 48
+; RV64IF-NEXT: srli a0, a0, 48
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_i16:
@@ -740,9 +738,8 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __fixunssfsi
-; RV32I-NEXT: lui a1, 16
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
@@ -752,9 +749,8 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi
-; RV64I-NEXT: lui a1, 16
-; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
index 210bcc7d4c10f0..35c7fdfb33fe44 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-intrinsics.ll
@@ -602,16 +602,14 @@ define float @fabs_f32(float %a) nounwind {
;
; RV32I-LABEL: fabs_f32:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a1, 524288
-; RV32I-NEXT: addi a1, a1, -1
-; RV32I-NEXT: and a0, a0, a1
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fabs_f32:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: and a0, a0, a1
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: ret
%1 = call float @llvm.fabs.f32(float %a)
ret float %1
@@ -695,8 +693,8 @@ define float @copysign_f32(float %a, float %b) nounwind {
; RV32I-LABEL: copysign_f32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
-; RV32I-NEXT: addi a3, a2, -1
-; RV32I-NEXT: and a0, a0, a3
+; RV32I-NEXT: slli a0, a0, 1
+; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
@@ -704,8 +702,8 @@ define float @copysign_f32(float %a, float %b) nounwind {
; RV64I-LABEL: copysign_f32:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 524288
-; RV64I-NEXT: addiw a3, a2, -1
-; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: slli a0, a0, 33
+; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
@@ -970,63 +968,61 @@ define i1 @fpclass(float %x) {
;
; RV32I-LABEL: fpclass:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a1, 524288
-; RV32I-NEXT: lui a2, 522240
+; RV32I-NEXT: lui a1, 522240
+; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: lui a3, 2048
; RV32I-NEXT: lui a4, 1046528
-; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: addi a3, a3, -1
-; RV32I-NEXT: and a1, a0, a1
-; RV32I-NEXT: addi a5, a1, -1
+; RV32I-NEXT: addi a5, a2, -1
; RV32I-NEXT: sltu a3, a5, a3
; RV32I-NEXT: lui a5, 520192
-; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: add a4, a1, a4
+; RV32I-NEXT: xor a0, a0, a2
+; RV32I-NEXT: add a4, a2, a4
; RV32I-NEXT: sltu a4, a4, a5
-; RV32I-NEXT: xor a5, a1, a2
-; RV32I-NEXT: sltu a2, a2, a1
-; RV32I-NEXT: seqz a1, a1
+; RV32I-NEXT: xor a5, a2, a1
+; RV32I-NEXT: sltu a1, a1, a2
+; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: seqz a5, a5
; RV32I-NEXT: and a3, a3, a0
-; RV32I-NEXT: or a1, a1, a5
+; RV32I-NEXT: or a2, a2, a5
; RV32I-NEXT: and a0, a4, a0
-; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: or a0, a2, a0
+; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: or a0, a1, a0
+; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fpclass:
; RV64I: # %bb.0:
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: lui a2, 522240
-; RV64I-NEXT: slli a3, a0, 32
-; RV64I-NEXT: li a4, 1
-; RV64I-NEXT: lui a5, 2048
-; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: seqz a1, a0
-; RV64I-NEXT: xor a6, a0, a2
+; RV64I-NEXT: lui a1, 522240
+; RV64I-NEXT: slli a2, a0, 33
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: li a3, 1
+; RV64I-NEXT: lui a4, 2048
+; RV64I-NEXT: srli a2, a2, 33
+; RV64I-NEXT: seqz a5, a2
+; RV64I-NEXT: xor a6, a2, a1
; RV64I-NEXT: seqz a6, a6
-; RV64I-NEXT: or a1, a1, a6
+; RV64I-NEXT: or a5, a5, a6
; RV64I-NEXT: lui a6, 520192
-; RV64I-NEXT: srli a3, a3, 32
-; RV64I-NEXT: xor a3, a3, a0
-; RV64I-NEXT: sub a4, a0, a4
-; RV64I-NEXT: sltu a2, a2, a0
-; RV64I-NEXT: sub a0, a0, a5
-; RV64I-NEXT: addiw a5, a5, -1
-; RV64I-NEXT: snez a3, a3
-; RV64I-NEXT: slli a4, a4, 32
-; RV64I-NEXT: slli a0, a0, 32
-; RV64I-NEXT: srli a4, a4, 32
; RV64I-NEXT: srli a0, a0, 32
-; RV64I-NEXT: sltu a4, a4, a5
-; RV64I-NEXT: or a1, a1, a2
-; RV64I-NEXT: sltu a0, a0, a6
-; RV64I-NEXT: and a4, a4, a3
-; RV64I-NEXT: or a1, a1, a4
-; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: xor a0, a0, a2
+; RV64I-NEXT: sub a3, a2, a3
+; RV64I-NEXT: sltu a1, a1, a2
+; RV64I-NEXT: sub a2, a2, a4
+; RV64I-NEXT: addiw a4, a4, -1
+; RV64I-NEXT: snez a0, a0
+; RV64I-NEXT: slli a3, a3, 32
+; RV64I-NEXT: slli a2, a2, 32
+; RV64I-NEXT: srli a3, a3, 32
+; RV64I-NEXT: srli a2, a2, 32
+; RV64I-NEXT: sltu a3, a3, a4
+; RV64I-NEXT: or a1, a5, a1
+; RV64I-NEXT: sltu a2, a2, a6
+; RV64I-NEXT: and a3, a3, a0
+; RV64I-NEXT: or a1, a1, a3
+; RV64I-NEXT: and a0, a2, a0
; RV64I-NEXT: or a0, a1, a...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/119427
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